Note : Les descriptions sont présentées dans la langue officielle dans laquelle elles ont été soumises.
14S~ 7
Cross Reference to Related Patents and Patent Applications
U.S. Patent 3,614,740 issued October 19, 1971 for a DATA PROCESSING
SYSTEM WITH CIRCUITS FQR TRANSFERRING BETWEEN OPERATING ROUTINES, INTERRUP-
TION ROUTINES AND SUBROUTINES and assigned to the same assignee as the present
invention.
U.S. Patent 3,614,741 issued October 19, 1971 for a DATA PROCESSING
SYSTEM WITH INSTRUCTION ADDRESSES IDENTIFYING ONE OF A PLURALITY OF REGISTERS
INCLUDING THE PROGRAM COUNTER and assigned to the same assignee as the present
invention.
U.S. Patent 3,710,324 issued January 9, 1973 for a DATA PROCESSING
SYSTEM and assigned to the same assignee as the present invention.
U.S. Patent 3,999,163 issued December 21, 1976 for a SECONDARY
STORAGE FACILITY FOR DATA PROCESSING SYSTEM and assigned to the same assignee
as the present invention.
Canadian Patent Application Serial No. 314,183 filed October 25,
1978 for a CENTRAL PROCESSOR FOR PROCESSING VARIABLE LENGTH INSTRUCTIONS and
assigned to the same assignee as the present invention.
Canadian Patent Application Serial No. 314,184 filed October 25,
1978 for a CENTRAL PROCESS0R UNIT FOR EXECUTING INSTRUCTIONS WITH A SPECIAL
OPERAND SPECIFIER and assigned to the same assignee as the present invention.
--1--
: ' " "''; :''' .- ., ' '"'. ~ , ' ' " , '' ' ,' '~ ' ' ' ;' ',-
:: . . . ., ~ , ~ .. . .. .
:: . . :.. - .. . .. . ! ... . . .. .
` - :
S~'7
Canadian Patent Application Serial No. 314,209 filed October 25,
1978 for a CENTRAL PROCESSOR FOR PROCESSING SUBROUT~NE CALLING INSTRUCTIONS
and assigned to the same assignee as the present invention.
Canadian Patent Application Serial No. 314,182 filed October 25,
1978 $or a DIGITAL DATA PROCESSING SYSTEM and assigned to the same assignee
as the present invention.
Background o$ the Invention
This invention generally relates to digital data processing systems.
More specifically it relates the interconnection of various units in such a
system and the transfer of data among those units.
A digital data processing system comprises three basic elements:
namely, a memory element, an input-output element and a processor element.
The memory element stores information in addressable storage locations. This
information includes data and instructions for processing the data. The
processor element transfers information to and from the memory element,
interprets
83-204
. ~ ~
`7
Pg. 3
1 the incoming information as either data or instructions and
! processes the data in accordance with the instructions. The
input-output elements also communicate with the memoey element
in order to transfer input information to the system and to
obtain proc~ssed information from it.
O~er the years many different types of digital data
processing systems have been developed. However, this
development has been directed towara evolving new processor
elements with more efficient architecture, larger and faster
memory elements and more sophisticated input-output elements.
There has been little change in the technology involved in
transferring information among the various elements in the data
processing system. In fact, all the data processing systems of
which we are aware can be classified by the timing method that
they u5e. There are only two ti,ning categories: synchronous and
asynchronous timing.
Digital data processing systems that utilize
synchronou~ timing usually include a ma~ter clock that controls
all operations in all elements. This master clock generates
ti.~ing signals that con!trol operations in the processor element
and also in the memory and input-output elements that connect to
an interconnecting bus. As all the elements in the system are
synchronized to the master clock, the master clock frequency
: :, . , :: . . s ; ,. . .. . , - -.. . . .
`~:
83-204
.
" 1~145`~7
Pg. 4
must be set to operate in a way that is compatible with the
slowest element in the system. The transfer rates between
elements impose ultimate limitations on the speeds with which
the faster elements can operate. ThuS a slow transfer rate slows
the entire syste.n so that the system runs below the theoretical
efficiehcy of .nany of its component units.
Other digital data processing systems utilize
asynchronous timing over their interconnections. With
asynchconous ti.ning each element is feee to opeeate at its most
efficient rate. Typically two elements communicate with each
other when one ele.nent initiates a data tcansfer over an
interconnecting bus. Then the one element controls the bus to
the exclusion of all third elements in the system until the
other element acknowledges that the requested transfer has been
completed. Systems using asynchronous ti.ning tend to be somewhat
- faster than their counterpart synchronous systems because they
can make some transfecs at a greater rate than the sLowest
element in the system, while maintaining the ability to
communcicate more slowly with the slower ele.nents. However,
asynchconous transfecs do have drawbacks in some applications.
In some asynchronous systems, once a transfer operation has been
initiated, the entire bus is unavailable to any elements other
than the two involved in the transfer until that tcansfer is
:.,,.. , . . : , .: . . . .
... .. .. - ... ,:. - .. : : . :: .: .. :, -
Pg. 5
completed. Thus tcansfers involving slower elaments hold up
opecation of the faster elements and reduce their efficiencies
below their theoretical levels~
Despite the drawbacks of both synchronous and
a~ynchronous tcansfecs, most digital data processing systems
still are built soleLy acound either one or the other, but not
both timing schemes. The selection of one ovec the othec
appacently depends upon the predicted applications for the
digital data pcocessing system. Thus, in some applications
unacceptable operating speeds may be encountered while in othees
the speeds are acceptable.
c ~v~
q~ There is described in copending ~k Patent
3\~ 2_
Application Serial No. -(83 ~03) a digital data processing system
in which a synchronous bus interconnects the individual
ele,nents. Unlike prior systems, however, this system does not
extend the timing control exerted on the bus throughout all the
elements. Each element operates at its own maximum speed while
it is not connected to the bus. At the time that an element is
to make a transfer, it prepares to make the transfer in
synchronism with the bus. While this system greatly increases
the overall speed of com.nunications, by itself this does not
increase the overall transfer rate to the maxilnum potential
rate.
. , .
: . ~. . .. ~ ,. :
`' ` 1~45~7 83-204
,,
Pg. 6
Thecefore, it is an object of this invention to
provide a data pcocessing system in which the elements are
enabled to exchange information at very fast rates.
Anothec object of this invention is to provide a data
pcocessing system in which each element is enabled to opecate at
its most efficient speed without unduly delaying othec
information exchanges between elements.
Still anothec object of this invention is to pcovide a
data pcocessing system in which each element is enabled to
operate at its most efficient speed during a data exchange with
another data element without having to inhibit information
exchan3es with other e~ements completely.
S m__y_of___e_Inv__tion
In accordance with this invention, each transfec of
information between two elements in a digital data processing
system comprises two distinct tcansactions. Ducing a ficst
transaction one element sends a command over an interconnecting
bus to another element, the command specifying the data transfec
operation and that identifying the element that is sending the
command. If the transfec operation is to transfer infocmation to
the one element, the lattec celinquishes control over the bus
and allows other transactions among other elements in the
-
' :
~14S~7
system. ~hen the other element retrieves the requested information, it gains
control of the bus and sends that information onto the bus along with the
identification of the element that requested the information. The one ele-
ment responds to that identification`by accepting the information and thereby
completes the information exchange.
In summary, according to the present invention, there is provided
a data processing system including a first data means, a second data means
including at least one storage location, and transfer means including a
plurality of transfer channels for transferring information between said first
and second means: said first data means including means for transmitting onto
said transferring means one of a plurality of commands, each command having a
function portion for defining a transfer function to be performed, an identi-
fication portion for identifying said first data means and an address portion
for identifying a location m said second data means to or from which the
transfer of data is to occur~ said first~datameans transmitting the function,
identification and address portions onto corresponding function, identifica-
tion and address transfer channels in said transfer means, said second data
means including: command responsive transfer means responsive to a command
for transferring data between the location identified by the address portion
received from said address transfer channel and said transfer channel means~ -
identification means for storing the identification portion from said
identification channel that identifies said first data means, and control
means enabled by said transfer means for controlling a transfer in response
to signals from said identification means and said transfer channel means.
The invention will now be described with reference to the accompany-
ing d~awings, in which:
Fig. 1 is a block diagram of a digital data processing system con-
structed in accordance with this invention;
--7--
.. .. ... : - .. ,.. ..... ,~ , . . . .. .
'7
Figs. 2A through 2D pictorially depict data types that are
utilized in conjunction ~ith à specific embodiment of this invention;
Fig. 3 illustrates the lines and corresponding signals that con-
- stitute an interconnection for elements in the digital data processing system
in Pig. l;
Figs. 4A through 4K are graphs or timing charts that depict the
various clocking signals and timing intervals that synchronize transfers of
-7a-
~ 83-204
`7
P~. 8
information between the elements shown in Fig. l;
Fig. 5 is a diagram that depicts sequences of
transactions that can occuc between the elements shown in Fig.
3;
Fig. 6 is a detailed block diagram of the centcal
processor unit 10 shown in Fig. l;
Fig. 7 is a block diagra,n of the data paths within the
saI contcol shown in Fig. 6;
Fig. 8 is a detailed block diagram of relevant
portions of contcol logic shown in Fig. 7;
Fig. 9 is a timing diagram that is useful in
F,js.
understanding the operation of the SBI control shown in ~ 6
through 8 during a reading operation;
Fig. 10 is a timing diagram that is useful in
understanding the operation of the ciccuitry shown in Fig. 6
through 8 during a writing operation;
Fig. 11 is a block diagra,n of a me~ory controller and
memory array as shown in Fig. 1;
Fig. 12 is a block diagra,n of a portion of the memory
controller shown in Fig. 11;
Fig. 13 is a block diagram of another portion of the
conteoller shown in Fig. 11; and
Fig. 14 depicts registers that are utilized in the
~ 83-204
;7
Pg. 9
memocy controller shown in ~ig. 11.
D_sc_ietion of an Illustrative Embodimént
; ~eneral Dlscussion
i Data Pcocessinq System
. Refercing to Fig. 1, the basic elements of a data
processing system that embodies our invention comprises a
7 / 7~5
A central pcocessor unit 10, iP memory unit 11 and I/O units 12. A
synchronous backplane interconnection (SBI) 14 interconnects the
f s
central processoc unit 10, memocy~ 11 and I/O units 12.
The centcal processor unit 10 compcises an opecator's
console 15, an SBI interface and memocy cache circuit 16, an.
~,~c~, 7~
address tcanslation buffec~l7, an instcuction buffec ciccuit 18
and a data path and internal registec ciccuit 19. The S~I
intecface and memocy cache ciccuit 16 pcovides the necessacy
interfacing circuitcy for transferring information over the SBI
14 to the memory units 11 and I/O units 12. The circuit 16
receives all data fcom the memocy and all address translations
. from the buffec circuit 17. It includes an associative memory,
or cache. Each time data is wcitten into the cache memocy in the
circuit 16 fcom the data path and internal cegistec ciccuit 19,
that data is also wcitten into a cocresponding location in the
memory unit 11.
, : - .: . . . ::. .............. . . . ............... ~ . , ~
.
83-204
P9. 10
Tnis specific embodiment of the central pcocessor 10
operates with virtual addeesses. The address tcanslation buffer
circuit 17 converts the virtual addresses to physical addresses
which the .nemory cache circuit 16 uses eithec to determine
; 5 whether it contains data from the cocresponding location or to
initiate a transfer from the corresponding actual location in
the memory unit 11. The instruction buffer circuit 18 includes
means for storing instructions, or portions thereof, as they are
retrieved either from the cache memory directly or from the
memory unit 11.
The operator's console 15 serves as the operator
interface. It allows the operator to examine and deposit data,
halt the operation of the central processor unit 10 oc step it
through a sequence of program instructions. It also enables an
operator to initialize the system throu3h a bootstrap procedure
and pecform various diagnostic tests on tha entire data
processing system.
~",~s
In Fig. 1, the memory ~ 11 comprises two memory
controllers 20A and 208. Each memory controller connects to a
plurality of memory arrays. Specifically, me,no~y controller 20A
connects to memory arrays 21A while memory controller 20a
connects to memory acrays 21B. The opecation of the memory unit
11 is disclosed in detail later.
:
83-204
. ~
Pg. 11
Sevecal types of I/O units 12 ace shown. An I/O bus
adaptec 22 interconnects various input/output tI/O) devices 23,
such as teletypewciters, to the bus 14. The intecconnection,
operation an~ transfer of signals between the I/O bus adapter 22
and the I/0 devices 23 is disclosed in U.S. Patent 3,710,324.
Two othec I/O units 12 provide a secondacy stocage
facility for the data processing syste,~. They include a
secondary storage bus adapter 24 and a plurality of disk dcives
25. There is also shown a secondary storage bus adapter 26 and a
tape dcive 27. The interconnection of the secondary stocage bus
adapte~s 24 and 26 and their respective disk dcives 25 and tape
drive 27 is disclosed in the foregoing U.S. Patent 3,999,163.
As apparent iiiirom Fig. 1, the SBI 14 interconnects the
various units in the data processing system. In accordance with
this invention, the vacious ciccuits that connect to the SBI 14
interact ovec the SBI 14 in an extcemeLy efficient mannec. To
undecstand the transfec of infocmation between diffecent paics
of units connected to the SBI 14, it will be helpful ficst to
establish some definitions foc terms that have already been used
and that will be used throughout the cemaindec of this
descciption.
"Information" is intelligence used to control and
ptovide the basis for data pcocessing. It includes addcess,
, .. ;......... . , . ~ ~: ,, :. - . -,
83-204
,
Pg. 12
data, contcol and status information. "Data" includes
information which is the object of or result of processing.
Transfers of information between units in the data
peocessing system shown in Fig. 1 occur over the SBI 14 and
; 5 involve transfers of disccete information ite,ns. Each
information item has a characteristic size on the SBI 14. Other
elements may process information items having othec sizes. The
most elementary information item is a byte. In one specific
embodiment of the data processing system shown in Fig. 1, the
byte includes eight binacy digits loe bits). Fig. 2A depicts a
number of contiguous bytes. The next lacgec data item size is a
~s s/0~
"wocd". A "wocd"~compcises two contiguous bytes. As shown in
Fig. 2C, two contiguous wocds constitute a "longwocd". Two
contiguous longwocds constitute a "quadwocd" as shown in Fig.
2D.
`- The S8I 14 tcansfecs all the infocmation ln a longwocd
in pacallel. Figs. 2A thcough 2D collectively illustrate four
~uadwords. In the quadwocd shown in Fig. 2A, byte 0 is in the
least significant byte position while wocd 0 and longwocd 0 ace
in the least significant wocd and longwocd positions of 2B and
2C respectively. The following discussion assumes that
cocresponding alignments are maintained within the data
processing system. However, there is no requicement that any
.,
`
such alignments be maintained. Indeed, as described in
co-pending Canadian Application Serial No. 314,183, transfers may
occur without maintaining this alignment, as when a central
processor unit transfers a longword beginning at some other byte
boundary.
If two elements are to exchange information over the
SBI 14, at least two "SBI transactions" are necessary. During a
first SBI transaction, one element requests the information exchange
and transmits command and address information onto the SBI 14.
The other element, designated by the address information,
responds and prepares to complete the information exchange. This
completes a first SBI transaction. During a second SBI transac-
tion the information to be exchanged passes over the SBI 14.
A third SBI transaction for transferring still additional infor-
mation is also possible.
Each element that connects to the SBI 14 is called a
nexus. The specific system shown in Figure 1 includes six nexuses.
A nexus further is defined in terms of its function during an
exchange of information. During such an exchange, the nexus that
~0 transmits command and address information onto the SBI 14 is
called a "commander nexus". The unit which responds to that
:
.,, ~
- 13 -
, X~
S~ 7
command and address information is called a "responder nexus".
Thus, if the central processor needs to retrieve data from the
memory controller 20A, the central processor unit becomes a
commander nexus and transmits a read command and memory address
during a first SBI transaction. The memory controller 20A be-
comes a responder nexus when it receives and accepts the command
and address information from the SBI 14. During the second SBI
transaction the memory controller 20A transfers the requested
data back to the central processor unit 10.
A nexus also is defined as a "transmitting" or
"receiving" nexus. A transmitting nexus drives the signal lines
while a receiving nexus samples and examines the signal lines
during each bus transaction. In the foregoing example, the
central processor unit is a transmitting nexus during the first
SBI transaction and a receiving nexus during the second SBI
transaction. Similarly, the memory controller 20A is a receiving
nexus duringithe first bus transaction and a transmitting nexus
during the second SBI transaction. Similar transactions occur
for information exchanges between any two nexuses. However, the
memory controllers normally function only as responder nexuses
while central processor units normally function only as com-
mander nexuses.
Typical information exchanges with the central
` processor unit 10 over the SBI 14 involve data to be interpreted
in the central processor unit as instructions, operand
~ .,
-~, - 14 -
~i
., ~ .
,~
f~ 83-204
-~ P3. 15
specifiers and data. Othec transfees will toute data fcom the
central pcocessor unit back over the SBI unit 14 for transfer to
other elements, or units, connected to the SBI 14.
Likewise, the other units shown in Fig. 1 can initiate
information exchanges over t~e SBI 14. Typical exchanges would
include transfecs between one of the disk drives ~5 or tape
drive 27 and one of the memory units 11. The I/O devices 23 also
communicate with the memory controllers 11.
; Each of the memory controllers 20A and 20B and the bus
; 10 adapters 22, 24 and 26 contain various control registers. At
dLfferent times during the operation of the data processing
system, programs being executed by the central processor 10 may
transfer infor,nation directly to or from one of these control
registers over the SBI 14 without involving the memory
contcollers 20A or 20B. All these transactions over the SBI 14,
however, are basically the sa,ne because each control register
that connects to the SBI 14 has a memory address. More
~pecifically, the command-address infor.nation has the capability
-of addressing a predetermined number of memory locations. The
maximum value of this number depends upon the number of bit
positions in the address, and it defines the available memory
space as a number of bytes. A portion of the available memory
space is reserved for the storage locations in the memocy arrays
., ~
.
~ ~ 83-204
1~4~:~7
Pg. 16
21A and 21B. The re,naining available spaca is eeserved for these
contcol re~isters. Thus, each storage location in the data
processing system, whether it comprises a stocage location in a
memocy array or a control register has a unique memory address.
5~ This feature of the data processing system shown in
Fig. 1 eLi.ninates the need for input/output insttuctions. As a
cesult, the SBI interface and memory cache circuit 16 or any
other ~Lement connected to the SBI 14 can access any memory
location using the same basic operations as it would if one of
the memory units 11 were being accessed. Consequently, a
desceiption of infocmation exchanges between the SBI interface
and memory cache circuit 16 of the central processor unit 10 and
the memory controller 20A and one of the memory arrays 21A in
the memory units 11 essentialLy describes the information
exchanges between any other units connected to the SBI 14.
Variations or modiflcations required for a specific one of the
adapters 22, 24 and 26 will be based upon the specific function
of those adapters and will, based upon the following discussion,
be apparent to anyone of ordinary skill in the art.
ii. The S~nchronous Back~lane Interconnect ~SBIL 14
In accocdance with one specific embodiment of this
invention, the SBI 14 conveys a number of signals to and from
: .:. ~...... . . . . . ~. : . ,.. ::, .. .... ,~.. . .,,. .. . ::.. .
.. . .. , . . . . .. - . . - .
the various units that connect to it over corresponding
~ conductor positions. These conductor positions and signals can
I be listed in five classes:
1. arbitration;
2. information transfer;
3. response;
4. control;
' 5, interrupt request;
; All these signals are maintained in synchronism with
clocking signals that constitute some of the signals on the
control conductor positions. These clocking signals are shown in
Figure 4. Specifically, a clocking circuit utilizes signals from a
master clock (e.g., a clock generator 70 in Figure 6) to
generate a number of signals. Figures 4A and 4B depict
complementary TP signals that are designated as a TP-H signal
and a TP-L signal respectively. The clocking signals also
;, include quadrature-phase signals at half the frequency of the TP
`', signals. These are depicted as PCLK-H and PCLK-L complementary
.~
! clocking signals in Figures 4C and 4D and complementary clocking
signals PDCLK-H and PDCLK-L signals in Figures 4E and 4F. The
foregoing signals are clock signals that appear on conductors 30
~, of the SBI 14 shown in Figure 3.
¦ Each nexus includes circuitry for deriving the timing
,
, - 17 -
signals that are necessary to perform transactions over the SBI
14. As shown in Figures 4G through 4J, these signals include TOCLK
through T3CLK quadrature signals, each having a 25% duty cycle
at half the frequency of the TP signals. The leading edges of
the TOCLK through T3CLK pulses define TO through T3 clocking
times as shown in Figure 4K. Thç time interval between successive
TO times is called a bus cycle time. GeneralIy, a transmitting
nexus transfers information onto the SBI 14 at a TO time. A
receiving nexus samples the SBI 14 at a T3 time. In one specific
embodiment of this invention, the interval between successive TO
times is about 200 nanoseconds.
As will now be apparent, each nexus that connects to
the SBI 14 can transfer information over the SBI 14. Some means
to control access to the SBI 14 must therefore be provided. The
arbitration signals on ARBITRATION~TR) conductors, or lines, 31 in
Figure 3 provide this control function. Each nexus has a predeter-
mined bus access priority assigned to it. In this specific embodi-
ment, there are sixteen arbitration lines that are designated
¦ respectively as TR00 through TR15 lines. The TR00 signal
constitutes a HOLD signal and connects to every nexus. Each of
I
the TR01 through TR15 lines has assigned to it a priority. The
highest priority nexus transmits an access control signal on the
TROl line and the second lowest priority nexus transmits another
- 18 -
'
'
,
83-20~
~` .
L7
P3. l9
access conteol signal on the TR15 line. The lowest pciority
nexus does not transmit any access conttol signal. Each nexus
cesponds to access contcol signals from nexuses that have
priorities that are higher than the pciority assigned to that
nexus and to the HOLD signal.
A When a nexus~ othec than the nexus having the lowest
priority, such as the nexus 32 shown in Fig. 3,desires to gain
access to the SBI 14, it conditions an arbiteation circuit 33A
to transmit its access control signal on its assigned TR line at
a T0 time. At the next T3 ti,ne, the arbitration circuit 33A
samples all the access control signals from higher priority
nexuses and the HOLD signal. If such an access control signaL or
the HOLD signal is baing transmitted, the nexus 32A continues
sampling the access control signals at each successive T3 time .
until no access control signal from a higher priority nexus or
the HOLD signal is received. When, at a T3 time, no such signals
are received, the arbitration circuit 33A enables the
information transfer circuit 56A to begin transmitting
information tcansfer signals at the following T0 time.
As previously indicated, the lowest priority nexus
transmits no access control signal, but it receives all the
access control signals and the HOLD signal. If this nexus wishes
to gain access to the SBI 14, it can do so provided at a
- :: . ., .. ., .. : . -. , , . , . .. ~ . , ,
:
1'1145:~7
particular T3 time none of the access control signals and the
HOLD signal is received. It is not necessary for this nexus to
delay its first sampling of the TR lines. Consequently, this
nexus actually has shortest access time to the SBI 14. For that
reason the central processor unit 10 normally is assigned the
lowest priority in the digital data processing system.
The information transfer signals and their
corresponding lines 34 are grouped in four subgroups. They
- include (1) parity check lines 35, ~2) information tag ~TAG?
lines 36, ~3) identification ~IO) lines 37, and ~4) information
lines 40.
There are two parity check lines 35. A PO line car-
ries a parity signal for the signals on the tag lines 36, ID lines
~ i
:1 37 and mask lines in the information lines 40. A Pl line carries
:js parity for the signals on the other information lines 40.
: ~.
;~ The tag signals are generated by a tag circuit 60A in
transmitting nexus. They control the interpretation of the
signals on the ID lines 37 and the information signals 40 by ID
and information circuits 57B and 56B. There are four general
. ,. ~
;) 20 types of information that are carried over the information lines
' 40. They include read data, command-address, write data and
:,................................................ . .
interrupt summary read information. A set of tag bit values that
correspond to each of these types control the interpretation
given to the mask signals on the information lines 40 by the
~ i
,~ i
. . .
- 20 -
''.: X
:
information circuit 56B. For example, if the tag signals specify
that the information is data that has been read from some
location, the mask bits can be interpreted to indicate whether
the data is actual data, corrected data or substituted data.
When the tag bits specify that the information on the
information lines 40 constitutes data to be written into some
location, the mask bits specify which of four contiguous bytes
in the addressed longword location will be written.
When the tag bit value specifies that the information
of the information lines 40 constitutes a command and address,
the information is divided into two fields. A first field is a
function field; the second, an address field. The function field
specifies different types of reading and writing operations to
be performed by the responder. The mask bits may or may not be
i used with lndividual ones of these operations.
There are six basic operations which the function
field can define; and they include (1) a masked reading opera-
tion, (2) an interlocked masked reading operation, (3) an ex-
tending reading operation, t4) a masked writing operation,
(5) an interlocked masked writing operation and (6) an extended
masked writing operation. With the exception of the extended
reading operation, all these operations utilize the information
in the mask field.
Response lines 41 include a fault line 43 and two CNF
- 21 -
~s~
~r
~ 83-204
Pg. 22
lines 44. Whenever a transmitter nexus transmits infocmation on
the SBI 14 during a bus cycle, the receiving nexus that decodes
the address and, two bus cycles latec, tcansmits a confirmation
of the proper receipt of that information. Each nexus samples
5~ the signals on the SBI at the T3 ti,ne of each successive bus
cycle. Therefoce, each tcansmitting nexus must include ciccuitry
for distinguishing those confirmation signals that are in
response to each of its transmissions.
rhe confirmation lines 44 may define one of four
states: namely an unasserted state that indicates no response or
selection; an acknowledge IACK) state as a positive
acknowledgment to a transfer; a busy state in response to a
successfuL selection of a nexus that is presently unable to
re~pond further to the command; and an error state when a
successful selection of a nexus has been made but the nexus
cannot execute that type of command.
The FAULT line 43 caccies a FAULT signal that indicates
whether any information path parity ercoc, wcite sequence ecror
or other error conditions exist.
Control lines 45 include the the clock lines 30 as well
as four other control lines.
An UNJAM line 46 in the central line~ 45 carries a
signal from the central processor unit 10 that establishes an
~,
~ .
.. .... , . .. . . , , ; , ~ ., . .. ~ .. ~ . .
83-204
'aJ
Pg. 23
initial condition in all the other elements and the UNJAM signal
; theceby constitutes a system initializing signal.
A FAIL signal on line 47 is asserted by a nexus if it
i is an essential element in the data processing system and its
power is failing. The central processor unit 10 is the only
naxus that recognizes a FAIL signal.
A DEAD signal on line 50 is asserted whenevec an r
impending power failure in the clocking or SBI terminating
netwocks is detected. It is equivalent to a DC LO signal in a
data processing syste~.
, ~
A ~ INTERLOCK signal on line 51 coordinates vacious
,. .
, nexuses eesponding to interlocked reading and writing
opecations. When a com.~anding nexus ttansmits infocmation
including an interlocked reading command during a first bus
cycle, it transmits the INTERLOCK signal ducing the next bus
cycle. The responding nexus transmits the INTERLOCK signal
during the succeeding bus cycle. It will continue to transmit
the INTERLOCK signal until it receives an interlocked masked
wciting command and tcansmits a corresponding a positive
confirmation. Tha INTERLOCK signal then is terminated.
A final group of lines 52 carries INTERRUPT REQUEST
signals. These signals are generated by nexuses which must
~ignal the central processing unit 10 to respond to some
.
. . . -, : - , . : . ,~
~ 83-204
5~7
P~. 24
condition, such as the completion of a data transfer by one of
", ~j, ~ .
A the sacondary stocage bus adapters 24 or 26~ The INTERRUPT
REQUEST lines ~ are assected in synchronism at the T0 time.
When the central processor unit l0 cesponds to an INTERRUPT
REQUEST si~nal, it tcansmits an inteccupt summacy cead command
that designates one intereupt request line. A nexus that
ceceives the interrupt sum,nary read command and is asserting the
corresponding int~rrupt cequest line transmits ONES in the
pceassigned bit positions of the longwocd in the information
field at the same time that it transmits its CNF signals. No
other sign~ls are transmitted. These signals unique1y identify
the requesting nexus and enable the central processor unit l0 to
cespond. No other transactions can occuc over the SBI during
such a ttansaction because the central processor unit l0 assects
the HOLD signal on the TR00 line foc both the bus cycle during
which it transmits the inteccupt summacy read command and the
following bus cycle. The centcal pcocessoc unit l0 then can
respond to the condition that caused the intecrupt.
If a nexus does not contain an intercupt mechanism,
such as the memory contcollec 20A, it may still be necessary to
alect the centcal processing unit l0 to some change in its
condition. If such a change occurs, such a nexus generates an
ALERT signal on the line 54. The central processing unit l0
,. , . : . , -. . .-, .: . .... ~
,, ., ., . . ., : .,, .:, .. .. .., . , .: . .
... . . ~ . . . .. .. . .
-~ 83-204
Pg. 25
responds to the ALERT signal.
With this knowledge of the vacious signals that are
transmitteZd over the SBI 14, it will now be possible to use .-~
Figs. 3 and 5 to describe generally several selI tcansactions
that illustrate the efficiency of a data pcocessing syste.n
utilizing elements that connect to the SBI 14. The SBI 14 is a
time-division multiplexed intecconnection. As appacent fcom the
foregoing discussion, a memocy exchange involves at least two
transactions. A first transaction invoLves the tcansfer of
Z 10 com,nand and a~dcess infocmation; a second and any following
transactions involve the tcansfer of data. The same lines are
,.j
used for all transactions, and the meaning given to the
information on the information lines 40 ducing each tcansaction
is determined by the signals on the tag lines 36.
.~
Fig. 5 depicts several sequences that might occuc
,.,
between sevecal nexuses including the nexus 32A and the nexus
32B, assuming that the nexus 32B includes one of the memory
conteollecs. The nexus 32A could be the I/0 bus adaptec 22 oc
one of the secondacy stoeage bus adaptecs 24 and 26.
Initially, the acbitcation ciccuit 33A ceceives a
signal fcom other ciccuitry indicating that the nexus 32A is
pcepaced to transfer data to the nexus 32B. At each T3 time
theceaftec, the acbitcation ciccuit 33A samples the arbitcation
:.
. ' ' 'J ~ .. ' ' ''` ' ' ' - ~ ' ' "
~ 83-204
Pg. 26
lines until it receives control of the SBI 14. In Fig. 5 the
- arbitration circuit 33A samples the arbitcation lines 31 and
finds no access conteol signal of higher priority or the HOLD
1 signal on the TR lines at the T3 time during bus cycle 1.
., .
At the completion of the bus cycle 1, circuitry
including the information circuit 56A and ID circuit 57A, a tag
;i,
k circuit 60A and a parity circuit 61A transmits,during bus cycle
2, appropriate signals onto information transfer lines 34. These
include write command signals and address signals from the
information ciccuit 56A for identifying a location in the
information circuits 56B, signals identifying the nexus 32A from
' the ID circuit 57A and signals from the tag circuit 60A
specifying that the information lines 40 have command and
address information. The parity circuit 61A generates the
appropriate parity. If the writing colnm~nd is to be followed by
data, called "write data", during the next bus cycle, the
arbitration circuit 33A also tcansmits the HOLD s~gnal on the
TR00 line during bus cycle 2 thereby to prevent any higher
priority nexus from assuming control over the information
transfec lines 34 during bus cycle 3. During bus cycle 3,
nothing occurs with respect to SBI sequence "n". On the second
following bus cycle li.e., bus cycle 41, a CNF circuit 63B in
the nexus 32B transmits a positive confirmation Idesignated as a
!`~
_~ 83-204
l~lg~ L~
P3. 27 ;~
- MEMORY ~CK) over the CNF lines 44, assu.ning that the infocmation
` received during bus cycle 2 by the nexus 32B was without eccoc.
This completes SBI sequence "n" foc transfeecing a masked oc
inteclocked ~asked writing com,nand and addcess; this transaction
cequiced four consecutive bus cycles. Ducing bus cycle 3, the
nexus 32A stops tcans.nitting the wciting com,nand and addcess
infor.nation and tcans.nits, fcom the infocmation ciccuit 56A, the
wcite data. Aftec the nexus 32B receives the wcite data ducing
bus cycle 3, it waits until bus cycle 5 to tcansmit the
',!10 corcesponding MEMORY ACK. This completes SBI sequence "n+l". The
cesponding nexus ,nodifies only the byte positions specified by
the byte mask tcan~ferred with the co.nmand and address.
Fcom the focegoing descciption it will be appacent
that the wciting opecation requices two separate tcansactions.
15 - Moreover, each transaction requires four successive bus cycles.
However, the sequencing and timing of the tcansactions of the
SBI 14 ceduces the ducation of this wciting operation to five
bus cycles, rathec than eight.
If the nexus 32A were pcepaced to issue an extended
eeading command and no othec nexus of highec priocity was
transmitting its access conteol signal and the HOLD signal was
not being tcansmitted ducing bus cycle 3, the nexus 32A could
transmit the command and addcess infocmation on the infocmation
~ ' .
- -
S~7
transfer lines 34 during bus cycle 4. The MEMORY ACK
confirmation for this transaction, bus sequence, "n+2" in Fig-
- ure 5, would not be sampled at the commander nexus 32A until bus
cycle 6. An extended reading operation causes responder nexus
32B to obtain a quadword beginning at the location specified by
~, the address signals. However, a quadword includes two longwords,
.~ and the information lines 34 only transfer one longword in parallel.
Thus, the nexus 32B interprets the extended reading command and
prepares to perform two successive transactions on the SBI14.
At this point, it would be possible to inhibit any further ~-
,
transactions over the SBI 14 by any other nexus~. However, in
accordance with this invention, the nexus 32A relinquishes its
control of the SBI 14, so another nexus can take control. This
release enables a secondary storage element, for example, to con-
trol the SBI 14 and transmit an extended writing command during
bus cycle 5. As described later, this command normally will spec-
ify one of the memory controllers 20A and 20B in Figure 1. If it
were directed to the same memory controller that received the
extended reading command, the memory controller 20A would still
accept the command and subsequently accept the transmitted write
data because each memory controller contains a command file
which stores sucaessive commands and write data items that are
transferred to it as described later.
- 28 -
,~, ...
~;~
83-204
15 ~45~7
Pg. 29
As pceviously indicated, any weiting operation may be
followed in successive bus cycles with the write data to be
written, so the secondary stora~e element, as a commander nexus,
asserts the HOLD signal during bus cycles 5 and 6 and transmits
the write data during bus cycles 6 and 7. Thus, an extended
writing operation requires three successive transactions that
are shown as bus sequences "n+3" through "n+5" in Fig. 5. They
extend only over an interval of six bus cycles.
/ef~o~ ~4 f~
A Assuming that upon/transfer of the writing command and
address information and the write data, the nexus 32B were ready
to ceply to the pcior extended reading com.nand, it would be in a
position to take control of the bus and transmit the first read
data item onto the information transfer lines during bus cycle 8
as part of SBI sequence "n+6". As an extended reading operation
is being performed, the nexus 32B asserts the HOLD signal during
bus cycle 8 to guarantee that it can send the second read data
item during SBI sequence "n+7". The nexus 32A decodes its ID
code on the ID lines 37 ana the read data function on the tag
lines 35 and accepts the read data items at the T3 times during
bus cycles 8 and 9. The nsxus 32A transmits it confirmation,
depicted as a NEXUS ACK in Fig. 5, over the CNF lines 44 during
bu3 cycles 10 and l1 so the nexus 32B "knows" that no
transmission error conditions exist.
`~'` ,'`, . , : ~` , " :. , `. ' ,' ` ``, , ' ~ `
" 83-204
:~`
5~7 p~,. 30
Fcom the focegoinq descciption, it can be seen that
the ciccuitcy shown in Fig. 3 and the opecation in Fig. 5 enable
tcansfecs over the SBI to be conducted vecy efficiently. As can
be seen by looking at any specific one of the bus cycles 1
thcough 11, diffecent groups of lines that constitute the SBI 14
ace involved with diffecent bus sequences oc tcansactions at the
same ti~e. Foc example, ducing bus cycle 6 the HOLD signal is
assected for bus sequence "n+5". Simultan20usLy, the information
transfer lines 34 are conveying the wcite data foc SBI sequence
Hn+4", and the eesponse lines 41 are conducting conficmation
signals foc SBI sequence "n+2". Moceover, the control of the SBI
14 enables eight transactions, that each requice fouc bus cycles
to complete, to be completed within 11 bus cycles, cather than
thirty-two bus cycles. It is the focegoing timing and sequencing
of signals on the SBI which enable it to tcansfer data among the
elements in a digital data processing systzm in a highly
efficient mannec.
Although the extended ceading opecation begun in bus
cycle 3 was not completed until bus cycle lI, the associated
release of the SBI 14 allowed a completely diffecent tcansaction
during bus cycle 5. Thz reading opecation thecefore did not
; inhibit other tcansfecs ovec the SBI 14 while the nexus 32B was
retrieving the cead data. It was only when the nexus 32B had the
L
.. ..
~ 83-204
- ~
~ .45117 Pg. 31
data items ready for transfer that it took control of the SBI
14.
S~ecific Descrietion
i~ Central Processor Unit 10
AS shown in Fig. 6, the central processoc unit 10
includes the operator's console 15, the SBI 14 and the other
circuits that constitute the SBI interface and .nemory cache
circuit 16, the address translation buffer circuit 17 and the
, ~ o~ f,~ ~
, ~ instruction buffer citcuit 1~ More speci~icalLy, the central
processor unit 10 operates under timing established by a clock
generator 70 that not only provides the intarnal clocking
signals but produces the TP~ PCLK and PDCLK clocking signals
that are transmitted onto the SBI 14. The SBI interface and
memory cache circuit 16 comprises an SBI control circuit 71 that
connects to the SBI 14 and to a physical addcess I PA) bus 72.
The PA bus 32 connects to a data cache circuit 73 and to a
translation buffer 74. The translation buffer 74 converts
virtual address ~VA) information and other control information
into a physical address that is transmitted simultaneously to
the SBI control 71 and data cache 73. Data from the data cache
73, or fro.n ~ny other location on the SBI 14 that passes through
the SBI control 71, is conveyed to other elements in the centr~l
processor unit 10 over a memory data I MD) bus 75. These units
~;
~, ; ,,, .. ,: ,~
- 83-204
S~7
: P9. 32
include a data paths circuit 76 and an instruction buffer and
decode ciccuit 77.
A microprogram control IUPC) bus 78 conveys signals
from the instruction buffer and decode circuit 77 to a program
control stoce 80. The pcogram controL stoce 80 then generates
various contcol signals onto a CS bus 81, and this bus conveys
signals to the translation buffer 74, the data paths 76, the
instruction buffer and decoder 77 and a traps-interrupts
arbitrator circuit 82. These ciccuits and the operator's console
15 communicate over an instruction data IID) bus 83 with a
microsequencer 84 that controls the sequence of operations in
response to microinstructions stored in the program control
store 80.
The microsequencec 84 establishes a retrieval state
., ~4
~ 15 for obtaining an instruction. ~ff~ program counter, which
.I specifies the address of the next instruction to be retrieved
from one of the memory units 11, passes from data paths ciccuit
.~ 76 throu~h the tcanslation buffer 74 onto the PA bus 72. If the
data cache 73 cantains valid infoelnation in a location
corcesponding to the specified physical address, it transmits
data over the MD bus 75 to the instruction ~uffer and decode
circuit 77. The microsequencer 84 establishes other data paths
: . that transfer other information to the translation buffer 74
,,
.
~, , ,., :.: .,, , .. 1 ~ , .,, , ', . ,., .. , ! .......... . .
1~L145~7
:` `
thereby to transfer other data into registers in the data paths
circuit 76 from either the data cache 73 or, after a retrieval
from the memory units 11 or other memory locations on the SBI
14, the SBI control 71. If the instruction requires data to be
- transferred to a physically addressed location, the micro-
sequencer 84 establishes the data paths that are necessary
to transfer signals to the translation buffer 74 thereby to form
the physical address and to transfer the data simultaneously to
the data cache 73 and to the SBI control 71. During any such
transfer the SBI control 71 initiates an exchange with the
specified memory location.
As shown in Figures 6 and 7, the SBI control 71 connects
to the PA bus 72, the MD bus 75, the ID bus 83 and the SBI 14.
If access is made to the data cache 73 in Figure 6 and the data
cache 73 does not contain the requested data, a "miss" condition
exists. A read-write condition circuit 91, shown in Figure 8,
asserts a STALL and conditions a RAISE TR flip-flop 92 to be set
at a subsequent SBITl time. This signal is shown as a zero asser-
tion signal in Figure 9. The general relationship between the
timing of the central processor unit 10 and of the SBI 14 is
shown in Figures 9 and 10. In the following discussion, the prefix
"SBI" designates SBI times; the prefix "CP", central processor
unit times. Figure 9 discloses cycle times bounded at CPT0 times.
.,
:, .
- 33 -
.
~ 83-204
5~
Pg. 34
During the first cycle time, the microword from the
miccosequencer 84 produces a reading signal and places the
physical addeess on the PA bus 72. If the data cache does not
contain the information, the fLip-flop 92 sets at the next SBIT1
time and generates the RAISE TR FF signal. After a shoct ti,ne
delay, an OR gate 93 genecates a BUFFER FULL signal which can
also be genecated in response to othec signals such as the
assertion of a READ DATA FF signal by flip-flop 94 when the
nexus is in a receiving mode or an EXPECT READ signal from a
shift register 95 after a read data item has been received. So
long as a BUSY flip-flop 96 is cleared, the RAISED TR FF signal
energizes an AND gate 97 and an OR gata 100 theceby to generate
a RAISE TR signal.
- A pciority arbitration circuit 101 asserts an ARB OK
signal at an SBIT3 time so long as (1) no incoming highee
priority access control or HOLD signals on the TR Lines are
asserted, (2) the AND gate 102 is energized by the RAISE TR
signal from the OR gate 100 and 1`3) the ARB OK signal is not
then asserted. The arbitration circuit 101 clocks the incoming
signal from the AND gate 102 in coincidence with the SBIT0 and
transmits a MY TR signal.
At the SBIT2 time, a latch 103 is set if the RAISED TR
signal is asserted thereby to energize an AND gate 104 and
83-204
~ 1~5~7
Pg. 35
generate a TRANSMIT CA signal. The TRANSMIT CA signal indicates
that com.nand-address information is to be sent, and this signal
is applied to seveeal other circuits. For exa~ple, this signal
` contcols the transfer of the address from an addcess register
- 5 120 in Fig. 7 through a teans~itting multiplexer 121 and data
A transceivers 115~onto the SBI 14. The BUSY flip-flop 96
~; responds to the TRANSMIT CA signal by setting at the next SBIT1time which disables the OR gate 100 and RAISE TR signaL. Then
the flip-flop 103 is cleared at the next SBIT3 time and
ter.ninates the TRANSMIT CA ~ignal. The BUSY signal and a RESET
BUSY signal energize reset logic 106 that establishes an initial
condition in a timing shift cegistec 107 that produces TIMING
PULSE 0, 1 and 2 during successive cycles, the timing pulses
changing at the SBIT2 times. This completes the transmission of
; 15 the command-address information.
The shift register 107 acts as a state control and
enables the CNF circuit 63 to monitor the CNF Lines 41 at the
approtiate time or times. When a positive confiemation is
received, the shift register 95 is loaded with an ANY READ
æa~c~ccr ~
output from a sequence decodec 108 that cesponds to a _cqucncc
109 by generating the ANY READ signal when the command-addcess
information defines any of the ceading operations. Thus, at the
next 5BIT1 time, the shift registec/wi11 assect an EXPECT READ
'' .
. .
~ 83-204
4S~
P~. 36
signal that enecgizes the OR gate 93 thereby to maintain the
BUFFER FULL signal at an asserted level.
When the responder nexus has retrieved the requested
data items and gains control of the SBI 14 and transmits the
data item and other information, a comparatoc 110 and nexus ID
A circui ~ that form part of the ID circuit 57, coact to generate
a MY ID signal when the incoming ID signals on the SBI 14
correspond to the signals from the NEXUS ID circuit 111. If the
~ signals indicate that the information is read data, no
parity errors are detected and the commander nexus has not timed
~ ef ~ fe~
out waiting for a response, an AND gate 112 will generate an ANY
READ DATA signal. At the next SBITl time, the flip-fLop 94
generates the READ DATA FF signal that enérgizes the OR gate 93
and conditions a flip-flop 113 to be set at the next SBIT2 ti.ne
thereby to enable a decoding circuit 114 to produce a WANTED
DATA signal. The WANTED DATA signal enables the condition
circuit 91 to disable the STALL signal at the next SBIT0 time.
At the time that the READ DATA FF signal shifts to an
asserted state, it also enables the control logic 90 in Fig. 7
to control the transfer of data from a data transceiver l15 and
read data register 116 to be diverted to the MD bus 75 thcough a
driver circuit 117. It also will be apparent that the incoming
data could be routed through the data transceiver 115, an SBI
:
,
- : . : : . . - .. : , . : -
~ 83-204
'1~ '7
pg. 37
silo ciccuit 122, an ID bus multiplexec 123 and A dciver circuit
124 onto the ID bus 83 foc diagnostic purposes.
Fig. 9 depicts the timing for an extended reading
operation. As shown, the responder nexus initiates a bus
transaction during the cycle designated "MEMORY TR" and
transfers a read data item during the next bus cycle. The
responder nexus also trans.nits the HOLD signal during the same
bus cycle that it transmits the first read data item so it can
transfer the second read data item on the subsequent bus cycle.
Fig. 10 depicts the timing sequence for the signals
that are generated during a writing operation. For this transfer
the microsequencer 44 issues a writing command and provides the
addcess and data items over the PA bus 72 and MD bus 75
respectively. The flip-flop 92 then asserts the RAISE TR FF
signal and causes the OR gate~to assert the 8UFFER FULL signal.
At the next SBIT1 time, the BUSY flip-flop 96 sets and the reset
logic 106 then enables the state counter 107. Fouc timing pulses
are generated for a writing operation involving only one
longword. These pulses define the command-address ti,ne, write
data time and two acknowledgement times respectively. When the
second acknowledgement signal is received over the CNF lines 44,
the RAISE TR FF, BUFFER FULL and BUSY signals are terminated. It
will also be apparent from Fig. 10 that the data item is
. .
j 83-204
P~. 38
simuLtaneously written into the cache memocy at the beginning of
the opecation.
ii Memory Units 11
With this undecstanding of the basic constcuction and
opecation of an SBI control circuit, such as the SBI contcol
ciccuit 71 in Fig. 6, opecating as a co,nmandec nexus in both the
tcansmitting and ceceiving states, we now will describe the
operation of a memory controller as a responder nexus.
Memory controller 20A and one arcay 21A are shown in
Fig. 11 as a typical memory unit. The memocy controller 20A
includes a memory-SBI interface circuit 200 that contains .nany
of the circuits shown in the nexus 328 in Fig. 3. This intecface
200 connects through a FILE bus to a contcol and timing circuit
201 and a data path circuit 202. A CONTROL bus from the contcol
and timing ciccuit 201 intecconnects vacious memory array
sections 203 while a DATA bus intecconnects the memory array
sections 203 and the data path circuit 202.
Referring to Fig. 12, the SBI interface circuit 200
comprises a number of drivers and receivers in an SBI interface
204 that connect to the SBI 14 dicectly. Othec poctions of the
me.nocy SBI interface 200 include circuits for responding these
signals and for generating appropciate signals onto the SBI 14.
. ",
''
.. .. , , ., : : . .: .. . - . .. : . -
~$~ 7
Before describing the operation of this memory
controller and array, it will be helpful to describe the
function of specific circuits that are shown in Figures 12 through
14. Still referring to Figure 12, a parity check circuit 205,
included in the parity circuit 61 assuming the nexus 32B
corresponds to this memory controller, receives the parity and
all other signals from the SBI interface 204 and monitors for
any parity errors. Response logic circuit 206 corresponds to
the CNF circuit 63B and the FAULT circuit 62B; it transmits a
response in the form of a confirmation or error, as previously
described, no more than two bus cycles after the memory receives
, a command-address or write data.
The arbitration logic circuit 207 corresponds to the
arbitration circuit 33B and it, like the circuitry shown in
connection with the central processor unit, determines when the
memory controller 20A gains control of the SBI 14. This circuit
connects directly to the SBI 14.
Tag decode circuit 210 corresponds to the tag circuit
60B in Figure 3. It decodes the tag field of received information
on the tag lines 35 thereby to determine the nature of the
I signals on the information lines 40. The decoded tag is routed
`i to an address-data validity checking circuit 211 and the tag field
is routed to a command file 212.
- 39 -
83-204
.
1~145~7
Pg. 40
A function decode circuit 213 decodes the function
signals when command-address information is received from the
SBI 14. This circuit determines the validity of the function
signaLs by comparing them against the allowed function signals.
The functions bits also are transmitted to the addcess/data
validity check circuit 211 and the command file 212.
The address-data validity checking circuit 211
generates a VAL DAT signal when the parity check circuit 205
indicates that no parity errors exists, when the function decode
circuit 213 indicates that the function bits are valid and when
the destination address, function and other information all
indicate that the operation can be performed in the memory.
Circuitry in file control Logic 214, associated with the command
file 212, enables the information on the SBI intecface 204 to be
A 15 transfecred into the command file 212 and t~e write countec 252
to be incremented in response to the VAL DAT signal.
An acray address checking circuit 215 determines
whether the received address on the information lines 40 falls
within the range of memory locations that is associated with the
particular memocy controller. The circuit 215 also receives
; signals from a memory size encoding network 220, a chip-size
cocrection circuit 221 and an interleaving addtess correction
circuit 222. Circuits for checking incoming addresses against
.
:
~ 83-204
1~L145~7
Pg. 41
valid canges of memory Locations are well known in the art.
~/a/~ /Y
An I/O address~checking circuit 223 detecmines if the
address and selected function are valid for any control
registers that are included in the memory controller. In one
specific embodiment a memory controller includes three
configuration tegisters, that are shown schematically in Fig.
14, and a read-only memory.
Configuration register A in Fig. 14 includes an
interleaving information field 230, a subsystem field~that
lndicates the size and type of memory 232 and an enable write
intecleave field 233 that enables the inteeleave field to be
- wcitten. A size field 234 indicates the size of memocy stocage
connected to the memocy controllec. A power up flag 235 and a
, ,
powec down flag 236 indicate whether the me.~ory is undergoing
eithec one of the cocresponding sequences. Fault condition flags
237 including a tcansmit fault ITF), multiple tcansmittec fauLt
~MTF), interlock command sequence fault IICS), wcite data
sequence fault IWDS) and bus pacity ~BP) fault also ace
included~ The TF signal is generated if the memocy was opecating
as a transmitting nexus when a fault occurred. The MTF signal
indicates an ID check circuit 238 IFig. 12) detects ID signals
on the lines 37 (~ig. 3) that differ from the ID signals being
transmitted by an ID latch 239 at the time that the memory
~ - 83-204
S~7
Pg. 42
controller acts as a tcansmitting nexus. The ICS signal is
asserted when an interlocked masked writing co~mand is received,
but the INTERLOCK signal on the control line 51 is not asserted.
Interlocked exchanges require that the commander nexus issue a
interlocked masked reading command befoce the inteclocked masked
writing command is sent. The first command causes an interlock
flip-flop in the commander nexus to be set thereby to assect the
INTERLOCK signal. The WDS signal is asserted whenever any of the
; weiting commands is sent and not immediately followed by wcite
data during the subsequent bus cycle. The BP signal is asserted
whenever a parity error is detected.
Still referring to Fig. 14, configuration register B
contains information for testing the error checking logic and
memory status. It includes a force check bits field 240 used for
forcing error corrections and a FOR field 242 to force an error~
at a predeter~ined address.~ECC field 241 is used to disable the
ECC ciccuit. An INIT STAT eield 243 indicates whether the memory
data is valid, the memoey is in the process of initializing or
~ initialization is complete. An EWSA field 244 enables a memory
starting addcess fiPld 245 to be altered. The memory starting
address, as the name implies, identifies the first location in
the memory. A file fullness field 246 indicates whether the
command file 212 in Fig. 11 is full.
.,
1~ 7
Still referring to Figure 14, configuration register C
contains error syndrome, error address and other fields that are
used in indicating corrected data if certain types of errors
occur.
Referring again to Figure 12, an address generator 250
generates memory reference addresses in response to the
addresses received from the SBI 14 and the starting address
signals from configuration register B, identified by reference
number 247 in Figure 13.
A command/address destination decode circuit 251 uses
the incoming address signals from the SBI 14 to select the
appropriate section in the memory. As previously indicated,
these address signals may identify a location in an array
section 203 ~Figure 11), one of the configuration registers (Fig-
ure 14) or read-only memory 248 in Figure 13 that is used to ini-
tialize the system. The circuit 251 decodes the incoming address
signals to select one of these storage locations.
Still referring to Figure 12, the file control logic 214
monitors the amount of space in the command file 212. It
includes a write counter 252 and a read counter 253. A differ-
ence decoder 254 monitors both counters 252 and 253. As de-
scribed later, a room-in-file comparator 255 indicates whether
additional information can be loaded into the command file 212
- 43 -
;~ 83-204
P~. 44
in response to signals from the difference decoder 254 and the
function decoder 213 ~9 ~escribed iatcr.
The circuitry in Fig. 12 also includes clock logic
256. This logic receives a clocking signals on the lines 30 and
produces the necessary timing pulses in synchronis,n with the
clocking signals on the SBI 14.
When data is transmitted onto the SBI 14, a parity
generator 257 responds to the information in the data~ ID, TAG
and other fieids to produce the appropriate parity signals.
In addition, the memory controller contains circuitry
foc controlling memory cycles during which data is transmitted
into oc retrieved from a memory array 21A. This circuitcy is
shown in Fig. 13 and includes an address register 260 that
- receives the address for the location in an array that is
derived from the address information in comlnand-address signals
from the lines 40. These signals ace directed through an address
muLtiplexer 261 to the memory array, to the read-only me,nocy
248, or to the configuration cegisters. The other input to the
address multiplexer 261 includes address signals from memory
timing and refresh logic 262 that maintains the data in a
volatile memory in a valid state. Refreshing of such memories is
well known in the art.
Cycle decode and control logic 264 in Fig. 12 receives
- .
~ 83-204
Pg. 45
information from the command file and generates control signals
that are utilized in the circuitry shown in Fig. 13.
Still ceferring to Fig. 13, a I/O data multiplexer 265
selects data from one of the configuration registers 247, 266
and 267 or the read-onLy memory 248 for transferring the data
; onto the FILE bus if the incoming address identifies one of
those specific registers. Data receive latches 268 receive a
longword of data from the FILE bus and store it temporacily
until it is ready to be transferred over the DATA bus into the
memory 21A. This data is also loaded into latches 269 and 270
which serve as inputs into an error checking circuit 271 that is
not desccibed in any further detail.
A read data tag generator 272 encodes the tag field in
accocdance with any etrocs that may exist or not and enecgizes a
~ 15 tag transmitter 273 when the data is transmitted onto the SBI
; 14.
During opecation of the data processing system, the
clock logic 30 monitors the timing signals on the SBI 14. At saI
time ~3, all information on the SBI 14 is transferred into
appcopciate latches of all receiving nexuses. Initially, all
signals on the SBI 14 are tested for parity. If a pacity error
is detected, various flags ace set and cleared and a parity
fault is indicated. If write data is being received, it is
.,A,. , ' ,. ' , I ' . ' ' . .; ' , , . ~ ~ . ., , . ; ~ " '
5~7
placed in the command file along with an indicator that will
abort the write cycle and the write counter 252 is advanced. If
command-address information is received, it is placed in the
command file 212, but the write counter 252 is not advanced.
Assume that command-address information is received
without error, the tag decode circuit 210 decodes the function
~; signals. If the address signals specify a location in a memory
array, the address is transferred into the command file 212.
The memory array can be accessed by any of the valid functions;
if an invalid function is detected, the CNF signals will be set
to an error state.
The foregoing description is limited to a specific
embodiment of this invention. It will be apparent, however,
that this invention can be practiced in data processing systems
having diverse basic construction or in systems that use
different internal circuitry than is described in this
specification with the attainment of some or all of the
foregoing objects and advantages of this invention. Therefore,
, it is the object of the appended claims to cover all such
variations and modifications as come within the true spirit and
scope of this invention.
.''~ , .
- 46 -
