Note : Les descriptions sont présentées dans la langue officielle dans laquelle elles ont été soumises.
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This invention relates to a digital bus system which is
particularly suited for the transmission of pulse code modulated speech
and control data between a common multiplex and control circuit on one
hand, and a multiplicity of individual line interface circuits on the other.
Background of the Invention
In telecommunication switching systems utilizing digital
transmission, it is common practice to multiplex a plurality of PCM
encoded analog speech signals onto a common data transmission path.
The PCM encoded signals are coupled through the digital switching
system where they are distributed in accordance with address control
information. Due to the high reliability requirements of such systems,
it is also common practice to duplicate all major networks of the system
or to provide sufficient capacity that should one section fail another
can take over with the only penalty being some loss of access to the
system during busy periods.
In the past, time division multiplexed PCM (pulse-code-
modulation) data has been distributed from the switching system to
a plurality of line circuits over a common bus system utilizing address
control to access each line circuit during its assigned time slot.
A major weakness of such a system is that should the input to one of
the line circuits develop a short circuit, the whole bus including the
balance of the line circuits connected to it, is rendered unserviceable
even though redundant components feeding the bus system have been provided.
Statement of the Invention
This disadvantage of the prior systems has been overcome
in the present invention by providing a bus system in which a separate `
single data line is established between each line circuit and a pair
of multiplexers, either one of which may alternately access each of
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the data lines. The multiplexers in turn are alternately actuated by a
single gate so that only failure of this gate in a particular mode would
inhibit both multiplexers. All communications between the multiplexers and
the line circuits are carried over these single data lines so that should
one fail only the associated line circuit will be rendered unserviceable.
In addition, a single clock signal is distributed on a common bus to all line
circuits with sufficient isolation that failure of a line circuit will not
affect the clock signal coupled to the balance of the circuits. No other
synchronization or timing leads are used.
Thus, in accordance with the present invention there is
provided a digital communication bus system comprising first and second
multiplexers. Each of the multiplexers includes means for decoding consecutive
time division multiplexed addresses received over an address bus and for
receiving and transmitting time-division multiplexed data over respective
receive and transmit signal data paths in corresponding iterated time slots
of each frame. The system also includes a plurality of line circuits, each
of which couples the information from at least one individual telephone line
to a single bidirectional data line that is connected in common to both
multiplexers. Each of the multiplexers includes means responsive to each
decoded address for steering data received over the receive data path to
the associated line circuit over its single bidirectional data line; and
for steering data received from the associated line circuit over its single
data line to the transmit data path in the two time slots succeeding its
address. In addition, this system includes means responsive to a control
signal for actuating one or the other of the first or second
multiplexers.
With such a system, the single data line would sequentially
carry all control, PCM, supervision and status information data in both
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directions, between the multiplexer and the line circuit. The system
utilizes a minimum number of leads coupled between each line circuit and the
multiplexers which helps to avoid manufacturing problems should a large
number of line circuits be mounted in a small space. The system also
provides complete redundancy of other components for reliability. With
this system, failure of one line circuit will not affect operation of the
bus to the other line circuits.
Brief Description of the Drawings
An example embodiment of the invention will now be
described with reference to the accompanying drawings in which:
Figure 1 is a block schematic diagram of the overall bus
system for a line module using duplicated controllers with a number
of line-group networks;
Figure 2 illustrates in greater detail one of the line-group
networks of Figure 1 showing the interconnection of multiple line circuits
with two multiplexers; and
Figure 3 illustrates various timing signals used in the
network of Figure 2.
Description of the Preferred Embodiment
Many of the elements illustrated in the drawings are duplicates
of each other. In general, only one such element will be illustrated in
detail while all the others will be shown in block form. Where a plurality of
elements are used, each will be given a base reference character followed by a
-number. A common practice of assigning zero to the initial unit of each
series will be followed. Thus, whére 40 units are utilized, they will be
identified as -0 through -39.
Referring to Figure 1, the system comprises a group of
40 line-group networks LG-0 through LG-39 each of which includes a pair
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of multiplexers M-0 and M-l and a plurality of 32 line circuits L-0
through L-31. The multiplexers M-0 and M-l in turn are connected to the
respective line-module controllers LMC-0 and LMC-l through common
buses B-0 and B-l and 40 individual group select leads GS-0 and GS-39.
The duplicated line module controllers LMC-0 and LMC-l are connected to
a central switching network (not shown) through four duplicated input
ports P0-0 through P3-1, and P4-0 through P7-1 respectively, via dual
multiple data links MDL. Each input port P0-0 through P7-1 has a capacity
of 30 input channels in 32 time slots allowing two time slots for supervision
and control. Under normal operation, each controller functions as the
primary controller for one-half the line-group networks and hence accesses
one-half the 1280 (32x40) line circuits. Normally therefore, 640 line
circuits have access to 120 (4x30) channels in the switching network
through each controller. However, should one primary controller LMC-0
or LMC-l or any one of its associated operating multiplexers M-0 or M-l
be rendered unserviceable, the other controller functioning as a secondary
to it, will take over control of all 1280 line circuits. Since all
1280 line circuits must now share the 120 rather than 240 available
channels, access to the switching system may be affected during peak
traffic periods.
The function of each of the controllers LMC-0 and LMC-l
includes scanning for originating calls, collecting digits, assigning
channels to lines, controlling application of ringing signals or tones
to the lines, and communicating with the central control computer in
the switching network via at least some of the message channels in the
two time slots allotted for supervision and control.
Referring to both Figures 1 and 2, each of the
40 line-group networks comprises the pair of multiplexers M-0 and M-l
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which are coupled to their respective controllers through buses B-0 and B-l,
except for the activity control signal ACTY which is coupled to only the
primary controller LMC-0 over bus B-0 (in this embodiment). Each of the
line circuits L-0 through L-31 couples the subscriber loops 24 to the
32 separate bidirectional data lines DL-0 to DL-31 which in turn are
connected in common to both multiplexers M-0 and M-l.
The detailed structure of the line-group network in Figure 2
will be readily apparent from the following detailed description of its
function and operation taken in conjunction with the timing waveforms
illustrated in Figure 3, the location of which in each bus is identified
by corresponding reference characters.
In Figure 3, boxed waveforms each represent 10 bits of binary
information. As mentioned above, two channel time slots 0 and 16 are
utilized for supervision and control. During these periods the line
circuits L-0 through L-32 are selectively scanned by controllers LMC-0 or
LMC-l. The remaining channel slots 1-15 and 17-31 are available for PCM
data. In this example embodiment, it is assumed that line circuits
4, 8, 17 and 23 (assigned channel time slots 5, 13, l and 12 by the
controller) are carrying traffic in one line-group network while line
circuits 6, 14, 17 and 29 (assigned time slots 8, 26, 20 and 27 by the
controller) are carrying traffic in one or more of the other line-group
networks, for the duration of the respective telephone calls. In addition,
line circuits 8 and 9 of the said one line-group network are scanned during
time slots 0 and 16 respectively of one frame, while channel 10 of
another line-group network is scanned during time slot 0 of the following
frame. The balance of the channels for this port are idle at this time.
The 10-bit addresses ADDR for the networks normally from
their primary controller, are transmitted over buses B-0 and B-l to
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serial/parallel converters 10. After a complete address is received,
the parallel output of converter 10 is loaded into a receive address
register 11 under control of a group select signal G-S and a channel
pulse C-P (which indicates the beginning of each 10-bit channel period) during
the succeeding time slot. The output of the register 11 then enables a
demultiplexer 12 which then accepts the received serial data RDAT which is
coupled through an AND gate 13, under control of a delayed group select
signal G-S, to the signal input of the demultiplexer 12. The serial data RDAT
is steered through the demultiplexer 12 to the selected data line where it is
coupled to the input of the selected line circuit L-0 through L-32. In the
present example, the address ADDR for channel 8 in time slot 0 in conjunction
with the presence of the group select signal G-S, causes the received control
data RCTL on the receive data path RDAT to be directed to the line circuit L-8
during time slot 1. Similarly, the address ADDR during time slot 1 together
with G-S causes the received PCM data RPCM on the receive data path RDAT to be
directed to the line circuit L-17 during time slot 2, and so on. However, the
address for channel 6 which occurs during time slot 8 will not enable the
demultiplexer 12 in the one group select network due to the absence of the
delayed group select signal G-S at the input to the AND gate 13 (N.B.-RDATA in
Figure 3). It will however enable an alternate group-select network if the
signal G-S is applied to it over another group select lead G-S as shown in
Figure 1.
At the end of time slot 1, the address in register 11 is
shifted to transmit address register 14 which enables the multiplexer 15
so as to steer incoming information TDATA from the selected line circuit
to the transmit data path TDAT through an AND gate 16 which is opened
by the group-select signal G-S that has now been delayed two time slots.
This is illustrated in Figure 3 where the scan information XSCN from line
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circuit 8 is transmitted during time slot 2 over data line DL-8 and the
XPCM information from line circuit 17 is transmitted over the data line
DL-17 and the transmit data path TDAT during time slot 3.
The activity signal ACTV from the prima;ry controller LMC-0
enables both the CLK and demultiplexer 12. During normal operation,
different channel information is transmitted to each of the multiplexers
M-0 and M-l since they are driven by controllers LMC-0 and LMC-l respectively,
each of which acts as the primary controller for a different half of the
1280 line circuits. However, since each ACTV signal actuates only one of
the multiplexers M-0 or M-l at a time, the channel data going to the
non-operating multiplexer is not transmitted through to its associated
line circuits. Failure of either of the controllers LMC-0 or LMC-l or any
one of the operating multiplexers M-0 or M-l is sensed by the other
controller as well as the switching network. This causes the ACTV signal
to be removed from the affected multiplexer in each of the line-group
networks LG-0 through LG-39, thereby resulting in the other multiplexer
of that network taking over. Concurrently the channel information for -
that line-group network is routed from the switching network through the
secondary controller to its associated multiplexer. Hence, the line
circuits L-0 through L-31 continue to function over the common data
lines DL. The non-operating multiplexer is monitored continuously by its
associated controller through test codes sent via RDAT, TDAT, using special
address codes. Detection of a failure causes an alarm for repair but no
switch-over of the system.
Referring again to Figure 3, the group-select signal G-S
together with the serial address signal ADDR determines during each channel
period the line to be accessed from the controller during the succeeding
two time slots. Actual data (PCM or control/scan) is transmitted serially
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over the receive data RDAT bus to the line group and over the transmit
data TDAT bus to the controller. Each data exchange extends over periods
of three channel time slots. In the first period, the line address is
transmitted; in the second period, data is received from the controller
by the line circuit; in the third period, data is transmitted from the
line circuit back to the controller. Thus, during the second and third
periods, the operating multiplexer M-O or M-l is transparent to data
being transmitted or received from the selected line circuits. The
access to different line circuits in successive transaction periods
overlaps in time to allow effective use of all 32 channel time slots.
The only restriction is that the same line not be accessed in successive
channel time slots. Thus, in the example embodiment, PCM data information
for channel 8 cannot be received or transmitted during time slots 1 and 2
since the control and scan information for that channel occupies these
periods. To avoid overlap, even scanning/control addresses are transmitted
during time slot O while those for PCM data for the even address lines are
never transmitted during time slots 31 or 1. Odd scanning/control addresses
are transmitted during time slot 16 while those for PCM data for the odd
address lines are never transmitted during time slots 15 or 17. Various
other arrangements are also possible.
Referring again to Figure 2 and the expanded portions of
Figure 3, data on the data line DL-8 (not specifically shown in Figure 2 -
refer to typical data line DL-l and line circuit L-l) is received by the
line control circuit 21 in the line circuit L-l under control of the
clock CLK. Each 20 bit exchange between the line circuit and the controller
is initiated by a start bit S = 1 (note the expanded portions of Figure 3).
This is followed by a mode bit M = 1 which indicates that control/scan
information will follow or M = O which indicates that PCM information
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will follow. After reception of the bit M = 1, 8 bits of control data
RCTL are transmitted from the controller to the line control circuit 21.
This information which provides control for ringing, or operation of
numerous test functions, is steered to the scan and control registers 22
where it is utilized to actuate a line interface circuit 23 which is -
connected to the subscriber loop 24. This is followed by 8 bits of
scanning information XSCN, which transmits status and dialling information
from the line circuit back to the controller. Finally, line status LS
and on/hook supervision SV bits are transmitted again from the line circuit
10 during the last two bits of the exchange.
Every line, whether it is carrying traffic or not, is
accessed for scanning and control once every n x 5msec, 5msec being
the basic cycle time of the controllers. The value of n depends upon
the number of lines being scanned and the status of the line (supervision
or dialling).
During an exchange of PCM information, the start bit S = 1
and mode M = 0 are followed by 8 bits of RPCM transmitted from the
switching network, through the controller to the line circuit. These 8 bits
are steered through the line control circuit 21 to a codec 25. The codec 25
20 converts the RPCM signal to analog form for transmission through the line
interface circuit 23 to the subscriber loop 24. Conversely, a coded analog
sample SPCM is transmitted from the codec 25 through the line circuit 21
back through the controller to the switching network. Again, line status LS
and supervision SV are transmitted at the end of this data exchange to the
controller. The S and T leads between the circuits 21, 22 and 25 provide
start and timing information in a well known manner.
In an alternate embodiment, the channel information fed to
the input ports P0-0 through P3-1 may be a duplicate of that to ports
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P4-0 through P7-1 respectively. With this arrangement both multiplexers
M-O and M-l transmit and receive the same information although at any
point in time only one of any pair is activated by the ACTV signal.
In yet another embodiment, several telephone line circuits
(e.g. 4) may be served by a single bidirectional data line with all lines
in a line-group network (e.g. 32) being accessed in a fixed sequence,
from the multiplexer. All line circuits on the single data line are
accessed in sequence so that only a single synchronizing pulse (one per
frame) is required in addition to a clock signal, to identify the start
of the sequence.
With this arrangement failure of one line circuit could
render unserviceable the balance of the line circuits (e.g. the other 3)
coupled to its associated bidirectional data line. However, the balance
of the lines in the line-group network would be unaffected.
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