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Sommaire du brevet 1121517 

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Disponibilité de l'Abrégé et des Revendications

L'apparition de différences dans le texte et l'image des Revendications et de l'Abrégé dépend du moment auquel le document est publié. Les textes des Revendications et de l'Abrégé sont affichés :

  • lorsque la demande peut être examinée par le public;
  • lorsque le brevet est émis (délivrance).
(12) Brevet: (11) CA 1121517
(21) Numéro de la demande: 1121517
(54) Titre français: COMMUTATEUR DE HAUTES TENSIONS ISOLE PAR DIELECTRIQUE A SEMICONDUCTEUR A PORTE ELOIGNEE
(54) Titre anglais: HIGH VOLTAGE DIELECTRICALLY ISOLATED REMOTE GATE SOLID-STATE SWITCH
Statut: Durée expirée - après l'octroi
Données bibliographiques
(51) Classification internationale des brevets (CIB):
  • H01L 29/38 (2006.01)
(72) Inventeurs :
  • BERTHOLD, JOSEPH E. (Etats-Unis d'Amérique)
  • HARTMAN, ADRIAN R. (Etats-Unis d'Amérique)
  • RILEY, TERENCE J. (Etats-Unis d'Amérique)
  • SHACKLE, PETER W. (Etats-Unis d'Amérique)
(73) Titulaires :
(71) Demandeurs :
(74) Agent: KIRBY EADES GALE BAKER
(74) Co-agent:
(45) Délivré: 1982-04-06
(22) Date de dépôt: 1979-11-29
Licence disponible: S.O.
Cédé au domaine public: S.O.
(25) Langue des documents déposés: Anglais

Traité de coopération en matière de brevets (PCT): Non

(30) Données de priorité de la demande:
Numéro de la demande Pays / territoire Date
972,022 (Etats-Unis d'Amérique) 1978-12-20

Abrégés

Abrégé anglais


Abstract of the Disclosure
A high voltage solid-state switch, which allows
alternating or direct current operation and provides
bilateral blocking, consists of a first p- type silicon
body dielectrically isolated from a semiconductor
substrate with a p+ type anode region an n+ type cathode
region and an n+ type gate region located within the
body. A second p- type region of higher impurity
concentration than the body encircles the cathode region.
The anode region, gate region, and cathode region are all
separated by the body. The anode region and the cathode
region are adjacent one another. Separate electrodes are
coupled to the anode region, gate region, cathode region
and substrate, respectively.

Revendications

Note : Les revendications sont présentées dans la langue officielle dans laquelle elles ont été soumises.


Claims:
1. A structure comprising a semiconductor body whose
bulk is of one conductivity type and which has a major
surface, a localized first region which is of the one
conductivity type, and a localized second region and a
localized third region, which are both of the opposite
conductivity type, each of the localized first second and
third regions being of relatively low resistivity as
compared to the bulk of semiconductor body and being spaced
apart from the others, and separate electrodes being
connected to each of the first, second and third regions,
the localized first, second and third regions each having a
portion thereof which forms a part of major surface and
being characterized in that:
the semiconductor body is separated from a
semiconductor wafer (substrate) by a dielectric layer, the
semiconductor wafer (substrate) being adapted to facilitate
electrical contact thereto; and
the first and third regions being separated by a
portion of the body with the second region being located in
a portion of the body other than that portion which
separates the first and third regions.
2. The structure of claim 1 further characterized in
that
the semiconductor body includes a localized fourth
region of the one conductivity type and of resistivity
intermediate between that of the bulk of the semiconductor
body and the first region, the fourth region encircles the
third region.
3. A structure of claim 1 further characterized by a
plurality of semiconductor bodies included within the
semiconductor wafer (substrate) and being separated
therefrom by dielectric layers.
4. The structure of claim 3 characterized in that the
conductivities of the semiconductor body, the first region,
second region, the third region, and the semiconductor
wafer (substrate) are p-, p+, n+, n+, and n-type,
respectively.
13

5. The structure of claim 3 further characterized by a
conductor region, being spaced between and separated from
the electrodes connected to the first and third regions,
and being electrically coupled to the second region.
6. A switching element comprising a semiconductor body
whose bulk is of one conductivity type and relatively high
resistivity and which includes anode, gate, and cathode
regions spaced apart and localized along a common planar
surface of the body, each being of relatively low
resistivity, the cathode and gate regions being of the
opposite conductivity type as the bulk and the anode region
being of the
14

Berthold-1
15.
same conductivity type as the bulk, the semiconductor
body being separated from a semiconductor wafer by a
dielectric layer, separate electrodes to the cathode,
anode, and gate regions, the semiconductor wafer having
a separate electrode coupled thereto which is adapted
to be held at the most positive potential used with
the structure, the anode region and the cathode region
being separated by a portion of the body with the gate
region being located in a portion of the body other
than that portion which separates the anode and cathode
regions, the parameters of the various portions of
the body being such that with the potential of the anode
region being greater than that of the cathode region
and the potential of the gate region being insufficient
to deplete the portion of the bulk of the semi-
conductor body between the anode and cathode regions
there is facilitated a substantial current flow
between the anode and cathode regions via the bulk,
and with the potential of the gate region being
sufficiently more positive than that of the anode
region to deplete the portion of the bulk of the
semiconductor body between the anode and cathode
regions there is facilitated an interrupting or
inhibiting of current flow between the anode and
cathode regions.
7. A switching element in accordance with
claim 6 in which the cathode region is surrounded
by a region of the same conductivity type as the bulk
but of lower resistivity.
8. A plurality of switching elements in
accordance with claim 6 each included in the semi-
conductor wafer and dielectrically isolated from one
another.
9. A pair of switching elements each in
accordance with claim 6 with the gate electrodes of
the pair connected to one another and the anode
electrode of each connected to the cathode electrode
of the other to provide a bilateral switch.

Description

Note : Les descriptions sont présentées dans la langue officielle dans laquelle elles ont été soumises.


Bertllold- 1
J 1.
HIGH VOLTAGE DIELECTRICALLY
ISOLATED REMOTE GATE SOLID-STATE SWITCH
Technical Field
This invention relates to solid-state structures
and, in particular, to high voltage solid-state structures
useful in telephone switching systems and many other
5 applications.
Background of the Invention
In an article entitled "A Field Terminated Diode"
by ~ouglas E. Houston et al, published in IEEE
Transactions on Electron Devices, Vol. ~D-23, No. 8,
10 August 1976, there is described a discrete solid-state
high voltage switch that has a vertical geometry and
which includes a region which can be pinched off to
provide an "OFF" state or which can be made highly
conductive with dual carrier injection to provide an
15 "ON" state. One problem with this switch is that it
is not easily manufacturable with the other like
switching devices on a common substrate. Another problem
is that the spacing between the grids and the cathode
should be small to limit the magnitude of the control
20 grid voltage; however, this limits the useful voltage
range because it decreases grid-to-cathode breakdown
voltage. This limitation effectively limits t~ use
of two of the devices with the cathode of each coupled
to the anode of the other to relatively low voltages.
25 Such a dual device structure would be useful as a high
voltage bidirectional solid-state switch. An additional
problem is that the base region should ideally be
highly doped to avoid punch-through from the anode to
the grid; however, this leads to a low voltage breakdown
30 between anode and cathode. Widening of the base region
limits the punch-through effect; however, it also
increases the resistance of the device in the ON state.
lt is desirable to have a solid-state switch
which is easily integratable such that two or more
switches can be simultaneously fabricated on a common
substrate and wherein each switch is capable of bilateral

blocking of relatively high voltages. One such structure
is described in Canadian application Serial No. 342,165
filed in the names of A.R. Hartman, T.J. Riley and P. W.
Shackle on December 18, 1979. This present application
relates to a subsequent improvement over such a structure.
Summary of the Invention
In accordance with an aspect of the invention there ix
provided a structure comprising a semiconductor body whose
bulk is of one conductivity type and which has a major
surface, a localized first region, which is of the one
conductivity type, and a localized second region and a
localized third region, which are both of the opposite
conductivity type, each of the localized first, second and
third regions being of relatively low resistivity as
compared to the bulk of semiconductor body and being
spaced apart from the others, and separate electrodes
being connected to each of the first, second and third
regions, the localized first, second and third regions
each having a portion thereof which forms a part of major
surface and being characterized in that: the semiconductor
body is separated from a semiconductor wafer (substrate)
by a dielectric layer, the semiconductor wafer (substrate)
being adapted to facilitate electrical contact thereto;
and the first and third regions being separated by a
portion of the body with the second region being located
in a portion of the body other than that portion which
separates the first and third regions.
In a preferred embodiment the first, second and third
regions serve as anode, gate and cathode, respectively, of
the structure.
The structure of the present invention, when suitably
; designed, can be operated as a switch which is

Berthold-l
3.
characterized by a low impedance path between anode and
cathode when in the ON ~conducting) state and a high
impedance path between anode and cathode when in the
OFF ~blocking) staee. The semiconductor wafer
5 (substrate) is typically held in potential at the highest
available potential. The potential applied to the
gate region determines the state of the switch.
During the ON ~conducting) state there is dual
carrier injection that results in the resistance
10 between anode and cathode being relatively low.
This structure, which is to be denoted as a
ga~ed diode switch ~GDS), when suitably designed, is
capable of blocking relatively large potential differences
between anode and cathode in the OFF ~blocking) state,
15 independent of polarity, and is capable of conducting
relatively large amounts of current with a relatively
low voltage drop between anode and cathode in the ON
(conducting) state. The relatively close spacing of
anode and cathode~ with the gate being located other
20 than between anode and cathode, results in relatively
low resistance between anode and cathode when the GDS
is operating in the ON state.
Arrays of these GDSs can be fabricated on a
single integrated circuit chip. The bilateral blocking
25 characteristic of the present GDS structure allows two
of such devices to be used with the gates common and
the cathode of each coupled to the anode of the other
to form a bidirectional switch.
These and other novel features and advantages of
30 the present invention are better understood from
consideration of the following detailed description
taken in conjunction with the accompanying drawing.
Brief Description of the Drawing
FIGS. 1 and 2 illustrate a cross-sectional and
35 a top view, respectively, of a structure in accordance
with an embodiment of the invention;

Berthold-l
4.
FIG. 3 illustrates a proposed electrical symbol
for the structure of FIGS. 1 and 2;
FIG. 4 illus~rates a structure in accordance
with another embodiment of the invention;
FIG. 5 illustrates a structure in accordance
with still another embodiment of the invention; and
FIG. 6 illustrates a structure in accordance
with still another embodiment of the invention.
Detailed Description
Referring now to FIGS. 1 and 2, there is illustrated
a cross-sectional and a top view, respectively, of a
structure 10 having a major surface 11 and comprising
a semiconductor wafer (substrate) 12 and a mono-
crystalline semiconductor body 16 of one conductivity
15 type. The monocrystalline semiconductor body has
a portion that is common with surface 11. Body 16
is separated from substrate 12 by a dielectric
layer 14.
A semiconductor gate region 20, which is of the
20 opposite conductivity type, is included in body 16
at one end thereof and has a portion thereof that
extends to surface 11. Gate region 20 can exis~ on
the letside of body 16, on the right side ~as is
illustrated by the dashed lines of FIG. 1), or on the
25 front or rear of body 16 ~as illustrated by the dashed
lines of FIG. 2). Region 20 can be separated from
dielectric layer 14 by a portion of body 16 or can,
as is illus~rated by the dashed lines of FIG. 1, extend
so as to come in contact with a portion of region 14.
A semiconductor anode region 18, which is of the
one conductivity type, is included in body 16 and is
separated from region 20 by portions of body 16. A
semiconductor cathode region 24 of the opposite
conductivity type is included in body 16 and is
35 encircled by a semiconductor region 22. Region 22,
which is of the one conductivity type and of
resistivity intermediate between that of body 16 and

Berthold- 1
~112~ 5~
5.
anode region 18~ acts to prevent voltage punch-through
and to inhibit an inversion layer being formed in
body 16. In a portion of substrate 12 ou~side of
dielectric layer 14 and body 16 there exists a
5 semiconductor region 34 which is of the same conductivity
type as substrate 12 but is of lower resistivity.
Portions of regions 18, 20, 24 and 34 extend to
surface 11 and allow low resistance contact to be made
to these regions. Region 22 also has a portion which
lO extends to surface 11. Regions 28, 30, 32 and 36 are
electrodes which make low resistance contact to regions
18, 20, 24 and 34, respectively. A dielectric layer
26 covers major surface 11 so as to isolate electrodes
28, 30, 32 and 36 from all regions other than those
15 intended to be electrically contacted.
A conduc~or region 38, which is optional, exists
on top of layer 26 and is located in between electrodes
28 and 32. Region 38 is electrically coupled to
electrode 30. Region 38 helps reduce the magnitude of
20 the gate voltage necessary in the operation of structure
10 .
In one illustrative embodiment, substrate 12,
body 16 and regions 18, 20, 22, 24 and 34 are of n-,
p-, p+, n~, ~, n+, and n+ type conductivity,
25 respectively. Dielectric layer 14 is silicon dioxide
and electrodes 28, 30, 32 and 36, and conductor region
38 are all aluminum. Substrate 12 and region 34
could also be of p- and p+ type conductivity, respectively.
A plurality of separate bodies 16 can be formed
30 in a common support to provide a plurality of switches.
Structure 10 is typically operated as a solid-
state switch which is characterized by a relatively
low impedance path between anode region 18 and cathode
region 24 when in the ON (conducting) state and a
35 relatively high impedance between said two regions when
in the OFF (blocking) state. This type of structure is
hereinafter denoted as a gated diode switch (GDS).

Berthold-l
6.
Substrate 12 is held at all times at the most positive
available potential by applying said potential to
electrode 36. The potential applied to region 20
through electrode 30 determines the state of the switch.
If the potential of gate region 20 is greater
than that of anode region 18 and cathode region 24 the
structure is in the OFF ~blocking) state. The effect
of the substrate 12 potential is to cut off or inhibit
conduction between anode region 18 and cathode region
10 24 because it tends to cause the portion of body 16
between anode region 18 and cathode region 24 to be
more positive in potential than either anode region 18
or cathode region 24~ This serves to inhibit the
injection of holes into that portion of body 16. In
15 addition, electrons in body 16 are collected at
region 20 and therefore do not reach anode region 18.
With the potential of gate region 20 at a more positive
level than anode region 18, conduction between anode
region 18 and cathode region 24 is thus inhibited.
20 It essentially pinches off body 16 against dielectric
layer 14 in the bulk portion thereof below gate region
20 and extending down to dielectric layer 14. The
amount of excess positive potential needed to inhibit
or cut off conduction is a function of the geometry
25 and impurity concentration (doping) levels of structure
10 .
The use of conductor region 38 has been shown to
reduce the magnitude of the potential needed to inhibit
or cut off conduction. In the OFF state structure 10
30 is capable of bilateral blocking of relatively large
potentials between anode and cathode regions, independent
of which region is at the more positive potential.
This bilateral blocking feature allows a bidirectional
switch combination of two structure lOs (or of two
35 bodies 16 separated by a dielectric layer such as 14
with both being formed in the same semiconductor substrate),

5~7
7.
with the anode of each body 16 coupled to the cathode of
the other body 16 and the gates being common. Such a type
of bidirectional switch is described in Canadian application
Serial No. 340,799 filed in the names of A.R. Hartman, B.T.
Murphy, R. J. Riley and P. W. Shackle on November 28, 1979.
In the ON state the potential of gate region 20 is
typically below that of the potential of anode region 18.
Holes are injected into region 16 from anode region 18 and
electrons are injected into region 16 from cathode 24.
~ome of the electrons emitted from cathode region 24, or
some which may be emitted from gate region 20, collect on
the surface of region 14 and act to effectively shield the
effect of the positive potential of substrate 12. This
allows for conduction between anode region 18 and cathode
region 24. These holes and electrons can be in sufficient
numbers to form a plasma which conductivity modulates body
16. This effectively lowers the resistar.ce of body 16 such
that the resistance between anode region 18 and cathode
region 24 is relatively low. This type of operation is
denoted as dual carrier injection.
Region 22 helps limit the punch-through of a depletion
layer formed during operation between region 20 and
substrate 12 and cathode region 24. Region 22 also helps
inhibit formation of a surface inversion layer between
cathode region 24 and gate region 20. In addition, region
22 allows cathode region 24 and region 20 to be relatively
closely spaced. This results in a relatively-compact
structure.
~ The p-n junction diode comprising body 16 and gate
region 20 becomes forward-biased during the ON state of
structure 10. Current limiting means (not illustrated) is
used to limit the conduction through the forward biased
diode. One example of such current limiting means is
illustrated and described in copending patent application
Serial No. 342,0~3 which was filed in the names of A. R.
Hartman, T. J. Riley and P. W. Shackle on December 17, 1979.

8.
Structure 10 is designated such that anode region 18
and cathode region 24 can be spaced relatively closely to
each other in order to provide relatively low resistance
between the two during the ON (conducting) state. Structure
10 is similar to a structure described in the above
identified Canadian patent application 342,165, except that
the gate region is located in a portion of body 16 other
than directly between the anode (18) and cathode (24)
regions. The improvement of the present structure over the
structure of the above described copending application is
that the anode and cathode regions can be more closely
spaced and the resulting resistance during the ON
(conducting) state is lowered.
A proposed electrical symbol for this type of switch is
illustrated in FIG. 3. The anode, gate, and cathode
electrodes of the GDS are denoted as 28, 30 and 32,
respectively.
One embodiment of structure 10 has been fabricated with
the following design. Semiconductor wafer (substrate) 12
is an n-type silicon substrate, 18 to 22 mils thick, with
an impurity concentration of approximately 5 x 1013
impurities/cm3, and is 100 ohm-centimeter type material.
Dielectric layer 14 is silicon dioxide that is typically 2
to 4 microns thick. Body 16 is typically 30 to 40 microns
thick, approximately 430 microns long, 170 microns wide,
and is of p- type conductivity with an impurity concent-
ration of approximately 5- 9 x 1013 impurities/cm3.
Anode region 18 is of p~ type conducti~ity, is typically 2
to 4
!

Berthold-l
9.
microns thick, 28 microns wide, 55 microns long, and
has an impurity concentration of approximately 1019
impurities/cm3. Electrode 28 is aluminum, with a
thickness of 1 l/2 microns, a width of 55 microns,
5 and a length of 95 microns. Gate 20 is of n+ type
conductivity, is typically 2 to 4 microns th ck,
38 microns wide, 55 microns long, and has an impurity
concentration of approximately 1019 impurities/cm3.
Electrode 30 is aluminum with a thickness of 1 1/2
10 microns, a width of 76 microns, and a length of 95
microns. The spacing between adjacent edges of
electrodes 28 and 32 is ~ypically 40 microns ~with
no region 38) and the spacing between adjacent edges
of electrodes 28 and 30 is typically 40 microns.
15 Region 22 is of ~ type conductivity and is typically
3.5 microns thick, 44 microns wide, 44 microns long,
and has a surface impurity concentration of approximately
1018 impurities/cm3. Cathode region 24 is of n+
type conductivity and is typically 2 microns thick,
20 30 microns wide, 30 microns long, and has an impurity
concentration of approximately 1019 impurities/cm3.
Electrode 32 is aluminum, 1 1/2 microns thick, 82
microns wide~ and 82 microns long. The spacing between
the ends of electrodes 28 and 32 and the respective
25 ends of p- type body 16 is 50 microns. Conductor
region 38, which is aluminum,is spaced 30 microns apart
from electrodes 28 and 32 and is 10 microns wide,
l 1/2 microns thick, and 75 microns long. Conductor
region 38 makes electrical contact to electrode 30 in
30 the front or rear of region 16.
Structure 10, using the parameters denoted above,
has been operated as a gated diode switch with 400
volts between anode and cathode. The anode had ~200
volts applied thereto and the cathode had -200 volts
35 applied thereto. The -200 volts can also be applied
to the anode and the ~200 volts can be applied to the
cathode. Thus, structure 10 bilaterally blocks voltage

Berthold-l
10 .
between anode and cathode. With conductor region 38
being present, a potential of ~210 volts was found
sufficient to break 1 mA of current flow between anode
and cathode. It is estimated that this voltage need
5 be 20 volts higher if conductor region 38 is eliminated.
The ON resistance of t~e gated diode switch with 100 mA
flowing between anode and cathode was approximately
10-12 ohms and the voltage drop between anode and
cathode is typically 2.2 volts. A layer of silicon
10 nitride (not illustrated~ was deposited by chemical
vapor deposition on top of silicon dioxide layer 26
to act as a sodium barrier. Electrodes 28, 30, 32, and
36 were then formed and a coating of radio frequency
plasma deposited silicon nitride ~not illustrated) was
15 applied to the entire surface of structure 10. The
layers of silicon nitride serve to help prevent high
voltage breakdown in the air between adjacent electrodes.
Referring now to FIG. 4, there is illustrated a
structure 100. Structure 100 is very similar to
20 structure 10 and all components thereof which are
essentially identical or similar to the corresponding
components of structure 10 are denoted by the same
reference number with the addition of a 'lO-' at the end.
The basic difference between structures 10 and 100 is
25 the elimination in structure 100 of a corresponding
region to that of region 22 of structure 10.
Appropriate spacing of anode region 180 from cathode
region 240 provides sufficient protection against depletion
layer punch-through to facilitate the use of structure
30 100 as a high voltage switch.
Referring now to FIG. 5, there is illustrated a
structure 1000. Structure 1000 is very similar to
structure 10 and all components thereof which are
essentially identical or similar to the corresponding
35 components of structure 10 are denoted by the same
reference number with the addition of two "0s" at the
end. The basic difference between structures 10 and 1000

Berthold-l
11 .
is the substitution of a semiconductor guard ring region
40 around cathode region 2400 instead of a region
like region 22 of structure 10 of FIG. 1. Guard rinu
40 can be separated from cathode region 2400 or, as is
5 illustrated by the dashed lines, it can be extended
so as to come into direct contact therewith. The
surface inversion protection provided by region 40
is believed adequate to allow high voltage operation.
Guard ring 40 is of the same conductivity type as body
10 1600 but of lower resistivity.
Referring now to FIG. 6, there is illustrated a
solid-state structure 10,000. Structure 10,00 is very
similar to structure 10 and all components which are
essentially identical or similar are denoted by the
same reference number with the addition of three "Os"
at the end. The main difference between structure
10,000 and structure 10 is the use of a semiconductor
guard ring region 400 around cathode 24,000. Guard
ring 400 is similar to guard ring 40 of structure 1000
20 of FIG. 5. The dashed line portion of guard ring 400
illustrates that it can be extended so as to contact
cathode 24,000. The combina*ion of region 22,000
and guard ring 400 provides protection against
inversion of body 16,000, particularly between gate
25 region 20~000 and cathode region 24,000, and provides
protection against depletion layer punch-through
to cathode region 2400. This type of dual protec~ion
around cathode region 24,000 is the preferred protection
structure. ~uard ring 400 is of the same conductivity
30 type as region 22,000 but is of lower resistivity.
The embodiments described herein are intended
to be illustrative of the general principles of the
present invention. Various modifications are
possible consistent with the spirit of the invention.
35 For example, semiconductor substrate region 12 can be
p- type conductivity silicon with region 34 being p~
type conductivity. Still further, a dielectric layer

Berthold- 1
12.
of silicon nitride or other dielectric materials can
be substituted for the silicon dioxide layer 14. Still
further, the electrodes can be doped polysilicon,
gold, titanium, or other types of conductors. Still
5 further, the impurity concentration levels, spacings
between different regions, and other dimensions of the
regions can be adjusted to allow significantly higher
operating voltages and currents than are described.
Still further~ the conductivity type of all regions
10 within the dielectric layer can be reversed provided
the voltage polarities are appropriately changed in
the manner well known in the art. A reversal of
conductivity types results in the anode and cathode
being reversed. It is to be appreciated that the
15 struc~ures of the present invention allow alternating
or direct current operation. A bilateral switch
comprising two of the disclosed structures with the
gates being common and the anode of each coupled to
the cathode of the other is easily formed.
,
.-

Dessin représentatif

Désolé, le dessin représentatif concernant le document de brevet no 1121517 est introuvable.

États administratifs

2024-08-01 : Dans le cadre de la transition vers les Brevets de nouvelle génération (BNG), la base de données sur les brevets canadiens (BDBC) contient désormais un Historique d'événement plus détaillé, qui reproduit le Journal des événements de notre nouvelle solution interne.

Veuillez noter que les événements débutant par « Inactive : » se réfèrent à des événements qui ne sont plus utilisés dans notre nouvelle solution interne.

Pour une meilleure compréhension de l'état de la demande ou brevet qui figure sur cette page, la rubrique Mise en garde , et les descriptions de Brevet , Historique d'événement , Taxes périodiques et Historique des paiements devraient être consultées.

Historique d'événement

Description Date
Inactive : Périmé (brevet sous l'ancienne loi) date de péremption possible la plus tardive 1999-04-06
Accordé par délivrance 1982-04-06

Historique d'abandonnement

Il n'y a pas d'historique d'abandonnement

Titulaires au dossier

Les titulaires actuels et antérieures au dossier sont affichés en ordre alphabétique.

Titulaires actuels au dossier
S.O.
Titulaires antérieures au dossier
ADRIAN R. HARTMAN
JOSEPH E. BERTHOLD
PETER W. SHACKLE
TERENCE J. RILEY
Les propriétaires antérieurs qui ne figurent pas dans la liste des « Propriétaires au dossier » apparaîtront dans d'autres documents au dossier.
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Nombre de pages   Taille de l'image (Ko) 
Revendications 1994-02-15 3 92
Dessins 1994-02-15 3 58
Abrégé 1994-02-15 1 17
Description 1994-02-15 12 439