Note : Les descriptions sont présentées dans la langue officielle dans laquelle elles ont été soumises.
112~3~2
Field of the Invention
. _ ....... .
The present invention relates to a communication
system, especially one designed for transmitting data over a
common bus between t~e c~mmcn control processor of a data
processing s~stem and a plurality of terminal devices which may
be remotely located with respect to the processor.
Back~round of the Invention
In present day data processing and transmission systems,
it is common practice to assign a common control processor the
task of processing data received from and to be transmitted to
a plurality of terminal equipment disposed at a plurality of
locations which may be remotely located with respect to the
processor. Such terminal equipment typically includes keyboard
devices, numeric displays, operator displays, printers, cash
drawers, etc., as common equipment at point of sales termlnals.
Transactions carried out by such terminal equipment require the
exchange of data between the remote equipment and the processor,
with real-time data handling.
In systems employing a common bus for transmission oi
serialized data, there has been a practical limit to the degree
of remoteness or physical separation of the terminal equipment
from the processor due to influences such as noise induced
signal degradation, lack of drive, etc. Furthermore, co~fine-
ment of all processing and memory to the processor not only
makes data handling and processing entirely dependent upon the
processor, but also reduces the speed at which transactions can
be processed.
3~Z
Brief Summary of the Invention
In accordance with the present invention, there is
provided a distributed function communication system wherein
data is transmLtted between a processor and a plurality of inter-
mediate equipment tenminals, hereinafter referred to as master
terminals. Each master terminal has the responsibility of con-
trolling the exchange of data between the processor and plural
remote terminals, hereinafter referred to as slave terminalc.
Data transmitted from the processor is retimed at the master
terminals so that, to the slave terminals, it appears to have
originated at the processor; namely, to the slave terminals, the
master terminals which control their operation are transparent.
By compensatin~ for timing errors-resulting from data trans-
mission, as well as providing drive, the master terminals enable
data to be transmitted ov~r distances normally considered
prohibitive.
Each master terminal is provided with memory and its
own common control microprocessor module. In addition, at each
master terninal there may be provided plural peripheral devices,
like those at the slave terminals. Polling of the peripheral
equipment from the processor is effected by using protected
and non-protected addresses transmitted serially over the common
bus. The protected addresses are used or system addresses and
local peripheral device addresses at the master terminals, while
non-protected addresses are reserved for peripheral devices at
the remote slave terminals. Protocollogic is defined by the
ti3~ J
control circuitry within each master terminal which is con-
structed to inhibit data processing to ensure correct timing of
the data. If the common control module (CCM) is ready for the
next transaction, the control circuitry compares the current
CCM state with the current data serialization logic state and
either inhibits future processing by the CCM or times in the
data to the CCM; serialization will also be permitted if
commonality is allowed. The control circuitry also provides
synchronization and includes registers to store the states of
various parts of the logic. The memory within each master serves
the master terminal itself and a plurality of peripheral devices
located at the slave locations controlled by the master terminal,
thus affording greater utilization of system memory, and
taking advantage of common control coding. No memory is required
at the slave terminals. The invention is further directed to a
communications system for transmitting data between a data
processor and a plruality of peripheral devices controlled by
said processor comprising first interface means coupled over a
first common bus to said processor and responsive to data trans-
mission instructions including bus control signals and the addressof a prescribed peripheral device supplied over said first
common bus from the processor for generating a data code in
accordance with the received data transmission instruction and
which identifies the address of the peripheral device and the
type of transaction to be carried out between said processor and
said addressed peripheral device, second interface means coupled
over a second common bus to said plurality of peripheral devices
addressable by said processor, a transmission line connected be-
tween said first and second interface means, said first interface
means includes a first storage means for storing the data trans-
~2~GZ
mission instructions received from the processor over the firstcommon bus and for outputting the data code when enabled, first
means for generating a transmission clock, first circuit means
responsive to receiving said bus control signals for generating
a control signal, first means coupled to said first clock gener-
ating means and said first circuit means for transmitting the
data code at said transmission clock rate from said first storage
: means to said second interface means over said transmission line
in response to the generation of said first control signal, said
second interface means includes means coupled to said trans-
mission line for reconstructing said transmission clock from
the transmitted data code, second storage means coupled to said
transmission line and said second common bus for storing the
data code received from said first interface means, second circuit
means coupled to said second storage means and said second common
bus for reconstructing from said transmitted data said bus control
signals, and third circuit means coupled to said second storage
means and said clock reconstructing means for enabling said
second storage means to output to the addressed peripheral device
over said common bus said data code wherein the first and second
interface means are transparent to the addressed peripheral device.
Brief Description of the Drawinqs
. _
Figure 1 is a general system diagram of a distributed
terminal communication system;
Figure 2 is a basic block diagram of the constituent
components of a master terminal of the system of Figure l;
Figure 3 is a basic block diagram of the constituent
components of a slave terminal of the system of Figure l;
Figure 4 is a circuit diagram of the master terminal
bus adapter of Figure 2;
Figure 5 is a circuit diagram of the slave terminal
bus adapter of Figure 3;
4a -
~26~6;~
Figure 6 is a schematic diagram of the modulator-
driver circuitry used by the master and slave bus adapters of
Flgures 4 and 5, respectively;
Figure 7 is a schematic diagram of the receiver-
demodulator circuitry used by the master and slave bus adapters
of Figures 4 and 5, respectively;
Figures 8A, 8B and 8C, taken toge~her, are a schematic
diagram of the control circuit of the master bus adapter of
Figure 4; and
Figures 9A and 9B, taken together, are a schematic
diagram of the control circuit of the slave bus adapter of
Figure 5.
Detailed Description
The basic system configuration of the master-slave
distributed function communication system is illustrated in
Figure 1. The general data processing equipment includes the
usual host computer 107 connected by way of communicatlon lines
106 to a store controller 104. Disposed at a plurality of loca-
tions remote from the computer 107 are perlpheral devicest such
as keyboard input devices, displays, etc., shown in Figure 3,
which require data transmission between themselves and data
processing equipment. In accordance with the present invention,
between the data processing equipment and the peripheral devices
there are provided a master terminal 101, a plurality of associ-
ated slave terminals 102, and a master-slave communication link
103, For purposes of simplification, Figure 1 depicts only a
G2
s~ngle master terlTinal 101 linked to three slave terminals 102.
Suffice it to say that more or less than three slave terminals
102 may be associated wlth a single master terminal 101 via M/S
link 103 and the number of master tenninals 101 which communiaate
with the store controller 104 by communication lines 105 will
likewise vary according to the overall size of the system and
the amount of peripheral equipment to be serviced by the data
processing equipment.
As is shown in Figure 2, each master terminal 101 con-
10 sists of its own memory 202 which includes conventional ROM and
RAM structure and a common control module (CCM) 201 connected
with each other and with other components of the terminal over a
common control bus 211. The master terminal may include its awn
peripheral devices such as a keyboard 207, numeric display 206,
operator display 205, printer 204, and a miscellaneous control
device 203, such as a cash drawer. Data transmission with the
computer 107 is effected through a communication adpater 209,
whereas data transmission between the master 101 and slave 102
terminals takes place by way of a master bus adapter 208, the
20 details of which will be described below. Power for these com-
ponents is supplied over power bus 212 from pc~wer supply 210.
Such master terminal peripheral devices are conventional, employ-
ing a data register, status register, and an output buffer. The
common control module 201 contains a microprocessor, such as an
Intel 8080 microprocessor. Since those skilled in the art are
famlliar with the construction and operation of various types of
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common bus communication adapters and peripheral equipment, a
detailed description of the same will be omitted; this equipment
will only be brlefly referred to herelnafter where necessary to
facilitate the description of the c~nunlcation system of the
invention. Of course, details of the structure and operation of
the master bus adapter 208, which controls data communication with
the associated slave terminals 102, will be described below in
connection with Figures 4 and 6 through 8.
Referring now to Figure 3, each slave terminal 102
consists of a slave bus adapter 301 which communicates with an
associated master bus adapter (such as adapter 208 in Figure 2)
over a communications link such as a lOOn twisted pair line 103.
Within each slave terminal there are a plurality of remote (in
the sense of the processor) peripheral devices such as a key-
board 302, numeric display 303, operator display 304, printer
305, and a miscellaneous control device 306 (such as a cash
drawer). Such peripheral devices are connected with the slave
bus adapter 301 by way of common control bus 308. Power supply
307 supplies power for the components of the slave tenmlnal over
power bus 309. As was described above with respect to the
description of the general layout of a master terminal 101, the
various peripheral components of the slave terminal 102, per se,
do not form the sub~ect of the invention, and ~hls equipment
will be briefly described only as necessary for completing the
description of the communication system.
The basic circuitry of the respectiYe master terminal
llZti;~
and slave terminal bus adapters 208 and 301 is illustrated in
Figures 4 and 5. Each adapter includes serial data modulation
and driver circuitry for transmission to the receiver/demodula-
tor of the bus adapter to which it is connected.
The master ~erminal bus adapter 208 contains a
modulator-driver 402, a transmission clock 403, a receiver/
demodulator 404, and a control circuit 401. The control circuit
(the detalls of which will be described below with reference to
Figure 8) includes parallel/serial converter circuitry as well
as protocol/control logic for interfacing data between the
common control bus and the transmission lines to associated
slaves. The control circuit 401 serializes the datato be
transmitted to its associated slave terminals and controls the
operation of the data modulator and driver 402 by a transmit
enable signal XMIT ENAB. The data is clocked out at the trans-
mission rate generated by transmission clock 403.
The modulator driver 402, illustrated in Figure 6,
carries out Manchester coding and includes an exclusive-OR gate
601 which receives the serial data and the clock signal. The
output of the exclusive-OR gate 601 is connected to one input
of gate 602 and, through an inverter 603, to one input of gate
604. Gates 602 and 604 are enabled by the XMIT ENAB signal
from the master control circuit 401, thereby enabling the serial
data to be supplied to driver amplifier 605 and clocked out over
a 100n twisted pair line to the receiver/demodulation circuitry
of the slave bus adapter 301.
-- 8 --
~Z6~62
When data is received from a slave bus adapter in
response to a read instruction, the received signals are demod-
ulated by receiver/demodulator 404, the details of which will
now be described with reference to Figure 7. The serial data
clocked out from the bus adapter 301 at a slave terminal is
supplied to a threshold detector 701 which, in turn, controls a
flip-flop 702. One output of the flip-flop is coup~ed through
an inuerter 703 to a double-edge differentiator 704. The
output of the inverter 703 is the received data and is supplied
over line RX DATA to master control circuit 401. The received
clock is generated by delaying the double-differentiated data
signal through one-shot 705 and is coupled to control circuit
~01 via line RX CLK.
Like the master terminal bus adapter 208, the slave
terminal bus adapter 301 (Fig. 5) includes a modulator-driver
502, a receiver-demodulator 501, and a transmission clock 503.
These components are structurally and operationally the same
as those in the master terminal bus adapter so that the expla-
nation given above for Figures 6 and 7 is applicable for compo-
nents 501-503 in Figure 5. The slave bus adapter 301 also
includes a control circuit 504 (the details of which will be
described below with reference to Figure 9) for controlling the
transmission of data from a peripheral device in response to a
read request from the master terminal 101 and the writing of
data into an addressed peripheral device.
The control circuits of the master terminal bus
~ ~ Z 6 ~6 ~
adapter and slave terminal bus adapter 301 are shown in detail
in Figures 8 and 9, respectively. Included in these circuits
are arrangements of combinational logic and parallel-serial/
serial parallel register circuitry for effectlng the transmission
of data between the central processor 107 and a slave terminal
peripheral device 302-306 under the control of the master
terminal 101. To simplify an understanding of the structure
and operation of not only these circuits, per se, but the over-
all master-slave communication system of the invention, a
description of the respective data transmissions which are
implemented by the inventive system, under the control of the
circuits of Figures 8 and 9, will be presented.
There are three basic types of commun~cation transac-
tions which can take place between the data processor (be it the
host computer 107 or the common control module 201 of the
master terminal 101) and a piece of peripheral equipment. One
is a "write" transaction whereby a peripheral device is addressed
and data from the processor is transmitted to and written into
the peripheral device. Another is a "read" transaction whereby
a peripheral device is addressed and data contained within the
device is transmitted from the peripheral device to the process-
or~ Still another is a "reset" transaction which occurs on
power up and power down to initialize the processor and
peripheral equipment so as to prevent transient noise ~rom p~wer
up/down cycles from entering the peripheral devices and memory.
Except for reset) these transactions will be described on an
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1126~2
individual basis in accordance with the operations carried out
by each of the master control circuits of Figure 8 and the slave
control circuit of Figure 9, respectively.
Master Control Circuit ~FiRure 8)
Data Format
The master terminal 101 transmits a word to a slave
terminal 102 whenever an input/output (read or write) instruc-
tion is received from the processor 107 and the address
designated corresponds to a non-protected address of the master
terminal. As was described above, data is transmitted in serial
format, so that from the master terminal there will be
transmitted a series of bits which include, as part of the
transmitted code, a field of address information specifying a
particular slave terminal with which a transaction is to occur.
For purposes of illustration, a maximum code length
of twenty bits is assumed1 having a pair of sync bits (Sl, S2),
a reset false bit (RF), a read/write not bit (R/W), an eight
bit address field (A7-A0), and an eight bit data field ~D7-D0).
A twenty bit data format is transmitted by a master terminal
for a write transaction or for a continuous reset transmission,
and is coded as follows:
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:~LlZt~
g -~ .
.,~ .q
.,
0 3
U~
h U~
E~ ,1
u ~ cq
.,., ~a
~O ~
~ 3 J, o
td ~, ~ a
~; ~; ~r; 3
~ ~ Z ~ ~ 2
The control field of the twenty bit code consists of the reset
false bit (RF) and the read/write not bit (R/W). During a "write"
transaction, the reset bit is a "1", while the read/write not
bit is a "0". D~ring a read transaction, since no data is sent
to a slave terminal 102, the data bits are dropped, so that a
twelve bit code will be transmitted from the master terminal
101. The reset false bit is again a "1", while the read/write
not bit is a "1".
To create the respective read and write codes to be
transmitted from the master terminal, the control circuit shown
in Figure 8 includes a parallel-serial/serial-parallel register
Rl and a set of associated combinational logic. The register Rl
is comprised of conventional cascaded registers, the stages of
which are connected to accept a maximum of tweDty parallel input
bits Sl through Do and to clock out these bits in serial format;
similarly, the register Rl will receive a serial input data
stream and selected stages, i.e. the data bit stages for D7
through Do have their outputs connected to data line d~ivers
DDl, from which parallel output data bits are obtained in re-
sponse to the receipt of a serial data stream read out from aslave bus adapter 301. The address bits A7 through Ao and the
data bits D7 through Do are coupled to respective parallel lines
of a portable bus connector PTB as part of the common control
bus for coupling the bits with the microprocessor of the common
control module 201 (Figure 2).
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llZ6~6Z
Read Transaction
In the process of effecting a data exchange between a
peripheral device and the processor 107, an initial examination
is made to determine whether or not the peripheral device is
capable of accepting information. Thus, before data can be
written into a peripheral device, its status register is read
to determine if the device can receive another word, and if it
can, a write transaction will then proceed. Referring to
Figure 8 (made up of 8A, 8B and 8C), on the common control bus
from ~e common control module (CCM) a "1" will be received at
the R/W input to gate G6 and the RESET input to gate G7 will
also be a "1" (Fig. 8A). Thus 9 the RF and R/W inputs to register
Rl are both "1", the sync bits are strapped to "0" and "1"
respectively, and the address of the peripheral to be read is
supplied over bit lines A7 through Ao. There are no data blts
since the transaction is not a "write" transaction.
Transmit Mode
The three most significant address bits (A7, A6 and As)
are strapped through inverters (not shown) to the inputs of gate
G10 (Fig. 8A) to effect a preselection of an available non-pro-
tected address field, i.e. reserved for peripher~l devices 302-
306 at the slave terminals 102. Of course, any appropriate
number of address b1ts may be so strapped depending upon the
system's requirements. In the present example, of the 255
available addresses, the protected addresses are addresses 0 - 63,
reserved for master peripherals and prescribed system addresses,
while addresses 64 - 255 (due to the A5 - A7 bit strapping) are
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1~2~
non-protected addresses reserved for slave peripheral devices.
Proceeding on the assumption that there exists a peripheral
device at the interrogated address and this device contains
data, then the peripheral cycle request line PCR will be "0'~
and the data enable line DE will be "0" to enable gate Gll and,
consequently, gate G12, through inverters I2 and 13. The output
of gate G6 sets flip-flop FFl and flip-flop FF3. The output of
gate Gll is delayed by a one-shot delay Dl and toggles flip-
flops FF2 and FF3. Since flip-flop FF3 has been set by gate G6,
it is reset by the toggle to provide an output at Q. The Q
outputs of flip-flops FF2 and FF3 are coupled through gate G13
(Fig. 8B~ and inverter I6 to the READY line.
The READY line is connected to the microprocessor of
the common control module 201 through the common control bus 211
and is used to inhibit processing by the microprocessor under
various conditions. First, upon a read command from the micro-
processor, processing is inhibited, so as to allow data to be
read from a slave ter~inal peripheral device and presented to
the master terminal. Second, if a read command or another write
command is attempted during a write transaction, processing will
be inhibited throughout the remainder of the write transactlon
and throughout the read transaction but will resume when the
current transaction is completed. The Q output of flip-flop FF2
inhibits processing through the READY line via gate G13 and
inverter 16 if a transaction is still in progress, while flip-
-
flop FF3 through its Q output inhibits processing during a read
6Z
transaction. Flip~flop FF~ is cleared or reset by a transac-
tlon termination signal supplied through inverter I8, while flip-
flop FF3 is cleared by gate G14, as will be described below.
Proceeding,now, through the assumed transaction of
reading a slave peripheral containing data, the output of gate
G12 (Fig. 8A) is coupled through gate G16 to toggle flip-flop
FF4 (Fig. 8B), which effectively synchronizes the operation of
the data serializaticn process. Flip-flop FF4 will be reset via
inverter I5 upon transmission of the data code to the slave
terminal. Toggling of flip-flop FF4 causes a reset or clear
signal to be supplied via gate G9 and delay D2 to the R/CL
terminal of register Rl to clear and prepare the register to load
and serialize data. Such reset or clear signal originates at
the RESET output of gate G7 which is coupled through inverter Il
and gate G8 to gate G9.
Gate G9 (Fig. 8B) also enables the Q output of clocked
JK flip-flop FF5, to clear the flip-flops FF8 and FF9 (Fig. 8C),
whlch form a shift register SR2, and also clear the flip-flop
FF10 of timing counter Cl. Gate G17 is now enabled by the shift
register SR2 and flip-flop FF5 to supply a transmission enable
signal over line ENAB XMIT (Fig 8C) to one input of gate Gl
(Fig. 8A). The output of gate Gl is coupled through gate G3
to clock the data which has been parallel-loaded into register
Rl out over the serial data output to the exclusive-OR gate 601
of the modulator-driver (shown in detail in Figure 6). As a
result, a twelve bit serlal data stream conslsting of the two
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sync bits (S~ o~; S2 = "l"), the reset bit (RF ~ "l"), the
read/write not bit (R/W = "l"j, and eight address bits (A7 - Ao)
will be transmitted to the slave terminals 102 associated with
this particular master terminal lOl.
Termination of the read transmission occurs after all
the twelve bits o~ the data code have been serialized out of
the register Rl. The count of twelve is detected by the counter
Cl (Fig. 8C), which counts the clock pulses supplied from the
transmission clock via counter module CMl and enables gate G18
10 (Fig. 8B) via lines A, B and D, with the fourth input to gate G18
being coupled to the Q output of flip-flop FFl which was set, as
described above, due to the occurrence of a read transaction.
After the last or twelfth bit 013t from register Rl has been
serialized out, gate G18 is enabled to set via inverter I7 the
first flip-~lop stage (FF8) of shi~t register SR2 (Fig. 8C), and
gate G17 is disabled to thereb~ remove the ENAB XMIT signal from
gate Gl and the driver modulator, so that data serialization is
terminated. The second flip-flop stage (FF9) of the shift
register SR2 receives a "l" with the next clock pulse~ to enable
20 the ENAB RX output line to gates G2 and G4 (Fig. 8A), so as to
permit the master terminal to receive the data read out from
the slave terminal. The flip-flop FF9 provides a one bit delay
between the completion of the read transmission and enable
receive signal ENAB RX.
Rece ive Mode
With the ENAB RX input to gates G2 and G4 now enabled,
~ 2
the register Rl is now ready to recelve data read out from a
slave terminal 102. The only permissible data format trans-
mitted by a slave termlnal ls a ten bit data code as follows:
¦ SlTs~D7lD6lD5lD4lD3lD2lDllDo ¦
.,
8 bit data field
I Sync bits (Sl-O;S2=l)
(No control field or address field need be transmitted since
the only transmission required from a slave tenminal is a reply
to an interrogation.) As the serial data train from the
receiver/demodulatur 404 (Figure 4) is received at one input of
gate G5, it is serially clocked by gates G2 and G3 into the
cascaded stages of the register Rl. The first bit loaded into
register Rl is the "0" of the sync bit Sl and the second bit
loaded is the "1" of the sync bit S2. When the second sync bit
(S2 ~ "1") is clocked into the ninth stage of the register
(corresponding to the Ao bit of the address field) all the data
bits will have been clocked into the Do - D7 stages of the
register and loading of the data read out from the addressed
slave peripheral device Ls now completed. The Ao bit now dis-
ables gate G4 to prevent further clocking of data via gates G2and G3. At the same time, gate G4 causes flip-flop FF3 to be
reset through gate G14, to enable the microprocessor of the
common control module 201 via the READY line, so that the micro-
processor can now read the data on the PTB lines Do - D7 from
the data line drivers DDl.
To prevent the system operation from being delayed by
- 18 -
il26;~2
a misoperation of a slave device, such as due to power loss,
loss of sync, noise, etc., the logic is configured to permit
the slave 102 only a prescrlbed amount of time to supply its
data to the master tenminal l0l. To this end, selected outputs
from the counter Cl and the D7 bit from the register Rl are
supplied to inputs of gate Gl5, which causes flip-flop FF3 to
be reset through gate Gl4, so as to remove the common control
module inhibit signal from the READY line. Namely, gate Gl5
and counter Cl provide a slave response time-out.
Write Transaction
Transmit Mode
.
Completion of the read transaction means that the con-
tent status register of the peripheral device has been read and
its associated output buffer is empty and ready to receive data
from the common control module 201. The CCM now supplies a ~oi.
on the R/W line input to gate G6, as opposed to a "l" for the
read transaction described above. With flip-flop FFl being
reset by the output gate G7, which receives a "l" on input line
. _
RESET, the Q output of the flip-flop FFl will be a "0", while
its Q output will be a "l". Also, the set input of flip-flop
FF3 is a "0", each of flip-flops FF2 and FF3 being again toggled
by the output of delay Dl. Otherwise, the initial conditions
are the same as for a read transaction9 so that a description
of the same sequence of operations of the control circuit need
not be repeated.
In addition to loading and serializing the sync,
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1 1 2 ~ ~ 2
control and address fields, as occurred during a read transac-
tion, the reglster Rl also loads and serializes elght data
bits Do - D7 to produce a twenty bit data code to be trans-
mitted to a slave terminal. As it did during a read transaction,
counter Cl will count clock pulses fromthe trans~ission clock,
and it terminates transmission after twenty clock pulses have
been counted. This is accomplished by way of a connection from
the Q output from flip-flop FFl (Fig. 8A) to one input of gate
Gl9 (Fig. 8B), and selectively connecting appropriate A, B and E
outputs from the counter Cl corresponding to a count of twenty
bits to the gate Gl9 and to the JK flip-flop FF5. Note that
at the count of twelve, gate G18 is not triggered as it was
during a read transaction, since the Q output of flip-flop FFl
is a "0"; therefore, no signal is present on the ENAB RX line.
Once the twenty bit write code has been clocked out, the Q
output of the JK flip-flop FF5 is coupled through inverter 18
and causes flip-flop FF2 to be cleared, which removes the
inhibit signal fromthe READY line if one was present. The Q
output of flip-flop FF5 is also coupled through gate G8, delay
D3, gate G16, toggled flip-flop FF4 and gate G9 (Figs. 8A and
8B) to prepare the system for the next transaction. The shift
register SRl, comprising the flip-flops FF6 and FF7, is
coupled to the JK flip-flop FF5 to provide a three bit dead
time between words to allow slave termlnals 102 to reset for
the next transaction.
As was described previously, flip-flop FF2 inhibits
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the microprocessor of the CCM 201 if another transaction is
attempted during a write transaction. Thus, if, during the
above-described write transactionr the microprocessor was to
attempt a read or write transaction, flip-flop FF2, whose
reset input R is coupled through inverter I8 to the Q output of
the JK flip-flop FF5~ will inhibit processing, via the READY
line, until the counter Cl detects a complete clocking out of
data (twenty bits) and switches the Q output of flip-flop FF5.
Of course, once that data has been serialized out to the
master/slave link 103, flip-flop FF2 will no longer inhibit
processing vla the READY line~ so that a new transaction may
commence. Flip-flop FF5 is cleared by gate G20 via inverter
I4 coupled to gate G12 (Fig. 8A).
Slave_Control Circuit (Fi~ . 9)
Data Format
As was described above in connection with the con-
struction and operation of the master control circuit 401, dur-
ing a read transaction the slave control circuit 504 will
receive a twelve bit code consisting of the bits: Sl, S2, RF,
R/W, A7, A6, A5, A4, A3, A2, Al, Ao, and will respond with a
ten bit code consisting of the bits: Sl, S2, D7, D~, Ds, D4, D3,
D2, Dl, Do. During a ~rite transaction, the slave terminal
control circuit will receive a twenty bit code consisting of
the bits: Sl, S2, RF, R/W, A7, A6, A5, A4, A3, A2, Al, Ao, D7
D6, D5, D4, D3, D~, Dl, Do but no data is transmitted by the
- slave in replyO The slave control circuit 504 will be now
- 21 -
1~2f~6Z
described in connection with the two types of transactions (read
and write).
Read Transaction
Receive Mode
Referring now to Figure 9, which is made up of 9A and
9B and shows the details of a slave control circuit, as the
serial bit stream Sl, S2, RF, R/W, A7, A6, A5, A4, A3, A2, Al, Ao
is demodulated by receiver demodulator 501 (Fig. 5) it is applied
to the serial data lnputs of registers R2 and R3 (Fig. 9A).
Serial-parallel reglster R2 receives the serialized data from
the master terminal and delivers the received address blts over
parallel lines Ao - A7 to the portable bus PTB, and through gate
G21 via inverters I9 and I10 clocks the sync bit (S2 D 1) ~ the
reset bit (RF - 1), and the read/write not bit (R/W ~ 1) into
flip-flop register stages FFll, FF12, and FF13. The Q output
of flip-flop FF13 (Fig. 9B) is connected to gate G21 (Fig. 9A)
via line SYNC F to insure synchronization of the system in
accordance with "01" sync pattern of the Sl and S2 bits. Gate
G22, which is, in effect, a decoder, detects the sync bits and
through delay D4, causes a delayed output to be supplied in
line RESET F. The period of the delay D4 is longer than the
rate at which words are supplied to the slave terminal, so that
the RESET F line supplied, in effect, a continuous reset signal.
Also connected to the outputs of flip-flop FFll through
FF13 are a pair of decoding gates G27 and G28, which decode the
control field to determine whether a read or write transaction
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:~lZtj3~;2
is taking place. For the assumed read transaction, gate G28
supplies an output through invert I12 and gate G30, to cause
the Q output of flip-flop FF14 to go high. The output of in-
verter I12 is also supplied to a one-shot delay D6, to initially
clear register R3, so that it may load the data bits from the
output buffer of the addressed peripheral device. A signal
will be supplied on the ARF line (address recognize false) from
a peripheral device to inverter I13 whenever a peripheral device
associated with this slave terminal recognizes its address on
lines Ao through A7 of the PTB. Assuming, of course, that there
is an addressed peripheral device from whose output buffer data
is to be read, then both inputs of gate G30 are enabled. A
signal is now provided onthe XMIT ENAB line from flip-flop FF14.
The output of gate G28, which decodes a read trans-
action, is also coupled (RF) through gate G32 to delays D7 and
D8 which respectively provide the PCR and DE signals which are
duplicates of the like named signals on the common bus, but for
associated with the slave peripheral device bus in this instance.
Transmit Mode
The XMIT ENAB output from flip-flop FF14 (Fig. 9B)
via gates G24 and G25 (Fig. 9A), causes the serial-parallelt
parallel-serial register R3 to serially clock out the sync bits
(Sl ~ 09 S2 = 1) and the eight data bits(D7 - Do) received from
the output buffer of the addressed peripheral deviceS to the
modulator driver 502 (Fig. 5) for transmission to the master
terminal 101.
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1 ~ 2 ~ ~ 2
The Q output of flip-flop FF14 (Fig. 9B) also triggers
flip-flop FF15 and delay D5, so that the stages of register R3
which receive the parallel data from the addressed slave
peripheral, appearing at the D7 - Do inputs, will be cleared by
gate G26 (Fig. 9A) after the data has been clocked out by the
transmission clock signal XMIT CLK and the XMIT ENAB signals
supplied to gate G24 and coupled through gate G25 to the clock
input oi register R3. Counter module CM3 (Fig. 9B3 and gate
G33 are connected to time out the clocking of the ten bit code
serialized out of register R3, and then reset flip-flop FF14
causing the XMIT ENAB line to go low and terminate serialization
by the register R3.
Write Transaction (Receive Mode)
For a write transaction from the master terminal 101,
the full twenty bit code, described previously, will be supplied
as a serial data train to registers R2 and R3. Since the R/W
bit of the control field is a "0", the ~ output of flip-flop
FFll is a "1", so as to enable gate G27 (Fig. 9A). The WRF out-
put of gate G27 is supplied to counter module CM2 and to
inverter Ill. The WR output of inverter Ill enables gate G31,
to supply a signal on line RX ENAB, so that, via gates G23 and
G25 (Fig. 9A), register R3 will clock in the serial data bits
D7 - Do and supply the data to data line drivers DD2. The
parallel data bits D7 ~ Do are now written into the addressed
peripheral device via the portable bus PTB.
The clock pulses received on the RX CLK input to gate
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llZ6362
G29 are counted until counter module CM2 counts that the eight
data blts~ D7 - Do~ have been clocked into register R3. Invert-
er I14 now lnhibits the RX ENAB line, so that the received bits
are no longer clocked through the stages of the register ~3, and
signals are generated on the PCR and DE outputs of delays D7 and
D8 to clock the received data to the addressed slave device on
the slave bus.
As will be appreciated by the foregoing description of
the invention, read and write transactions can be conducted
between a data processor and peripheral equipment by provlding
an interface data-retiming and transmission system which to the
processor and to the peripheral is transparent. The interface
handling of the data via the master and slave bus adapters re-
quires no special knowledge by the processor and memory as to
which peripheral devices are local and which are remote. The
processor and memory can be confined to the master terminal
containing the c ~on control bus to the microprocessor. Also~
due to the duplication of common bus signals at the slave bus,
it is to be understood that the remote peripherals do not know
whether they are on the same bus as the processor and memory
or at a remote slave location.
While we have shown and described one embodiment in
accordance with the present invention, it is understood that the
same is not limited thereto but is susceptible of numerous
changes and modifications as known to a person skilled in the
art, and we therefore do not wish to be limited to the details
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~ ~ Z ~3 ~ Z
shown and described herein but i.ntend to cover all such changes
and modifications as are obvious to one of ordinary skill in the
art.
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