Note : Les descriptions sont présentées dans la langue officielle dans laquelle elles ont été soumises.
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~-LAW TO FLOATING POINT CONVERTER
Technical Field
Thls inventîon relates to digital signal pro-
5 cessing and, more particularly, to the converting of a
~-law code word into a floating point representation
thereof.
Background of the Invention
Pulse code modulation (PCM) signals consist, in
10 general, of a series of binary code words wherein each
word represents an instantaneous value of a periodically
sampled and quantized analog signal. In normal usage
these code words are transmitted in the form of a serial
bit stream to a receiving station where they are decoded
15 into a reconstructed version of the original analog
signal. In ~etween, the processing of the digital signal
usually involves various operations being performed
on the PCM words. For example, the present inventor in
"A Twelve-Channel Digital Echo Canceler", IEEE
20 Transactions on Communications, Vol. COM 26, No. 5
;
(May 1978), pp. 647~653 discloses an echo canceller
employing floating point multipliers. However, the
typical PCM word is not in a floating point representation.
Hence, a converting operation need be performed to convert
25 the PCM code word into a floating point representation
thereof. A floating point representation of a number z
is a representation of the form
z = S A B (1)
w~ere S is the polarity, or sign, of the number; A is its
30 mantissa; B is its base, which generally equals two in a
binary system; and ~ is its exponent.
Where the PCM code is linear, i.e., having no
compression or expansion, a simple shifting of the binary
35 digits can produce a multiplication or division in powers
o~ two. A linear code is therefore readily adapted to a
floating point representation. On the other hand, where
the PCM code is nonlinear, e.g., a compressed code, a
simple shift does not produce a uniform multiplication or
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division. The telecommunications art usually employs a
nonlinear PCM code.
In a special issue on digital signal processing,
an article by A. Kundig, "Digital Filtering in PCM
Telephone Systems", IEE~ Transactions on Audio and
Electroacoustics, Vol. AU-18, No. 4 (December 1970), pp.
412-417 discloses a method for converting a nonlinear PCM
word, encoded according to the so-called A-law, into a
floating point number representation. The Kundig method
succeeds, in part, because of the close relationship
between A-law encodings and floating point encodings.
A second nonlinear PCM code, known as the ~law,
approximates the compression function:
_ log (l~x~
- 15 Y ~ log (1+~) . (2)
Known ~-law to floating point converter arrangements are
of two types. One type includes a memory which, responsive
to the PCM word, has extended from a location therein the
floating point representation. For a common 8-bit PCM
word having one sign bit such arrangements typically
employ a memory having at least 27 locations, each
location with an eight bit floating point representation.
The second type is a two stage converter including a ~-law
; to fixed point conversion followed by a fixed point to
floating point conversion. ~ence, known ~-law to floating
-~ point converters tend to be expensive.
Summary of the Invention
In accordance with an aspect of the invention there is
provided a converter including input terminals adapted to
receive a ~-law code word, said code word including a sign
bit representing polarity, characteristic bits representing
segment value, and mantissa bits representing a code word
quantizing step; output terminals adapted to transmit a
floating point representation o~ said code word, said
representation including a sign, an exponent and a floating
point mantissa; means for extending said polarity and said
~ D ~.
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segment value to first predetermined ones of said output
terminals and characterized in that said converter further
comprises: a translator responsive to said segment value
and to a prefixed quantizing step for providing a reference
mantissa; means responsive to said reference mantissa and
to said code word quantizing step for providing said
floating point mantissa; means for extending said floating
point mantissa to second predetermined ones of said output
terminals whereby said floating point representation
includes said sign, said exponent, and said floating point
mantissa.
This and other problems are mitigated in accordance
with the principles of my invention by an improved ~-law
to floating point converter. The converter includes a
translator for providing a reference mantissa in response
to the segment value of the ~-law code word and to a
prefixed quantizing step. The floating point mantissa is
then obtained by adding the reference mantissa and the
quantizing step of the code word. The floating point
exponent is the segment value; while the floating point
sign is equal to the sign of the code word.
Brief Description of the Drawing
The various features of the present invention
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will be readily understood from the following detailed
description taken in conjunction with the drawings in
which:
FIG. 1 is a diagram illustrating a ~-law code;
~IG. 2 is a table which shows the analog output
levels for ~ = 255, ~-law code;
FIG. 3 is a table which shows the value of the
reference and floating point mantissas for a ~ = 255,
~-law code; and
FIG. 4 is a diagram illustrating apparatus for
converting a u-law code word into a floating point
representation thereof in accordance with the principles
of my invention.
Detailed Description
In considering nonlinear PCM codes, a typical
compressed PCM code X(L, V) comprises m binary digits,
called "characteristic bits" for representing a segment L,
and n binary digits, called "mantissa bits" for
representing a quantizing step V in segment L. In
addition, it is common that the compressed code include a
single polarity bit S. The resultant code word is then
a bit stream of length (m + n + 1) bits. Also, the total
number ~ of segments in one polarity is equal to 2m and
the total number N of quantizing steps in each segmen-t
is equal to 2n.
The usual compressed digital signal is then
given by
X(L, V) = V + ~L (3)
and the expanded, or linearized, signal is given by
Y(L, V) = AL(V + P) - Q (4)
where for the~-law
~L = 2L
P = N + a
Q = N + a-c
35 where a is the segment edge parameter, i.e., the transition
from one segment to the next, and c is the centering
parameter, i.e., the off~set of the curve from the origin.
In FIG. 1 there is shown a representation of a ~-law
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characteristic curve where c = 0. Henceforth, and without
loss of generality but rather for ease of description,
we consider c = 0 and a = 0.5. Furthermore, to simplify
the discussion that follows, we assume N = 16 (n = 4) and
5 M = 8 (m = 3). Hence, the expanded, or linearized, signal
of equation (4), with the aforementioned assumptions
incorporated and ignoring momentarily the sign bit, is
given by
Y(L, V) = 2L (V + 16.5) - 16.5 ~ (5)
10 The polarity or sign, bit is the eighth bit of the PCM
code word. The foregoing assumptions are common to the
8-bit, ~= 255 PCM code word which is used by the ~ell
System in its digital carrier facilities and which is
characterized by a bit stream of the form SLlL2L3VlV2V3V~
15 where ~ is the sign bit; LlL2L3 define the particular
segment L of the code and are the (m=) three characteristic
bits; and VlV2V3V4 define the quantizing step V and are
the (n=) four mantissa bits.
FIG. 2 is a table which shows the analog output
20 levels Y(L, V) from equation (5). From the table it can
be seen that a 13-bit linear code will represent the range
of values encompassed by the magnitude of the analog
signal. Equation (5) can be rewritten in floating
representation as
Y(L, V) = 2L U(L/ V) (6)
where the exponent L is the segment value and the floating
point mantissa U(L, V) is given as:
U(L, V) = V + 16.5 - 2L (16~5)o (7)
It should be noted that the mantissa of equation (7) can
30 itself be rewritten as
U(L, V) = U(L, 0) t V (8)
where U(L, 0) is a reference mantissa having the value
of the floating point mantissa for a particular quantizing
step, here for V = 0. FIG. 3 is a table which shows
35 the floating point mantissa values from equation (7).
It should be observed that the first row of the table
in FIG. 3 provides the values of the reference mantissa
U(L, 0). It is clear that equation (8) can be solved
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by simply adding quantizing step V to the reference
mantissa shown illustratively as the first row value
from FIG. 3. It should also be observed that the
magnitude of the difference between U(L, V) and its
5 closest, nearby integer (i.e., closest larger or
smaller integer as the case may be) does not exceed 15/32.
Using the latter observation, consider the set of
consecutive integers {0, 1, 2, ..., 31}. Let U5(L, V)
denote the integer from the set which integer is the
integer closest to U(L, V). Referencing the table in
FIG. 3 and the set {0, 1, 2, ..., 31} it becomes clear
that the magnitude of the observed difference between
U(L, V) and U5(L, V) is less than one-half a quantizing
step, i.e.,
¦U(L, V) U5(L, V) ¦ < 15/32 < 1/2. (9)
As a result, U(L, V) can be approximated by U5(L, V) and
yet introduce an error no larger than one~half quantizing
step. Noteworthy an error of such magnitude is
possible in the original quantization. Fortuitously
20 and consistent with the principles of my invention, the
expanded signal Y(L, V) can be provided by way of
equation (6) using U5(L, V) as an approximation of U(L, V)
thereby obtaining the floating point representation
2LU5(L, V). Also, U5(L~ V) can be provided using
inexpensive memory of combinatorial apparatus together
with simple adder apparatus~ Too, only five bits are
needed to specify U5(L, V)~
FIG. 4 includes illustrative apparatus
incorporating the principles of my invention. A PCM code
30 word with sign bit S; characteristic bits Ll, L2, L3
~ for representing segment L; and mantissa bits Vl, V2
`~ `V3, V4 for representing quantizing step V is provided to
respective, parallel input terminals 10; 11 1, 11-2, 11-3;
and 12-1, 12-2, 12-3, 12-4 of converter 100, processed
thereby and provided as a floating point representation
including sign bit S; characteristic bits Ll, L2, L3
for representing the exponent; and five-bit floating
point mantissa U5(L, V) having bits U5(L, V)l through
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U5(L, V)5 respectively to parallel output terminals 20;
21-1, 21-2, 21-3; and 22-1 through 22-5 for extension to
floating point apparatus, not shown. More particularly,
mantissa bits Vl, V2, V3, V4 are extended in parallel
5 from input terminals 12-1, 12-2, 12-3, 12-4 to
respective first inputs of adder 90. Characteristic
bits Ll, L2, L3 are extended from input terminals 11-1,
11-2, 11-3 jointly to exponent output terminals 21-1, 21-2,
21-3 and to first inputs of translator 200 for providing a
5~bit approximation U5~L, 0) of reference mantissa
U(L, 0). Specifically, translator 200, responsive to
input segment value L, extends an output reference
mantissa U5(L, 0) in accord with the translation set
forth in Table I below:
TABLE 1
L U5(L,
O O
1 8
2 12
3 14
4 15
16
6 16
7 16
25 Table I, it will be seen, reflects the values of U(L, 0)
from the first row of the table in FIG. 3, rounded to the
closest integer. Translator 200 may be implemented by a
memory device or by relatively inexpensive combinatorial
logic. Noteworthy, rather than requiring the prior art
2~m+n=)7 memory locations, converter 100, when implemented
using a memory for translator 200, requires only 2(m=)3
memory locations. My illustrative embodiment of trans-
lator 200 is by way of combinatorial logic for providing
an output U5(L, 0) in accord with Table I responsive to
a segment value L.
The output of translator 200 is extended in
parallel to second inputs of adder 90. In accord with
equation (8), the output of adder 90 is U5(L, V) for
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extension to the output terminals 22-1 through 22-5
concurrently with characteristic bits Ll, L2, L3 and sign
bit S being extended respectively to output terminals 21-1,
21 2~ 21-3 and 20. Advantageously, no clocking logic is
5 needed to convert the ~ law code word into a floating
point representation thereof.
To still more particularly illustrate the
operation of illustrative converter 100, its operation
in providing a floating point representation of an
10 expanded signal Y(L, V) having L = 5 and V = 6 is described.
First, turning to FIG. 2, the value of the linearized
signal Y(5, 6) iS 703.5 while from FIG. 3 the values
oE U(5, O) and U(5, 6) are respectively 15-63/64 and
21-63/64. Clearly U(5, 6) = U(5, O) + 6 in accord with
15 equation (8). Using a five bit approximation for U(5, 6)
and from Table I above, translator 200 is to provide a
value ~5 (5~ 0) = 16 which in binary format ~Us (5r )5 ~
Us (5, 0) 4, . . ., Us (5~ ) 1" equals the bitstream "10000".
Using the ~-law to floating point converter of FIG. 4,
20 a floating point representation equivalent to a value
of Y(5, 6) equaling 704 is extended to the output terminals
of converter 100. That is, referring to equation (1), the
polarity is extended to terminal 20; the exponent is
extended as a segment value L = 5~ which in binary is
25 the bitstream "101", to terminals 21-1, 21-2~ 21-3; and
the floating point mantissa is extended as a value
Us(5, 6) = 16, which in binary is the bits~ream "10000",
to terminals 22-5 to 22-1 respectively. To obtain
Us(5~ 6) ~ in accord with equation ~8), mantissa bits
30 Vl~ V2~ V3, V4 are extended from terminals 12-1 through
12-4 to respective first inputs of a standard binary
adder 90. Adder 90, may for example, be a conventional
adder, such as the four bit Texas Instrument adder 74283
having coupled thereto overflow logic 95 including
35 inverters 26 and 27 and NAND gate 60 for providi~ng a logic
one, as bit U5(L, V) 5 to terminal 22-5, when either
- bit Us (L~ 0) 5 is a logic one or there is a carry logic
one from adder 90. In order to obtain Us (L~ V) ~ the
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reference mantissa U5(L, 0) is extended from translator
200 to respective second inputs of adder 90. The
reference mantissa is determined by inverters 20 and 25,
NAND gates 30 and 40, included within translator 200.
5 In particular, a segment value L = 5 is extended in
binary form "1011' from respective inputs 11-1, 11-2
and 11-3 of converter 100. Bit Ll, being a binary one,
is extended to first inputs of NAND gates 30-2, 30-4 and
30-6 and, after inversion by inverter 50-1, is extended
10 as a binary zero to a first input of NAND gate 30-1.
Segment bit L2, being a binary zero, is extended to a
second input of NAND gate 30-2 and a first input of NAND
~ates 30~3 and 30~5 and, after being inverted to a binary
one by inverter 50-2, to a second input of NAND gates 30-1,
15 30-4 and 30-6. Segment bit L3, being a binary one, is
extended to a third input of NAND gates 30-1 and 30-6 and
a second input of NAND gate 30-5 and, after being inverted
to a binary zero by inverter 50-3, to a third input of
NAND gates 30-2 and 30-4 and a second input of NAN~
20 gate 30-3. It being well known that the output of a NAND
yate is a logic one if any input is a logic zero, the
outputs of WAND gates 30-1, 30-2, 30-3, 30-4, 30-5 are
logic ones while the output of gate 30-6 is a logic zero.
The NAND gate outputs are inverted by inverter 25 and NAND
25 gates 40 1, 40-2, ~0-3, 40-4 to provide U5 ~6, 0) as the
bit stream "10000", or U5(~, 0) = 16, to the second input
of adder 90 as per Table I.
Although the invention has been described and
- illustrated in detail, it is to be understood that the
30 same is by way of illustration only. Various modifica-
tions will occur to those skilled in the art. For example,
the approximation of U(L, V) by a five bit integer U5(L, V)
taken from the set of consecutive integers {0, 1, 2, ....
31} is only by way of example. The value U(L, V) could be
35 approximated by U6(L, V), the closest number in the set
{0, 1/2, 1, 1-1/2, ..., 31, 31-1/2} to U(L, V). Only one
more bit is needed to specify U6(L, V) than to specify
U5(L, V). Still further approximations exist. Thus,
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the spirit and scope of the invention are limited only
by the appended claims.
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