BASCULE J-K A CIRCUIT LOGIQUE A MODE NON SATURE POUVANT ETRE UTILISE DANS LES TESTS DE NON-FONCTIONNEMENT

J-K FLIP FLAP UTILIZING CURRENT MODE LOGIC WITH NON-FUNCTIONAL TEST CAPABILITY

Abrégé anglais

ABSTRACT
A 5-bit, J-K type master/slave edge triggered flip-flop
register with buffered outputs is disclosed. Each J and K input
is preceded by a two input AND gate to provide for greater design
flexibility. In addition, provision has been made to reset all
five flip-flop stages of the register synchronously as well as to
configure the device as an inverting shift register for nonfunc-
tional test (NFT) techniques.
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Revendications

C L A I M S
1. A plural bit J-K type master/slave edge triggered flip-
flop register with buffered outputs and reset and nonfunctional
test capabilities utilizing current mode logic (CML) comprising:
a plurality of data stages each of said data
stages further comprising:
an input section, a master/slave latch
section, and a buffered output;
first means for connecting the output of
said master/slave latch of each of said data
stages to the input section of the succeeding
stage;
second means for connecting the output of
said master/slave latch of said last of said
plurality of data stages to a single output
differential buffer for providing an <IMG>
signal;
third means for providing a <IMG> signal
to the input section of said first of said
plurality of data stages;
a control section connected to said plurality
of data stages for providing a reset and an NFT select
signal to each of said input sections, said control section
responsive to a NFTR signal and a NFTS signal; and,
a clock section connected to each of said plurality
of data stages for providing clock signals to each of said
master/slave latch sections, said clocking section responsive
to said NFTR signal, said NFTS signal, and a <IMG> signal, and
a $ signal.
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2. The plural bit J-K type master/slave edge triggered
flip flop register as recited in claim 1, wherein said input
section further comprises:
a three input-two output differential lower level
gate responsive to the differential output of the master/
slave latch of the preceding data stage and said NFT signal
from said control section for providing a differential
output signal to said master/slave latch section;
a first two input upper level gate responsive to a
J10 and a J11 input signal;
a second two input upper level gate responsive to
a K10 and a K11 input signal;
a three input-three output hybrid differential
lower level gate connected to said first and said second
two input upper level gates and responsive to the differential
output of the master/slave latch of that input sections data
stage and said reset signal from said control section;
a two input AND gate with differential output for
use in said first of said data stages, said two input AND
gate responsive to an <IMG> signal and said NFT signal from
said control section.
3. The plural bit J-K master/slave edge triggered flip-flop
register as recited in claim 2, wherein said master/slave latch
further comprises:
a first three input-two output differential upper
level gate, a first differential upper level gate, a second
differential upper level gate, a third differential upper
level gate, a first differential lower level gate, and a
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second differential lower level gate;
first means for connecting the outputs of said
input section to said three input-two output differential
upper level gate;
second means for connecting the output of said three
input-two output differential upper level gate to the input
and output of said first differential upper level gate;
third means of connecting the output of said first
differential upper level gate to the input of said second
differential upper level gate;
third means for connecting the output of said
second differential upper level gate to the input and
output of said third differential upper level gate;
fourth means for connecting the output of said
third differential upper level gate to the said three
input-three output hybrid differential lower level gate
of said input section;
said first differential lower level gate having its
inverting output connected to said three input-two output
differential upper level gate in its non-inverting output
connected to said first differential upper level gate; and,
said second differential lower level gate having
its inverting output connected to said second differential
upper level gate and its non-inverting output connected to
said third differential upper level gate.
4. The five bit J-K master/slave edge triggered flip-flop
register as recited in claim 3, wherein said buffered output
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further comprises:
a first and a second emitter follower connected to
the outputs of said third differential upper level gate,
the outputs of said emitter followers connected to the input
of a differential output buffer for providing a buffered
output signal.
5. A plural bit J-K master/slave edge triggered flip-flop
register as recited in claim 1, wherein said clocking section
further comprises:
- a clock generator for providing a differential
clock signal to each of said master/slave latch sections,
said clock signals not responsive to said $ signals
transitions when said <IMG> signal is a logical "1" and said
NFTR and said NFTS signals are logical "0's".
6. The plural bit J-K master/slave edge triggered flip-
flop register as recited in claim 1, wherein said control
section further comprises:
a single input upper level gate responsive to said
NFTR signal;
a first emitter follower connected to said NFTS
signal, the output of said first emitter follower connected
to a mixed lower level gate, the inverting output of said
mixed lower level gate connected to said single input upper
level gate, said non-inverting output of said mixed lower
level gate connected to a second emitter follower and also
providing said NFT signal to said first of said plurality
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of data stages, the output of said second emitter follower
providing said NFT signal to each of said plurality of
said data stages, a third emitter follower connected to the
output of said single input upper level gate for providing
said reset signal to said plurality of said data stages.
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Description

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FIELD OF THE INVENTION
, This invention relates generally to electronic logiccircuitry used in electronic data processing equipment and,
more specifically, to logic circuitry utilizing soft-saturating
05 current mode logic (CML) in high density integrated circuits.
BACKGROUND OF THE INVENTION
In the evolution of digital electronic circuitry many
different logic family types have been developed to increase the
switching times and throughput of digital processing apparatus~
These families, such as diode-transistor, resistor-transistor,
; and transistor-transistor (T2L), etc., have been stepping stones
in digital design evolution. At the present time, current mode
logic (CML) presents the best economic tradeoff between the cost
~ of manufacture and performance characteristics. As noted in the
; 15 first five cross references to this appllcation, the first
generation of the CML logic family has been in existence for some
time. The next step in the evolutionary process, of which this
instant invention is a part, concerns improvements in the power
, consumption, switching speeds, gate intensity, and magnitude of
integration. The development of the second generation of CML -
logic circuitry provides for an enhanced performance of the data
?l processing system, and at the same time lowers the cost/performance ratio.
In order that this second generation of CML devices may
l present the maximum throughput improvement possible, it is
-~ 25 necessary that a large selection of such circuits be available;~ for the designer's use.
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SUMMARY OF THE INVENTION
The 5-bit J-K master/slave, edge triggered flip-flop
register with buffered outputs in accordance with the instant
invention includes a variety of CML circuits configured in such
; 05 a manner as to provide bothaa J-K flip-flop functionality with
synchronous reset capability, as well as being able to be con-
figured into a 5-bit serial shift register with an inverter between
each bit. The serial shift ability was designed to enhance
testing capability of individual registers, as well as the data
processing system in general. The technique utilizing this
inverting shift register is known as Nonfunctional Testing (NFT).
The J-K register is configured such that on the falling
edge of the clock (the clock pulse going from a logical "O" to
a logical "1", utilizing the negative logic convention), each J-K
flip-flop will be strobed and an output signal dependent upon the
state of the four J-K inputs will be generated, or all outputs
` will be reset to zero or each output stage of each J-K flip-flop
will be tied together as an inverting shift register. Each J-K
flip-flop comprises an input section followed by a master/slave
latch and a buffered output. A control section generates the
signals that condition the input section to provide for either
normal J-K operation, resetting of the register, or nonfunctional
testing of the register. When the clock is not inhibited, and is
in the logical zero state, data in the slave latch is locked in
and the master latch accepts data. On the falling edge of the
clock the data in the master latch is locked in and passed through
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to the slave latch which in turn is connected to the buffered
outputs. So long as the clock is in the logical "1" state, the
output of the master latch preconditions the slave latch such
that when the clock again returns to a logical "0", the master
latch accepts new data and the data previously stored in the
master latch is locked into the slave latch.
The instant invention operates in a hybrid mode of
operations insofar as that input and output signals swing 0.5
VDC in going from a logical "0" to a logical "1" and vice versa,
whereas the signals, once buffered by the input section of cir-
cuitry are used in a differential mode to improve the signal
switching characteristics. This increase in performance is made
possible by the fact that in the differential mode switching
occurs with only a 0.25 VDC voltage change. This decrease in the
dv/dt necessary for intra-circuit communication provides for
improved switching speed characteristic, while at the same time
maintaining the same noise immunity generally provided by the
0.5 VDC swing of the input and output signals. This result is
! made possible because even though the input signals change a
0.5 VDC in going from a logical "0" to a logical "1" or vice
~; versa, the internal reference on the circuits receiving these
signals is set at a level -0.26 VDC below the logical zero state
` so that the difference in the base voltages of the switching
transistors is always approximately a . 26 volts VDC. In the
instant invention, this 0.26 VDC differential is maintained by
eliminating the use of a reference and applying the differential
voltage output of the internal logic circuit.
In accordance with the present invention, there is
provided a p}ural J-K type master/slave edge triggered flip-
flop register with buffered outputs and reset and non-functional
test capabilities utilizing current mode logic including a
plurality of data stages, each of the data stages having an
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input section, a master/slave latch and a buffered output;
apparatus for connecting the output of the master/slave latch
of each of the data stages to the input section of the succeed-
ing stage, apparatus for connecting the output of the master/-
slave latch of said last of the plurality of data stages to
a single output differential buffer for providing a nonfunctional
output signal and apparatus for providing a nonfunctional input
signal to the output section of the first of the plurality of
data stages. The instant invention further includes a control
section connected to the plurality of data stages for providing
a reset and a nonfunctional test select signal to each of the
input sections of the data stages, the control section being
responsive to nonfunctional test signals and the invention also
further includes a clock section connected to each of the
plurality of data stages for providing clock signals to each
of the master/slave latch sections, the clocking section res-
ponsive to the nonfunctional test signals and other signals.
; It is, therefore, an object of this invention to pro-
vide for a 5-bit, master/slave, edge triggered J-K flip-flop
register with buffered outputs.
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Another object of this invention is to implement the 5-bit
J-K flip-flop register in CML logic.
Still another object of the instant invention is to provide
for maximum switching characteristics without degrading other
05 circuit parameters by using internal circuit outputs in a
differential mode.
It is a still further object of the instant invention to
provide for nonfunctional testing of the J-K flip-flop register.
These and other objects and features of the invention will
be more fully understood from the following detailed description
and appended claims when taken in conjunction with the attached
drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
Figures lA and lB are a schematic diagram of the instant
invention.
Figures 2 through 18 are the schematic representations and
their respective electrical schematics for the various CML
building blocks utilized in the instant invention.
; Figure l9 is a timing diagram of the instant invention.
DESCRIPTION OF THE PREFERR~D EMBODIMENT
In reading the following description of the preferred embodi-
ment, it is important to note that the instant invention utilizes
; a negative logic convention, i.e., a logical "0" i8 represented by
a more positive DC voltage than a logical "1". It is also
important to note the hybrid nature of the circuits used in the
instant invention. All inputs and outputs of the J-K register
utilize a 0.0 VDC level as a logical "0" and a -0.5 VDC as a
logical "l", whereas much of the internal circuitry utilizes the
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differential mode of operation where a logical "1" or a logical
"0" is represented by a differential voltage between the two
input or output signals of 0.25 VDC, the polarity of that
differential voltage indicating whether or not a logical "0" or a
05 logical "1" is being transmitted from the signal source. Keeping
this in mind, the basic building block shown in Figures 2 through
18 will now be described so as to facilitate an understanding of
the overall J-K register schematic shown in Figure 1.
The emitter follower of Figures 2A and 2B permit buffering
of circuit outputs as well as providing for voltage translation
of approximately 0.8 VDC. An additional benefit to be derived
from the emitter follower is that common outputs from the various
emitter followers may be wired AND'ed and thereby eliminate the
need for additional logic circuitry. In operation, a logical "0"
input at point A turns transistor Ql on hard and provides a current
path to ground through Rl from VEE. The output voltage at point B
will then be approximately -0.8 VDC for a logical "0". A logical
nl" at A produces an output voltage at B of -1.3 VDC, Ql presenting
a greater resistance with its decreased base drive. Figures 3A
and 3B represent a typical lower level gate that is not driven
differentially. Input A is driven from the output of an emitter
follower, wherein a logical "0" i9 represented by -.8 VDC and a
logical "1" by a -1.3 VDC. When the A input is a logical "1",
transistor Q2, whose base is driven by a reference voltage of
approximately -1.05 V~C, is turned on and a current source is
provided via output C. When the A input is a logical "0",
transistor Ql is forward biased and it provides a current source
via output B. Only one of the two outputs may provide a current
source at any one time, however, at least one of the two outputs
is always active.
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Figures 4A and 4B are the schematic and electrical diagrams
of a single input upper level gate. A is the signal input and B
is connected to a current source such as that provided from the
outputs of Figure 3. Outputs C and D are the logical output of
05 input A AND'ed with current source B. In this instance the device
is operable only when an active current source is applied at B.
Without B being active, both C and D outputs are logical "0's",
regardless of the A input. When an active current source is
connected to B, output D will be a logical "1" when A is a
logical "1" and C will be a logical "0". When A is a logical "0",
D will be a logical "0" and C a logical "1".
Figures 5A and 5B represent a dual input upper level gate
similar to that æhown in Figures 4A and 4B, except that transis-
', tors Ql and Q2 are connected in parallel. This configurationallows for an`'AND"function to be performed and, as noted in the
A discussion of Figures 4A and 4B, an active current source has to
be provided at point C of Figure 5 for anything other than a
i logical "0" to appear at outputs ~ and D. Output E will represent
the logical AND'ing of inputs A and B and the current source,
; 20 whereas output D is indicative of the complementary function of
' A~B concurrent with current source C.
' Figures 6A and 6B represent the master/slave latch
arrangements utilized in the instant invention. While a detailed
description of the operation of the two different circuit types
are given for the descriptions of Figures 13 and 14, it should be
noted that in this configuration the circuit types are slightly
modified, i.e., whereas normally both differential upper level
gates would have individual output resistors, it is shown in
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Figure 6B that resistors R1 and R2 are shared by both differential
upper level gates. This modification is necessary any time outputs
of two different gates are wired together. Were it not for the
sharing of one common resistor, the output resistor of each gate
05 would be tied in parallel with the output resistor of the other
circuits causing an effective resistance less than that necessary
to develop the proper voltage. In operation, the voltage
differential between A and B will cause either transistor Q1 or
Q2 to conduct. When the voltage potential at A is positive with respect
to input B, Q1 will attempt to conduct and if input E is positive
with respect to F, Q3 will also conduct providing a current source
through Q1 and Q3 and R1 which induces a negative voltage at H.
The potential at G will be 0 VDC since there is no current path
to the current source, transistors Q2, Q4, Q5, and Q6 being in a
nonconducting state. If, on the other hand, B is positive with
respect to A, Q2 will conduct permitting C to become a current
i~ source and allowing either Q5 or Q6 to conduct depending on the
previous voltages at inputs G and H. If G were positive with
respect to H, Q5~would conduct and Q6 would be turned off and
current would flow from the current source through transistors
, Q2 and Q5 as well as R1 to produce a negative voltage at H, Gwould remain at 0 VDC since no current will flow through resistor
R2. The circuit is set up such that when switching occurs between
transistors Q1 and Q2, the voltage previously impressed at G
- 25 and H will be present at the base of their respective transistors,
Q5 and Q6, until such time as one or the other has had an oppor-
, tunity to turn on through the current source provided through
either Q1 or Q2, even though there is, in fact, a momentary
transient when transistor Q1 turns off and Q2 conducts or vice
, 30 versa.
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Figures 7A and 7B are diagrams of a three input AND gate
that operates on single-ended inputs, wherein a logical "0" is
0.5 VDC greater than the voltage used to represent a logical "1".
As shown in Figure 7B, a logical "0" input at either A, B, or C
05 will cause either transistor Q3, Q2, or Ql to conduct and pro-
vide a current path from the current source through that tran~-
istor and Rl to ground causing a logical "1" output at D.
Transistor Q4, whose base will be at a lower potential than the
voltage used to represent a logical "0" will be nonconducting
: 10 and a logical "0" output will appear at E. When inputs A, B,
and C are logical "l's", neither transistor Q1, Q2, or Q3 will
conduct but Q4, its base now being more positive than the bases
; of transistors Ql through Q3 will conduct with a logical "0"
output at D and a logical "1" output at E.
Figures 8A and 8B represent a true complement gate that
acts as a buffer for input signal A as well as providing for its
complementary output. In this case, when A is a logical "0",
0.0 VDC, transistor Ql will conduct and a logical "1" will
appear at output B, whereas transistor Q2, being in the noncon-
ductive state will cause a logical "0" to appear at C. When A
; is a logical "1", transistor Ql will be nonconductive, and
transistor Q2 will conduct causing a logical "1" to appear at
C, and a logical "0" at B.
Figures 9A and 9B are diagrams of a single output differen-
tial buffer that provides a logical "0" at C when A is positive
with respect to B and provides a logical "1" at C when B is
positive with respect to A. With A positive with respect to B
; transistor Ql conducts, transistor Q2 is turned off and C is
connected to ground through resistor Rl. When B is positive
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with respect to A, Q2 provides a current path from the current
source through Rl which generates a logical "1" voltage at C.
The mixed lower level gate represented by Figures lOA and
lOB is a hybrid device that exhibits some of the characteristics
05 of a lower level gate and some of the characteristics of an
- upper level gate. As shown in Figure lOB, when A is positive with
respect to the reference voltage, Ql will conduct and provide a
current source through output B.~ Q2, being in effect an open
circuit, will cause a zero voltage to appear at output C.
However, when A is negative with respect to the reference, a
logical "1" is generated at C by the current flow through transis-
tor Q2 and resistor Rl. --
Figures llA and llB represent a level shifter that closely
resembles the emitter follower shown in Figure 2 except that
the output B is taken off the opposite side of Rl. This technique
is utilized to allow voltage translation of the logical outputs
that are greater in magnitude than the voltage drop across
transistor Ql noted for the emitter follower circuit. The reasons
for this additional voltage translation is explained more fully
in the detailed description of Figure 1.
:~,
~ Figures 12A and 12B represent a differential output buffer
; circuit for the differential mode signals. ~he relative voltage
between A and B causes a proportional differential voltage
. :1
`1 between outputs C and D, the magnitude of that output differential
being controlled by the selection of resistors Rl and R2, in this
i,; case either a -0.5 VDC or 0.0 VDC output. When A is positive
-~ with respect to B, transistor Ql will conduct and transistor Q2
. will be turned off causing a negative voltage to appear at D and
a 0.0 VDC signal at C. When B is positive with respect to A,
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transistor Q2 conducts, transistor Ql is turned off and current
is supplied through Q2 and R2 to provide a negative voltage at
C, while D is held at 0.0 VDC.
Figures 13A and 13B represent a three input-three output
05 hybrid differential lower level gate that is operable in a
differential mode with potential override. This capability is
provided by using inputs A and B in normal differential mode
such that Ql will conduct when A is positive with respect to B and
and Q2 will conduct when B is positive with respect to A. However,
transistor Q3 is utilized to override the differential voltage
appearing between A and B by applying a more positive input at
C. When C is more positive than either inputs A or B, transistor
Q3 will provide the only current source from the gates.
Figures 14A and 14B represent a three input-two output
hybrid differential upper level gate. When enabled by a current
source at input F, the differential output D-E is controlled by
the differential input A-B or C. Signals to inputs A and B
are differential mode signals with a .25 VDC swing, whereas input
C is connected to a single-ended output with a 0.25 VDC swing,
a logical "0" being a 0.0 VDC signal and a logical "1" a -0.25
VDC signal.
Figures 15A and 15B represent an inverter circuit for signal
A and as such is very similar to the true complement gate shown
in Figures 8A and 8B except that the true output is not available.
In this case, when the A input is a logical "0", Ql will conduct
and the output at B will be a logical "l". When A is a logical
"l", Ql will not be conducting and the output of B will be a
logical "0".
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Figures 16A and 16B represent a differential upper level gate
which is active only when an active current source is connected
to input E. When so enabled, a voltage differential between A
and B, which is positive with respect to B, will cause transistor
05 Ql to turn on and current to flow through Ql and Rl forcing a
negative voltage at D and a 0.0 VDC signal at C, conversely when
B is positive with respect to A transistor Ql is turned off,
'I transistor Q2 conducts, and current flow causes a negative voltage
to appear at C and 0 VDC at D.
10Figures 17A and 17B represent a differential lower level
gate. Outputs C and D provide current sources through either
transistor Ql or Q2. When A is positive with respect to B, the
D output is an active current source and output C presents an
open circuit condition. When B is positive with respect to A,
C is an active current source and the D output represents an open
circuit.
Figures 18A and 18B represent a two input AND gate that
operates off of the 0 and -.5 VDC signals. Where inputs A and
B are both "l's", transistor Q3 conducts and a logical "1" appears
at output C and 0 VDC at D. When either A and B or both is a 0,
Ql or Q2 or Ql and Q2 conduct and a logical "1" appears at D and a
logical "0" at C.
Figure 19 is a timing diagram showing the interrelationships
between the control signals, the J-K inputs, and the flip-flop
outputs.
;.
~With an understanding of the basic CML building blocks
i.j
discussed above the description of the invention described in
Figures lA and lB should be more readily understandable. As
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shown in Figure lA, the J-K flip-flop register comprises five
nearly identical circuit structures denoted by elements 1001
through 1015, 1101 through 1115, 1201 through 1215, 1301 through
1315, and 1401 through 1416, as well as a control section and
clocking mechanism depicted in Figure lB. Two minor differences
do occur in the first and last flip-flop circuits. AND gate 1001
differs from the corresponding gates 1101, 1201, 1301, and 1401
in that it is a two input gate operating on one-half volt single-
ended input signals and its corresponding gate in the other flip-
flops are three input-two input differential hybrid lower
level gates. The s~cond difference occurs in the last stage
where gate 1416 provides an NFTOUT signal that is utilized when
the register is in the nonfunctional test mode. One furthe~ aspect
of the register should be noted at this time is that when the QSi
~i
data is input into the (i+l) flip-flop, it is connected in such
a manner that an inversion occurs between each stage. This is
necessary in order that the NFTOUT output data will be more
` meaningful during nonfunctional testing.
It will be helpful in understanding the following detailed
description to refer to the following list of logic equations and
; state table.
LOGIC EQUATIONS
; i = 0,1,2,3,4 (Bit #)
(Selector/Data) DSl = Jio-Jil-Qsi-NFTR-NFTs`
+ ~Kio.Kil).QSi.NFTR.NFTS + QS(i-l).NFTS
. (Master/Data) QMi = $.QM¢$.QMi + ($.QM¢~).DSi
(Master/¢$) QM¢$ = $.QM¢$ + ~(¢$ + NFTR + NFTS)
(Slave) QSi = ($-QM¢$)-QSi + $.QM¢$.QMi
(Buffer) Zi = QSi
(NFT) NFTOUT = ~
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ST-ATE TABLE NEXT STATE OF
$ ~ NFTR NFTS Jio-Jil Kio.Kil QSi QSi
1 0 0 X X Qsi Qsi
o o o o QSi QSi
05 ~ 0 0 0 1 0 1 0
O O O 0 1 O
O O O 1 1 ~i Qsi
X 1 0 X X 0
X X 1 X X QS (i-l) QS ~i-l)
'
With the foregoing in mind, it can be seen that when the
NFTS input to Figure lB is a logical "1", the output of mixed
lower level gate 1509 to emitter follower 1510 is a logical "1".
The output of 1509 connected to single input upper level gate 1501
does not provide a current source to that gate and it is, therefore,
not operative, the YZ output being equal to a logical "0". The
true output of gate 1509 is then directly connected to the two
~; input AND gate 1001 enabling the NFTIN signal to pass through
that gate. At the same time the output of emitter follower 1510
is connected to the three input-two output hybrid differential
, 20 lower level gates 1101, 1201, 1301, and 1401 enabling each of
j~ those gates. Each of gates 1101, 1201, 1301 and 1401 are
~ basically the same as gates 1011, 1111, etc., except that output
4 D, shown in Figure 13B is connected to ground through a resistor
j and outputs E and F are connected to ground through a common
.-`! 25 resistor as well. This implementation provides logic signal
outputs at D and E-F rather than acting as current sources.
As previously noted, the YZ output of fifth gate 1501 is a logical
"0" causing the output of emitter follower 1502 to also be a
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logical "0". That output is in turn connected to the
three input-three output hybrid differential lower level gates
1411, 1311, 1211, 1111, and 1011. A "0" at that input forces
the output connected to gate 1002, or 1102, or 1202, etc., to be
05 a logical "1". This forced set of conditions is caused by the
different voltage level inputs to the three input-three output
hybrid differential lower level gates. As previously noted, the
output levels from the level shifters provide for a logical "0"
output of a -1.05 VDC and a logical "1" output of a -1.3 VDC,
however, the output of emitter follower 1502 provides for a
logical "0" output of a -.8 VDC and a logical "1" output of a -1.3
VDC. Since no base of the transistor pair connected to the out-
puts of the ~evel shifter may rise above a -1.05 VDC level, the
transistor connected to the output of emitter follower 1502
will turn on harder and starve the other transistor pair from
sinking any current. In this manner, the output of emitter
follower 1502, when in a logical "0" state, overrides the differen-
tial inputs to that gate and prevents either of the two input
upper level gates 1009, or 1010 from being enabled, while at the
same time setting the input conditions to at three input-two
output differential upper level gate 1002 such that it will be
;; controlled by the output of gate 1001 when data is transferred
into the master/slave latch. In the four subsequent flip-flops
the data into the master/slave latch will be controlled from gates
1101, 1201, 1301, and 1401 which is, as previously described,
the complementary output of the preceding flip-flop.
` To reset the flip-flop register the NFTS signal must be a
"0" and NFTR must be a "l". In this manner the single input
'~
"
.
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017
upper level gate 1501 is enabled via mixed lower level gate 1509.
At the same time the three input-two output hybrid lower level
gates 1101, 1201, 1301, and 1401 are disabled by the logical "0"
output signal from the emitter follower 1510 and the two input
05 AND gate 1001 is disabled by the logical "0" output from gate 1509
causing a logical "0" to appear across its differential output.
In a similar manner, a logical "0" emitter output from emitter
follower 1502 forces the three input-three output hybrid
differential lower level gates 1011, 1111, 1211, 1311, and 1411
to a "0" output level, once again caused by the logical "0"
output from emitter follower 1502's more positive logical "0"
output.
With both the NFTR and NFTS signals a logical "0" the data
appearing at DSi is governed by the J and K inputs to the two
input upper level gates 1009 and 1010, 1109, and 1110, etc., as
well as the current flip-flop output. The following data
selection process, although specifically referencing the first
flip-flop in the register will be equally applicable to all of
; them.
The outputs from level shifters 1014 and 1015 enables either
two input upper level gate 1109 or 1010 depending upon the
output at QSo . When QSo iS a logical "1", gate 1010 will be
~i enabled, while gate 1009 is disabled. If Koo, Kol are both
"l's", a logical "0" will appear at DSo, whereas if either Koo
or Kol is a logical "0", a logical "1" will appear at DSo.
It can be seen that when QSo iS equal to a "1", the K input gate
will always be selected and DSo will be a "1" when Koo~Kol is a
` logical "0" and will be a "0" when Koo~Kol is a logical "1".
When QSo iS a logical "0", gate 1009 is enabled and when
, ~ ~
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~, .

- \
~129~17
Joo.Jol is a logical "1", DSo will be a logical "1" and when
Joo-Jol is a logical "0", DSo will be a logical "0". Combining
the information gathered when the QSo is a logical "1" and a
logical "0" with the various DSo values obtained with the
05 various J-K combinations provides the basis for lines two through
five of the state table previously given.
When the ~ input is a logical "1" and the NFTR and NFTS
input signals are logical "O's", no changes occur to the master/
slave latch clock, $.QM~$, causing the latch to preserve the
data currently in the latch, regardless of the number of transi-
tions of the clock, $.
Having established the criteria for data selection the
operation of the clocking mechanism and master/slave latch will
now be explained. As shown in Figure lB, two input upper level gate
1503 is enabled whenever the clock signal, $, is a logical "0".
If either of the inputs to gate 1503 is a logical "0", the output
of that gate will be a logical "1", however, the manner in which
the output of gate 1503 is connected to the input of differential
upper level gate 1504 causes the input to gate 1504 to be the
complement of the actual output of gate 1503. So long as this is
the case, the master/slave latch clock ($.QM¢$) will follow
; the basic clock, $, i.e., it will go from a logical "0" to a
logical "1" and a logical "0" to a logical "1" when the $ clock
; does. When the ~ signal is a "1" and the other input to gate
1503 is a "1" (which only occurs when both the NFTR- and NFTS
`~ signals are logical "O's") the master/slave latch clock will not
change states but will remain in a logical "0". Assuming now
that the output of gate 1503 is a logical "0" so that the master/
; .
:
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"
. . , ... . I

~29~7
slave latch clock will follow clock, $, the description of the
master/slave latch arrangement that follows, while specifically
referencing the first flip-flop will be equally applicable to
all similar circuits in the register~ With the foregoing
05 established criteria a logical "0" clock signal, $, will cause
gates 1002 and 1005 to be enabled latching in the previous QMo
output at QSo and causing the DSo output to appear at QMo. In
this state input changes at DSo will appear at QMo~ but will not
; affect the output at QSo, since gate 1004 is not enabled and can,
; 10 therefore, not pass the QMo information to QSo. On the falling
:~ edge of the clock gates 1003 and 1004 are enabled isolating QMo
and QSo from data changes at DSo, while at the same time passing
~ the QMo data to QSo. The QSo output is then buffered and shifted
;: -0.8 VDC by emitter followers 1006 and 1007, whose output is in
turn connected to differential output buffer 1008 which provides
a single-ended output and its complement with a 0.5 VDC swing
;~ at outputs Z0 and Z0. Emitter followers 1006 and 1007 are
; used to keep the bases of the input transistors of gate 1008 below
! ground potential in order that potential saturation of the input
transistors will be avoided and greater overall performance
~ij accomplished. When the clock goes through the "1" to "0" transi-
,; .
tion, the QSo data is latched by differential upper level gate 1005
and gate 1004 is disabled. In this manner data changes at QMo
will not affect the output at QSo. At the same time differential
upper level gate 1002 is once again enabled and the information
appearing at DSo appears at QMo which on the next logical "0"
` to logical "1" transition of $ will be transferred to QSo and Z0.
:
Two points that deserve special attention are the fact that
although the emitter followers are, in Figure lA, followed by
.
.~
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.;
'
:' . , .

9017
level shifters, they are actually the same device, the level
shifting outputs being taken from a point between the voltage t
source and the resistor, whereas the emitter follower outputs are
taken off the emitter of the emitter follower transistor.
05 Additionally, many of the various gate outputs are wired together
to perform a wired OR operation. Whenever this occurs, it should
be noted that only one resistor is shared between the various
output circuits.
While the principles of the instant invention have now
been made clear in an illustrative embodiment, there will be
many modifications of the structure, arrangement, proportion,
elements, material, and components that are obvious to those
skilled in the art without departing from those principles. The
appended claims are, therefore, intended to cover and embrace
any such modifications within the limits of the true scope and
spirit of the invention.
Whst is claimed is:
:,
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