Note : Les descriptions sont présentées dans la langue officielle dans laquelle elles ont été soumises.
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GI-MICRO-156
FABRICATION OF A SEMICO~DUCTOR DEVICE
IN A SIMULATED EPITAXIAL LAYER
Background of the Invention
The present invention relates to a
method of fabricating a semiconductor device and,
more particularly, to a method of fabrication of
monocrystalline semiconductive materials having a
simulated epitaxial layer therein produced by
ion implantation.
The use of epitaxial layers in the
fabrication of semiconductor devices and inte-
grated circuits has been an industry-wide
practice ever since such devices have been
commercially produced. A variety of different
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processes have been utilized to form epitaxial
layers. In one commonly used method, the
substrate surface is first carefully prepared in
order to remove contaminants on an atomic scale
and to provide a crystallographically oriented
surface having an exceptional degree of
planarity. However, even with the most careful
surface preparation, the initial growth of an
epitaxial layer is often characterized by lattice
dislocations and other imperfections. After
suitable surface preparation, the layer is
grown by a vapor deposition process. Vapor
deposition of silicon may be achieved by the
hydrogen reduction of sllicon tetrachloride, tri-
chlorosilane or si1ane at temperatures around
1000C. The flow rates and reactant ratios
are usually quite critical to the process, as
ls the accurate control of temperature during
the deposition process. Moreover, careful
control over the doping levels introduced
during epitaxial deposition i 5 essential.
Because of the delicate nature of the
vapor deposition process, yields obtained in the
production of epitaxial wafers tend to be low,
in large part because of crystal lattice
imperfections and the lack of uniform thickness
in the epitaxial layer from wafer to wafer and
from place to place on individual wafers. For
this reason, the cost of epitaxial wafers tends
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to be relatively high. Since the epitaxial
wafers are the raw materials from which semi-
conductor devices and integrated circuits are
fabricated, the cost of the end products is
likewise increased.
In addition, there is a trend in the
industry towards the use of thinner epitaxial
layers. The need has recently arisen for
epitaxial thicknesses of a few microns or less.
However, uniform epitaxial layers as thin as
this are difficult to produce by vapor
deposltion techniques and the production of
epitaxial layers of one micron thickness by
conventional methods may never be realized on
a com~ercial basis.
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In accordance with ~he present
invention, a method of fabricating a semiconductor
device in a semiconductor body of a given con-
ductivity type is proYided. The method includes
the step of forming a simulated epitaxial layer
of a given thickness below the surface of the
semicQnductor body. The simulated epitaxial
layer is formed by implanting impurit~es, of a
conductivity determining type opposite to the
conductivity type of the body, into the body to
a depth below the surface of the body less than
the desired thickness of the slmulated epitaxial
layer. Thereafter, the semiconductor body is
heated to a temperature above the temperature
wherein substant~al diffusion of the implanted
impurities occurs. The application of heat
to the semiconductor body is terminated after
the implanted impurities have diffused to a
distanoe below the surface of the semiconductor
body approximately equal to the desired thickness
of the simulated epitaxial layer. Designated
a:eas of the simulated epitaxial layer are then
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doped, to alter the conductivity thereof, to
form source and drain regions within the simulated
epitaxial layer. An insulating layer is formed
on the surface of the semiconductor body above
the simulated epitaxial layer at a point between
the source and drain regions. Thereafter,
areas above the source and drain regions and
the insulating layer, respectively, are metal-
lized to form electrodes.
It is preferable to cure lattice
damage and activate the implanted impurities
prior to heating the semiconductor body to
diffuse the im~lanted impurity. This procedure
comprises an additional heating step wherein the
semiconductor body is heated to a temperature
less than the temperature wherein substantial
diffusion of the implanted impurities occur
to cure lattice damage and activate the
implanted impurities.
Preferably, i~plantation of the
impurities takes place through a thin oxide
layer, formed on the surface of the semiconductor
body. Implanting through a thin oxide layer
eliminates surface damage which normally occurs
when implanting impurities at high acceleration
energies.
To the accomplishment of the above
and to such other objects as may hereinafter
appear, the present invention relates to a
method of fabricating a semiconductor device
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in a semiconductor body having a simulated epitax-
ial layer, as described in the following specifica-
tion and taken together with the accompanying
drawings, wherein like numerals refer to like parts,
and in which:
Fig. 1 is a cross-sectional view of a
semiconductor body as it is prepared to undePgo
the process of the present invention;
Fig. 2 is a cross-sectional view of
the semiconductor body after impurities have
been implanted below the surface thereof;
Fig. 3 is a cross-sectional view of the
semiconductor body as it appears after the simu-
lated epitaxial layer has been formed in accordance
with the present invention;
Fig. 4 is a cross-sectional view of the
semiconductor body af~er source and drain regions
have been formed in the simulated epitaxial
layeri
Fig. 5 is a cross-sectional view of
the semiconductor body as same appears after the
gate insulation has been formed on the surface
thereof; and
Fig. 6 is a cross-sectional view of the
completed semiconductor device.
The present invention is applicable to
the fabrication of semiconductor devices in
semiconductor bodies of a variety of known
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semiconductor materials such as silicon,
germanium, gallium arsenide and gallium arsenide
phosphide, for example. Suitable conductivity
type determining impurities for implantation in
each of the various types of semiconductor materials
are well known in the art as are the diffusion
coefficients for the various impurities. For
purposes of illustration, the present invention
will be illustrated by an example wherein N-type
silicon is implanted with boron ions to form a
p-type simulated epitaxial layer. However, it
should be understood that these materials are
chosen for purposes of illustration only and that
the present invention is not to be construed as
being limited to same.
In addition, the example of the method
of the present invention which has been chosen
for purposes of illustration teaches the
formation of a simulated epitaxial layer of
approximately 12 micron thickness. Implantation
energies, impurity dosage and diffusion para-
meters have been selected accordingly. It should
be appreciated, however, that these values are
determined in accordance with the materials
selected, the impurity implanted, and the par-
ticular depth of the simulated epitaxial layer
desired, and should not be construed as a
limitation on the present invention.
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As illustrated in Fig. 1, the process
starts with a body or wafer of n-type silicon 10
having a substantially planar surface 12. It is
preferable to thermally oxidize body 10 to produce
a relatively thin silicon dioxide layer 14 across
the entire surface 12 thereof. Preferably,
silicon dioxide layer 14 is approximately 500
Angstroms thick. The purpose of silicon dioxide
layer 14 is to prevent physical damage to ~he
surface 12 of body 10 which normally occurs
during ion implantation at high acceleration
energies.
Without any photolithographic masking
operations, the entire surface area of the
semiconductor body 10 is implanted with an
impurity which has a conductivity determining
type which is opposite to the conductivity type
of body 10. For example, boron, which will
result in a p-type layer, may be utilized. A
typical implant dose of 3.0 x 1012/Cm2 at
approximately 200 Kev. has proved suitable.
The boron is implanted to a depth below
surface 12 of body 14 which is substantially less
than the desired thickness of the simulated
epitaxial layer. For the implantation para-
meters set forth above, the boron implant will
have a peak concentration of approximately .02
microns below surface 12 with a lower boundary
or periphery approximately .05 microns below
3Q surface 12. The body thus appears as illustrated
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in Fig. 2 with the implanted boron layer being
denoted by numeral 16.
After the implantation step has been
completed, the semiconductory body is cleaned
with hot sulphuric/nitric acid and rinsed with
deionized water. The cleaned semiconductor
body is then preferably subjected to a short
heat treatment for approximately 30 minutes at
950C to cure the lattice damage and activate
the implanted boron ions. It should be noted,
that the heat treatment to cure lattice damage
and activate the implanted impurity takes place
at a temperaturt which is substantially less
than the temperature at which substantial
diffusion of the implanted impurity takes place.
In this case, since boron has a diffusion tem-
perature of approximately 1200C, a temperature
substantially below this value has been
selected.
The semiconductor body is now subjected
to an extensive heat treatment which lasts
approximately 12 hours at approximately 1200C,
in an oxidizing ambient consisting of 2 alone
or in combination with nitrogen, to cause substan-
tial diffusion of the implanted boron ions. The
parameters of this diffusion step are selected
in accordance with the desired impurity surface
concentration and the desired thickness of the
simulated epitaxial layer which is formed. The
parameters selected for the purposes of illus-
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tration will result in a simulated epitaxiallayer approximately 12 microns thick. The
semiconductor body then appears as illustrated
in Fig~ 3, wherein numeral 18 denotes the simulated
epitaxial layer formed in accordance with the
present invention.
After simulated epitaxial layer lg
has been formed, below surface 12 of semiconductor
body 10, the semiconductor body 10 is processed in
a conventional manner to fabricate a semiconductor
device therein. By conventional photolithographic
techniques, a mask 20 is formed on the surface 12
semiccnductor body 10 with openings above the
portions of simulated epitaxial layer 18 where
source and drain regions are to be formed. The
source 22 and drain 24 regions are then formed in
simulated epitaxial layer 18 in any known ~anner
such as by diffusion or ion implantation of an
n-type dopant. After the formation of the source
22 and drain 24 regions, the semiconductor body 10
appears as shown in Fig. 4.
After the source 22 and drain 24 regions
have been formed, mask 20 is removed and a rela-
tively thin insulatin~ layer composed of silicon
dioxide or the like is grown or deposited on
surface 12 of semiconductor body 10. Thereafter,
by a second conventional photolithographic
process, the insulating layer is removed from all
areas of surface 12 except for the area above the
channel of the semiconductor device which extends
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between the source 22 and drain 24 regions. In
this manner, the gate insulation 26 is formed.
The semiconductor body then appears as shown in
Fig. 5.
The semiconductory body is then subjected
to a metallization process where a thin layer of
metal is deposited on the surface of the body and
thereafter selectively removed, by a third
conventional photolithographic process, so as to
form a source electrode 2~ above source region 22,
a drain electrode 30 above drain region 24 and a
gate electrode 32 on the top surface of insulating
layer 26. Leads may then be connected to the
electrodes. The semiconductor body now appears
as shown in Fig. 6.
It will now be appreciated that the
semiconductor device fabricated by the process
of the present invention is identical to
corresponding devices fabricated on semiconductor
bodies where the epitaxial layer is formed by a
conventional technique, except that in the method
of the present invention, the source and drain
regions are formed in a simulated epitaxial layer
created by ion implantation and diffusion,
instead of by conventional chemical vapor
deposition techniques. The simulated epitaxial
layer thus formed has the identical physical and
electrical properties of an epitaxial layer formed
by conventional vapor deposition techniques, but
the need for careful surface preparation of the
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substrate, critical monitoring of flow rates
reactant ratios and temperature, as in the con-
ventional chemical deposition processes, is
eliminated. The simulated epitaxial layer formed
by the process of the present invention has a
more uniform depth, more uniform doping and a
greater degree of crystallographic perfection
than is normally obtainable by conventional
techniques. In addition, the entire process for
forming the simulated epitaxial layer can be
performed with conventional ion implantation
equipment. It is also possible, utilizing the
method of the present invention, to provide a
simulated epitaxial layer wh;ch is thinner than
those which can be produced with conventional
techniques.
While only a single preferred
embodiment of the present invention has been
disclosed herein for purposes of illustration,
it is obvious that many modifications and
variations could be made thereto. It is intended
to cover all of these modifications and variations
which fall within the scope of the present
invention, as defined by the following claims:
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