Note : Les descriptions sont présentées dans la langue officielle dans laquelle elles ont été soumises.
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Field of the Inventlon
; _
6 This inven~ion relates to electronic data processing
7 apparatus. More specifically, it relates to means responsive
8 to signals being transmitted between a computer and a display
9 unit having a keyboard for measuring the response time of the
computer, that is, the time required for completion of a com- !
11 puter activity.
12 Discussion Or the Prior Art
-
13 Many rorms Or data processing systems are known in the
14 art which include data input equipment, a central processor, a
memory and output devices, such as printers, punches, memories,
16 and the like. In these systemQ, data which is either stored in
17 the system or entered lnto the system by an operator, ror example
18 by a keyboard, i~ ~anipulated in accordance with predetermined
19 programs, and then the completed work is displayed visually or
in a printout or otherwise recorded for later uAe. In large
21 scale systems of this general type, use is frequently made Or
22 terminals, placed in different locations for the convenience Or
23jl the u~er, by means of which many different uQers can ha~e access j
24 to the computer for the performance of the ~ariety Or data pro-
cessing operations which may be programmed into ~he computer.
26 Because of the high cost of acquiring and operating computer
27 e~uipment, it is desirable for the organizatlon uslng the com-
28 puter to have accurate co~t infor~ation regardlng the time that
29 it take3 the computer to per~orm each operat~on ~or each dlf-
3 rerent u~er in order to enable the organlza~ion to allocate and
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1 control the co~t of using the equipment most effectively.
2 For thi~ purpose, it is desirable to know the actual
3j, operating or response time the computer take~ to complete a par- ;
4, ticular transaction or process. This information ~hould be made
5,, a~ailable at the computer terminal, as part of the information
6 displayed, or it can be made available as a printout, or col-
7 lected in the computer itielf.
8 The need ~or computer process time measurement capabil-
9 ities of the type just described has been recognized in the com-
puter industry and arrangements in which operation o~ timing cir-
11 cuitry in the computer is controlled by programmed instructions
12 are known.
13 There is a need, however, for a iimple, inexpensive
14 auxiliary equipment which can be added to existing systems for
performing this function.
16 One auxiliary system is known, which may be attached
17 to a computer and which depends for iti operation on the "system ;
18 available" status sym~ol which is flashed on the viewing BCreen
19 of the terminal when a particular operation i~ completed. The
"system available" or "system inhibltn ciignals used in a display
21 terminal are usually in the nature of a ~pot and may, for
22 example, be made up of several horizontal lines Or the video
23,, raster havin~ a length equal to the width Or an alphabet char- I
24 acter and appearing at a location on the right hand side of the
~creen. In this prior art auxiliary ~ystem, a photoelectric
2 cell i~ applied to the face Or the cathode ray tube to detect
~, the light from the status symbol. When the 3ymbol 1~ detected,
1 a microprocessor, Jeparate ~rom the computer belng measured,
9i processe~i the s~gnal from the photocell. For ~uch proces~ing
3 it may be nece~ary to ¢o~pensate ~or variat~ons ~n the ~ignal
h
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trength resulting rrom the software uQed, ror scan character
2 i~tics, for changeable refresh rates, ~or 9pot brightness and
3 duration, and for other syqtem characteristic~ which influence
4!~ the brightness o~ the ~pot. This system i3 complex and its
5~l performance is easily arrected by failure to compenqate pre-
6 cisely ~or the system variables ~ust mentioned.
7, It is an ob~ect of the present invention to uAe one
8 or more ~ignal~ generated by a computer for measuring the time
9 it takes the computer to complete a particular operation.
A further ob~ect of the invention is to provide a reli-
11 able and convenient system of measurement for use at a computer
12 terminal which is also capable of s~pplying the information
13 generated to the central processor.
14 Another object of the invention is to provide a reli-
able and convenient system for measurement of the number of key
16 strokes required to complete a particular transaction.
17 Stlll another obJect of the invention is to provide a
18 reliable and convenient ~ystem for uqe at a computer terminal
~9, which is capable Or reading the dead time between transactions
at the terminal.
21 SUMMARY OF THE INVENTION
22 The present invention uses a qignal generated at the
23l¦ terminal keyboard when the nEnter" key iA depressed to initi-
241l ate counting of internally generated clock pulse~ ln a main
25!! counter. The process related signal used ror thl~.purpose is
26j, a "keyboard lock signal," directed to the keyboard from the
27 terminal visual dlsplay unit to prevent operation Or the key-
28, board from affecting the computer during completion of the work
29,l in process. Once begun, counting Or the clock pul~es continues
3l, a~ long as the nkeyboard lock ~ignal~ remains in errect. Tbe
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1 measurement process ends when the keyboard is relea9ed at the
2 end of the process and signals generated in response to elapsed
3 time information stored in the main counter are coded and
4~' supplied to the display in the same form as from the keyboard
5~, so that the response time information appears in normal decimal
6 sequence on the face of the cathode ray tube at the end of the
7 measurement cycle. Readout to the display unit begins when
8 the timing measurement ends. A second counter generates binary
g signals which control the operation of electronic switches
connected in the circuits between the keyboard and the display
11 by which signals, coded in the proper form, are supplied to
12 the display input wiring for tran91ation by the display into
13 visual timing data. An auxiliary output is provided for
14 operatin~ a separate printer and provision is made for
selection of keyboard lock signal or like information from a
16 source other than a terminal to which the timing equipment is
17 connected.
18 In the preferred embodiment described above, the timer
19 circuit Or the invention is illustrated in connection with a
computer.
21 According to another feature of the invention, trans-
22 fer of a response time measurement can be initiated in re~ponse
231 to a keyboard code signal, such as "ENTER", inQtead of an un-
24l, lock signal. Then, instead of entering response time data in
the first three character positions of the display unit buffer,
26 by delaying the strobe associated with the ENTER key the data
27 ! i9 placed in the last three character positions of the screen
28 buffer, following data keyed in by the operator.
29 Data other than response time measurements may be
3 transferred into a computer data stream by insertion through the
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apparatus disclosed. For example, the number of key strokes
per transaction may be monitored by means of a counter unit
which responds and counts the strobe pulses generated by each
key stroke, thus providing a measure of the "traffic", or
operator activity. By means of additional electronic switches,
the tally in the keystroke counter is read out of the response
time monitor, in sequence, after the response time measurement.
Then the keystroke data is stored, in sequence, in the display
unit in the same way as the response time data.
The information transmitted to the host computer
need not be limited to transaction measurements other data
may be translated or coded into the proper form for insertion
into the data stream and supplied to still more inputs of an
expanded, multiple-position electronic switch.
For terminals using handshake signals between the
display and the keyboard for controlling transmission of data
from the keyboard to the display, another embodiment of the
invention provides fcr switching of additional input data,
coded in the proper form, through the monitor switches and
into the display upon receipt of a data acknowledge signal
from the display.
In accordance with a particular embodiment of the
invention there is provided an input signal device for a
computer system having a computer and at least one computer
terminal coupled thereto, the computer system having a
signal system for output data siynals and control signals
to be transmitted from the computer to the computer terminal
and for input data signals and control signals to be transmitted
from the terminal to the computer, the computer terminal
having an input for providing at least one of information
signals and control signals, means for receiving the inlDut
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signals for at least one of use in the terminal and of trans-
mission to the computer, means adapted to be enabled for trans-
mitting input signals from the receiving means to the com-
puter, means for enabling the transmitting means to transmit
to the computer, means for disabling the input when the trans-
mitting means is enabled, and means for re-enabling the input,
the input signal device comprising: a) means for receiving
an additional information signal, and b) means coupling the
means for receiving an additional information signal to the
receiving means of the computer terminal for transferring the
additional information signal to the receiving means of the
terminal in response to at least one of a control signal from
the terminal and from the computer.
From a different aspect, and in accordance with the
invention, there is provided a method for providing data
to a computer system having a computer and at least one ter-
minal coupled thereto, the computer system having a signal
system for output data signals and control signals to be trans-
mitted from the computer to the computer terminal and for in-
put data signals and control signals to be transmitted fromthe terminal to the computer, the computer terminal having an
input for providing at least one of information signals and
control signals, means for receiving the input signals for at
least one of use in the terminal and of transmission to the
computer, means for transmitting input signals from the
receiving means to the computer, means for enabling the trans-
mitting means to transmit to the computer, means for dis-
abling the input when the transmitting means is enabled, and
means responsive to a pre-determined control signal from the
computer for re-enabling the input, the method comprises the
steps of: a) receiving an additional information signal, and
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b) transferring the additional information signal into the
receiving means of the terminal.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram showing an illustrative
embodiment of the invention,
FIG. 2 is a schematic diagram illustrating the
logic activating the main counter and electronic switch of
the response time monitor of Fig. 1,
FIG. 3 is a schematic diagram of the main counter
and the electronic switch of Fig. 2;
FIG. 4 is a block diagram of a digit scan counter
useful in the circuit of Fig. 1,
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FIG. 5 is a schematic diagram of the counter and
electronic switch~of Fig. 2 modified to respond to an ENTER
code,
FIG. 6 is a schematic diagram of a circuit for
sensing the presence of an ENTER code,
FIG. 7 is a schematic diagram similar to that of
Fig. 2, but modified to include a keystroke counter,
FIG. 8 is a block diagram of a circuit for imple-
menting the keystroke counter function shown in Fig. 7, and
FIG. 9 is like the circuit of Fig. 3, but in addi-
tion provides for transfer of additional input data in response
to a data acknowledge signal from the display.
DETAILED DESCRIPTION OF THE INVENTION
Reference is made to FIG. 1 in which a keyboard 2,
connected through response time monitor 4, supplies control
signals to the visual display unit 6. For the sake of illus-
tration, the teachings of the present invention are illus-
trated herein in connection with a response time monitor
realized in connection with a type 3277 Interactive Terminal
which is produced by the International Business Machines
Corporation and which is connected, via a type 3271 Controller
connected to line 7, to a central computer. The response time
monitor is connected between the keyboard and di~play units
of the Interactive Terminal by opening the connector in the
cable which joins ~hem and by inserting appropriate female
and male connectors, connected to the monitor, as will be
understood by those skilled in the art. In FIG. 1 this has
been done and, with response time monitor ~ in the circuit,
signals between keyboard 2 and the display 6 are transmitted
through the monitor unit by means of the illustrated connec-
tions. In operation, "system available'` and "system inhibited"
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signals are transmitted to and made visible on the screen
of display 6 indicating whether the keyboard may be used or
is disabled.
Whether or not the keyboard is disabled depends
upon a keyboard lock signal which is generated in the com-
puter system. When a keyboard lock signal is transmitted
from display unit 6 to keyboard 2, monitor 4 is activated
and, when the computer process has been completed, the time
measurement which was thus initiated is stopped. The
monitor then transmits the amount of time so measured to
display 6 in the same format as signals from
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1 the keyboard where it may be retained in storage until polled
2; by the computer. Thu~, the re~ponQe time information becomes a
3 part of the normal data flow between keyboard and main computer,
4; and each transaction entered by the operator will have the
51 response time information for the prior tran~action appended to
6 it~ The $nformation thereby automatically becomes available to
7 the main computer where it may be ~tored and or procecsed as
8 part of the normal data processing trail. Thi~ obviates any
9 requirement for manual intervention or ancillary means of data
collection. This information is available to the central com-
11 puter system via the link from the Interactive Terminal and
12 needs only to be called for by the computer.
13 The structure Or response time monitor 4 is shown in
1~ more detail in the block dia8ram of FIG. 2. There, it can be
seen that the main interconnection between keyboard 2 and
16 display unit 6 is provided by an electronic switch 8. There
17 is also provided an auxiliary output 9 for connecting signals
18 to a printer, for example, to make permanent local record Or
19 the data. The operation of electric switch 8 is controlled by
signals S1 and S2, transmitted on lines 16 and 18, respectively,
21 to choose si~nals from keyboard 2 or, when a time measurement
22 has been completed, from main counter 10. Parity circuits 14
23,j are also fed by counter 10 for generation of parity signals
241l which are tran~mitted to display 6 to provide appropriate
parity information related to the activity o~ counter 10, as
26 will be understood by those skilled in the art.
27 Control Or the counting and ~ignal generation cir-
cuitry is lnitiated by means of a keyboard lock gignal trans-
9 mitted on llne 20 ~rom keyboard 2 to the logic c~rcuitry ~hown
3 at the left of FIG. 2. The mea3urement system employ3 a master
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clock 22 which is a free-running multi-vibrator operating at
lOHz. The square wave output of clock 22 is supplied by line
24 to one input each of AND gates 26 and 28. The other input
of A~D gate 26 is supplied, via inverting driver 30, with KL
signals which are the inverted form of keyboard lock signals
KL supplied by line 20. Line 32 from AND gate 26 is connected
to main counter 10, provision is thus made for control of the
supply of clock pulses to main counter 10 by the keyboard lock
signal.
The lOHz clock signal fed to AND gate 28 is also gated
into digit scan counter 12 via connecting line 35. It thus
serves as the base for generation of switch control signals Sl
and S2. Clock pulses are also fed from the output of gate 28,
via inverting amplifier 39, NAND gate 34, inverting amplifier 36,
and flip-flop 38, to provide strobe pulses for transmission on
line 40 to electronic switch 8. The strobe pulse activates dis-
play unit 6 after selection of each digit of the timing measure-
ment to be displayed. Just prior to generation of the strobe
pulse, digit scan counter 12 generates a "master reset" pulse
which resets digit scan counter 12, and, via connecting line 42,
main counter 10, and data entry cycle flip-flop 44.
Provision is made for selection of keyboard lock
signal or like information from a source other than the
terminal to which the timing equipment is connected. Control
of the counting and signal generation circuitry is initiated
by means of a keyboard lock signal transmitted on line 20 from
keyboard 2 to the logic circuitry shown at the left of FIG. 2.
Keyboard lock signal KL is supplied, via inverting driver 30,
to "counter run" gate 26, from the pin of single-pole, double-
throw, "inhibit select" switch 46. This switch may be operated
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to choose between keyboard lock signal KL or an inhibit signalsupplied from an external source, connected to the other
terminal of the switch. Whichever signal is chosen, (in FIG.
2, the KL signal), is fed from switch 46 to manual-automatic
switch 48. By operation of switch 48, choice may be made of
whether push button 50 or keyboard lock signals KL will cause
the transfer of the timing information of the display. As
shown, switch 48 is in the internal cycle scan operate position,
and the keyboard lock signals KL are fed, via digit scan gate
52, to data entry cycle flip-flop 44.
At the end of the response time interval, keylock
signal KL goes high, clock pulses are no longer transmitted by
AND gate 26 to main counter 10, and the data entry cycle is be-
gun. During the data entry cycle, the measured response time
stored in main counter 10 is scanned out into display unit 6
and appears to the display unit to be normal keyboard signals.
"D" type flip-flop 44, which controls the data entry operation,
is set; once "set", it cannot be reset until a reset signal is
received on line 42. Activation of flip-flop 44 by keyboard
lock signal KL results in application of a signal from the Q
output of the flip-flop to one input of gate 28, via line 54,
as well as to an input of digit scan gate 52, via inverter 53.
As a result, clock pulses from clock 22 are transmitted on line
35 to digit scan counter 12, and a holding signal is applied to
gate 52 to inhibit further input transitions of data entry
cycle flip-flop 44 until the end of the scan cycle.
Reference is now made to FIG. 3 which shows detail of
a circuit for transmitting the count stored in main counter 10
either through electronic switch 8 to display unit 6~or, sep-
arately, to auxiliary output 9 for use by an external printer
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1 or the like.2' Shown in FIG. 3 are electronic switch 8, which con-
3 tains five Dual 4-Input Multiplexers 60, 62, 64, 66, and 68,
4l,l constituting the individual switches. Also shown are decade
5 ll counters 70, 72 and 74, which comprise the main counter 10.
6 Decade counters 70, 72 and 74 may be of the Di~ide-By-2 and
7 By-5 type. In addition, there are parity generators 76, 78
8 and 80. These may be g-Bit Odd/Even Parity Checker/Generators.
g Counters 70, 72 a~ 74 are connected in cascade, and clock
pulses from AND gate 26 are applied to the input of first
11 counter stage 70 ~ia line 32. The outputs of the counters are
12 in binary-coded decimal form, so that, when first counter 70,
13 the tenths counter, changes from a count of 9 to 0, a signal
14 is conveyed from the QD output of counter 70 to the input of
counter 72, causing it to advance one count. Similarly, the
~6 QD output signal from second counter stage 72 drives third
17 counter stage 74. Since the clock rate is ten pulses per
18 second, the first stage of counter 10 advances the second
~9 counter stage once per second, and the second stage advances
the third stage once every ten seconds. A timer having a maxi-
21 mum count of 99.9 seconds is thus provided. It will be under-
22 stood by those skilled in the art that the maximum time to be
23l measured will determine the counting capacity, and that longer
24 times merely require the addition of another counter stage for
25l ezch decade to be counted.
26 FIG. 3 also shows that all four output~ QA, QB, QC,
27 QD, of each counter stage 70, 72 and 74 are connected to multi-
28 plexers 64, 66, and 68 and to parity checker/generators 76, 78,
29 and 80, as well as to auxiliary output 9. In particular, it
3~ will noted tbat She QD outputs o~ counter units 74, 72, and 70,
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are connected by connecting lines 83, 85, and 87 to input
terminals lCl, lC2 and lC3 of third multiplexer 64, respectively.
Similarly, the QC outputs of each counter unit are connected
to the 2Cl, 2C2 and 2C3 inputs of multiplexer 64, and the QB
and QA outputs of main counter units 70, 72, and 74 are
respectively connected to the lCl, lC2, and lC3 and 2Cl~ 2C2,
and 2C3 inputs of multiplexer 66. Provision is thus made for
selection of individual output signals from counter units 70,
72, and 74 by the switch unit.
Before describing the remainder of the circuit of
FIG. 3, reference is made to FIG. 4 which shows detail of digit
scan counter 12. Counter 12 controls the indexing of multi-
plexers 60 through 68 by means of control signals Sl and S2
transmitted on connecting lines 16 and 18, respectively. As
shown in Fig. 4, these signals are generated at the Q outputs
of flip-flops 82 and 84 which form the first two stages of a
three stage counter circuit. The three flip-flop stages, 82, 84
and 86 of digit scan counter 12 may be Dual J-K Master-Slave
flip-flops with Preset and Clear. The input to first digital
scan flip-flop 82 is provided on line 35 from AND gate 28, as
was discussed previously, and is controlled by data entry cycle
flip-flop 44. Clearing of all three counters, 82, 84, and 86
is accomplished by connection to line 54. The output of flip-
flop 82, taken from the Q terminal, is supplied as switch
control signal Sl to connecting line 16. The inverse of this
output, Q, is connected to the clock input of second flip-flop
84. The Q output of flip-flop 84, connected to line 18, sup-
plies switch control signal S2. Output signal Q of flip-flop
84 is connected to the clock input of flip-flop 86, whose Q
output terminal supplies the reset signal transmitted by con-
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necting line 42 to decade counters 70, 72, and 74 of maincounter 10 and to one input of AND gate 27, for control of the
transmission of clock pulses from clock 22 to the reset terminal
of data entry flip-flop 44. The Q output of flip-flop 86 is
connected to AND gate 34 for generation of the strobe pulse.
Referring back to FIG. 3, it will be seen that the
input terminals lCl, lC2, and lC3 of multiplexers 60 and 62
are all connected to a fixed supply voltage through a dropping
resistor. A positive signal is thus transferred to any one of
the multiplexer output terminals Bit 0, Bit 1, Bit 2 and Bit 3
when the internal switching logic of the associated multiplexer
connects any of the input terminals to its output terminal
1~ or 2Y.
The fifth multiplexer 68 in electronic switch 8
chooses the parity and strobe signal outputs to be fed to
display 6. Thus, parity signals, generated in parity checker/
generators 76, 78, and 80, are transmitted on lines 90, 92,
and 94 and to terminals lCl, lC2, and lC3, respectively, of
multiplexer 68. Similarly, strobe pulses generated on line 40
20 of monitor 4 are connected to terminals 2Cl, 2C2, and 2C3 of
multiplexer 68.
Connections from keyboard 2 are made by means of con-
necting lines 100 through 118, all of which are supplied via
dropping resistors from the 5-volt system supply and are con-
nected to the multiplexers as follows. Keyboard lines 100 and
102 are connected to input terminals lC0 and 2eo of multiplexer
60. Keyboard lines 104 and 106 are connected to input terminals
lC0 and 2C0 on multiplexer 62. Keyboard lines 108 and 110 are
connected to input terminals lC0 and 2C0 on mulitplexer 64.
30 Keyboard lines 112 and 114 are connected to input terminals
lC0 and 2C0 on multiplexer 66, and keyboard lines 116 and 118
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are connected to input lines lC0 and 2C0 on multiplexer 68.
The purpose of the assembly of five multiplexer
switches in electronic switch 8 is to determine whether 8-bit
character coded signals from keyboard 2 or from counter 10 will
be transmitted to display 6. In normal operation, signals flow
directly through the switches between keyboard 2 and display
unit 6. When a time measurement cycle provided for by the
monitoring arrangement of the invention is completed, these
same switches serve to transmit simulated keyboard signals
constituting the measurement data in 8 bit character coded
signals from the response time monitor circuitry to display 6
for automatic display. At the same time, parity and strobe
signals originating in the response time monitor are substituted
for those normally transmitted from keyboard 2 on keyboard lines
116 and 118. The IBM equipment on which the response time
monitor was fitted utilized EBCDIC (Extended Binary-Coded
Decimal Interchange Code) character coded signals. In this
code, only the last four digits are required for transmitting
the numeric information from the response time monitor. There-
fore, provision is made by means of three of the inputs tomultiplexer 60 and 62 to substitute positive voltage signals
for the Bit 0, Bit 1, Bit 2, and Bit 3 signals of the first
four digits being fed in on keyboard lines 100, 102, 104 and
106, respectively. As was seen above, the Bit 4, Bit 5, and
Bit 6, and Bit 7 inputs to multiplexers 64, 66, and 68 are
supplied by the main counter unit.
Switch unit 8 provides the electronic equivalent of
ten 2-pole, 4-position switches, all of which are simultaneously
switched by switch signals Sl and S2 connected to the SA and SB
terminals, respectively, of each multiplexer. Therefore, the
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input from keyboard 2, supplied via keyboard leads 100, 102,
104, 106; 108, 110, 112, 114, and 116, 118, to the lC0 and 2C0
input terminals of the associated multiplexer~, will be connected
to display output lines Bit 0, Bit 1, Bit 2, Bit 3, Bit 4, Bit
5, and Bit 6, Bit 7, respectively, when no signals Sl or S2 are
transmitted to the multiplexers on control lines 16 and 18.
When activated by signals Sl and S2, the multiplexer switches
transmit the simulated keyboard signals to the display unit.
Table 1, below, illustrates the correspondence
between the logical state of control signals Sl and S2 and the
choice of input signal switched to the output Yl and Y2 of the
electric switches. When both control signals Sl and S2 are at
logical 0, the signals from the keyboard are fed directly to
display unit.
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1 TABLE I
SWITCHING OBTAINED WITHi DIFFERENT
2 CONTROL SIGNAL COMBINATIONS
3'l Logical State Or Control Signal Input Signal Switched to Output
4,l Output Output
5il S2 S1 lY 2Y
6i O O 1C0 2CO
7 O 1 1C1 2C1
8 1 0 1C2 2C2
9 1 ~ 1C3 2C3
The relation between the states of the scan cycle
ll counter flip-flops and the connections established in the
12; multiplexers for sequential supply Or time measurement related
13 signals from the main counter to the display for production of
14 decimal digits in the usual significance $s shown in Table 2,
below.
16 TABLE 2
SCAN CYCLE SEQUENOE
17
18 States of Cycle Switch
Scan Fllp-flops Control Signals Description
Count 82 84 86 S2 S1
2l Cycle Re~et Reset Reset O O Di~play
22 1 Reset Reset Set O 1Tens Diglt Fed to Display
23ll2 Reset Set Reset 1 0 Display
24 3 Reset Set Set 1 1Tenths Di~it Fed to
25'1 4 Set heset Reset 0 0Xeyboard Connected to
~; Terminated, Reset Reset Re~et O O
27~ Countlng
28; S~opped
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l The switching circuit provided by multiplexer 68
21 supplies the parity bit (even parity), and strobe signals
3, required to complete the transfer of EBCDIC, character coded
4j1 data to the display unit.
The keyboard si~nals, such as keyboard lock, shift
6 control, and alarm signals, are routed to the display unit,
7 along with power supply and ground circuit connections, via
~ wiring in the interconnecting cables (not shown), as will
9 be understood by those skilled in the art.
Operation of the circuit described above is as
ll follows. Clock pulses from AND gate 26 are fed to first counter
12 stage 70 in main counter 10. When tenths counter 70 chanses
13 from a count of 9 to 0, the transition of the high order bit
14 signal, QD,~s coupled to the input of counter sta~e 72, causing
it to advance one count. S~milarly, the QD signal from second
16 stage 72 drives third counter stage 74. The outputs of these
17 counters are fed to the input terminals of multiplexers 64 and
18 66 for selection to form the lower order bits of the 8-bit
19 ~BCDIC code. As was discussed above, the hiBh order bits Or
the EBCDIC code are supplied by multiplexers 60 and 62.
21 When a count has been completed, the four lower b~ts
22 of accumulated value in three stage main counter 10 are
2311 sequentially switched, as shown in Table 2, under control Or
24j, sequential slgnals S1 and S2 from di~it scan counter 12. Their
2511 outputs are switched to the C1, C2, and C3 multiplexer input
26 connect~ons~
27 Parity scanner/generators 76, 78 and 80
28, generate requ~red parlty bits for the ~CD outputs of maln
29 counter sta~e~ 70, 72 and 74 respectl~ely. These are fed to
3, t~e tC ~nputs of electronic multiplexer s~ltch 68, whlch pro-
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vides sequential selection of the parity signal associated
with each digit selected during the data entry cycle.
At the end of the response time interval, the key-
board lock signal returns to high level. This causes AND gate
26 to inhibit the clock pulses which were driving main counter
10, and marks the beginning of the data entry cycle. During
the data entry cycle, the response time measurement stored in
main counter 10 is scanned into display 6 instead of the normal
keyboard signal. To this end data entry cycle flip-flop 44 is
set by the positive level transition at its clock input. Flip-
flop 44, once set, cannot be reset until a low level signal is
applied at its reset input. Flip-flop 44 is normally in the
reset state, with its Q output at low level and its Q output at
high level. The feedback signal from the Q output is inverted
by inverting amplifier 53 and fed to one input of A~D gate 52.
The other input of AND gate 52 is connected to the keyboard lock
signal via non-inverting driver 49. When both inputs to AND
gate 52 are high, the high output produced is fed to the clock
input of data entry cycle flip-flop 44, switching it to the set
condition and causing its Q output to go high. The inverted
feedback signal from the Q output then inhibits further input
transitions, keeping flip-flop 44 in this condition until it
is reset at the end of the scan cycle.
Sequential scanning of the three response time digits
is controlled by digit scan counter 12. Initially, the Q out-
puts of scan flip-flops 82, 84 and 86 are at a logic ~ or low
voltage level. When data entry cycle flip-flop 44 is in the
set position, AND gate 28 is enabled and passes counting pulses
to the input of the first counter, flip-flop 82. The counting
pulses appear during positive going cycles of clock 22 when a
- 17--
~145~35C~
.,
, .
l true condltion occurs at the input of AND gate 28. The first
2 three count~ advance the firRt two stages of the counter and
3 produce ~witching control signal~ S1 and S2 which are trans-
4 ferred by lines ~6 and 18, respectively, and control the opera-
tion of multiplexer switches 60, 62, 64, 66 and 68. This results
6 in ~equential selection of the BCD signal outputs in main
7 counter 10 for transmi~sion to the display.
8 When the keyboard is in operation, the strobe pulse
g from the keyboard gates the keyboard data signals lnto the dis-
play immediately after each new character code is produced by
ll depressing a key. In order to prevent premature data entry by
12 the operator after occurrence of the "systems ready" signal on
13 the display, generation of the ~trobe signal is delayed by
14 one-half clock cycle. This is accomplished as follows. The
positive pulses from AND gate 28 occur during the positive
16 half Or the clock cycle. The signal fed to strobe generator
17 38 is inverted by inverter 39 and so provides positive-going
18 pulses during the second half Or the clock cycle which are
19 coupled through NAND gate 34. With both its inputs high, NAND
gate 34 has a low output. The ~ signal from third stage flip-
21 flop 86 of digit ~can counter 12, which is fed to the other
22 input of NAND gate 34, i8 normally high during the first three
231l cycles of Qcan counter 12. ~hus, one input Or NAND gate 34 is
24 enabled. Due to the inver3~0n Or pulses supplied from inverter
39, the output of NAND gate 34 goes low during the second half
26 of the clock cycle and remains so until the Q output of third
27, gtage flip-rlop 86 changes to low.
28i The net re~ult of the gating circuitry ~ust described
29 iQ to provide a pul~e which occurs in the ~econd half of clock
3 cycle~ occurrlng durlng the first three couGts of digit scan
:
; _18-
~1458SO
counter 12. This interval is called the strobe interval. The
logic level of the strobe interval pulse is inverted by inverter
36 and supplied to one-shot multivibrator 38, which is designed
to produce a negative-going pulse of 5 milliseconds duration
at the leading edge of the strobe interval. This strobe pulse
is fed to the 2C inputs of electronic multiplexer 68 to provide
the required strobe pulse for display 6, after selection of each
digit. Immediately after the fourth pulse fed to the digit scan
counter 12, the positive transition of output Q of third counter
86 causes the master reset to occur before the strobe pulse.
This master reset pulse is supplied by line 42 to all main
counter and digit scan counter stages as well as to data entry
cycle flip-flop 44, resetting them. The path of the reset signal
through AND gate 27 and inverter stage 29 provides noise
immunity and level inversion for signals to be supplied to the
"clear" input of data entry cycle flip-flop 44.
It will be noted that, in addition to connections to
the BCD outputs of main counter stages 70, 72, and 74, the
auxiliary output is also provided with a strobe pulse connection
to facilitate operation of an attached printer, for example.
In an alternative embodiment of the invention, a
single parity generator is connected across the output signals
from electronic switches 60, 62, 64, 66, and 68. In this way
a keyboard fail indicator can be added as a parity generator,
which will also generate a parity bit for signals fed to the
display unit from the keyboard. The parity bit generated in
this way is compared with the parity signal from the keyboard
to checX the integrity of data flowing through the monitor
from the keyboard to the display.
The process described above can be used with equal
-- 19 --
~45850
facility to measure the interval between operations and to
provide a direct measurement, for example, of time chargeable
to overhead. Inversion of the keyboard lock signal supplied
to switch 46 will result in initiation of a timing measurement
by the restoration of keyboard control to the operator. Thus
when the keyboard signal from keyboard 2 goes low, releasing
the keyboard to the operator, inverter 120 supplies a positive
keylock signal, permitting clock pulses to flow from clock 22
to counter 10. Similarly, when the keyboard signal goes high
at the time the "Enter" command is given at keyboard 2, the
counting operation is stopped and the data entry cycle begun.
The necessary change in circuitry to produce this result is
shown in Fig. 2 by the dashed lines.
When the system is measuring response times related
to operation of the local keyboard, as described above, readout
occurs when the digit scan counter is triggered by transition
of the keyboard lock signal going from locked (low) to unlocked
(high). When this occurs, the three digit response time value
is stored in the buffer of the display unit in the first three
digit positions. Data entered via the keyboard subsequently is
- 20 -
~ ,
1~5~350
placed in the buffer after the first three digit positions.
When the operator presses the ENTER key, causing generation of
an ENTER code at the completion of data entry, the data, inclu-
ding the response time information, is locked into the displav.
Then the keyboard lock signal operates to lock the keyboard,
initiating another response time measurement operation, while
the computer is acquiring the data, including previous response
time measurement data, during a computer polling or read cycle.
Response time data thus read into the computer can be subse-
quently stripped out of the data stream as part of the trans-
action or process performed by the computer.
It is sometimes desirable to delay reading out of
the response time data from the monitor until data entry has
been completed by the operator and the ENTER key is depressed.
The function for doing this is controlled by setting manual-
automatic switch 47 (FIG. 7) to the position marked "From FIG.
6" (line 144) in Fig. 6. Switch 47 corresponds to manual-
automatic switch 48 of FIG. 2. The circuitry of Figs. 5 and 6
provides means for doing this. Fig. 5 is essentially the same
circuit as was shown and described in connection with Fig. 3,
but differs in that passage of the strobe signal from the key-
board directly to the 2C0 terminal of parity and strobe signal
multiplexer 68, as shown in Fig. 3, is interrupted, with the
connecting wiring being brought out, at the bottom of FIG. 5,
as strobe lines 118 and 140. It will also be seen, at the top
of Fig. 5, that connections to keyboard input lines 100 to
114, the respective transmission paths for bits numbered 0 to
7, are also brought out and directed to Fig. 6.
As was pointed out in the description of FIG. 3, the
strobe signal transmitted on line 118 from the keyboard is part
- 21 -
.,
~458SO
of the ten-signal data set required for entry of characters
from the keyboard into the display unit. When data from the
response time monitor is being fed into the display unit, the
response time monitor generates a strobe signal of its own
which is connected to the display unit by multiplexing switch
68, at the same time that the switch connects the monitor unit
to the display unit for transmitting response time data. In
the IBM equipment, with which the response time monitor circuit
illustrated here is adapted for use, the strobe pulse generated
by the keyboard is a negative going pulse and the digit code
and parity signal which are generated when a key is depressed
on the keyboard are stored there until the next key strobe
occurs, at which time transfer to the display unit occurs.
The circuit of FIG. 6 provides the necessary means
for delaying transmission of the strobe pulse for each key
stroke unt~l the key code can be examined. If, when examined
by this circuit, the code is found not to be an ENTER code, the
strobe pulse is immediately propagated to the display unit,
allowing normal data entry to occur. However, when an ENTER
code is detected by the circuit of Fig. 6, the digit scan cycle
is initiated and the response time monitor generates a strobe
pulse which is transmitted to the display unit when the elec-
tronic switches restore the keyboard signal path. Since the
ENTER code was stored in the keyboard, it is then transferred
to the display unit, following data entered by the operator.
This process is brought about in the circuit of Fig.
6 by reading the information on input lines 100 to 114 in NAND
gate 142. Input lines 100, 102, and 114 contain inverting
amplifiers so that the presence of the IBM ENTER code, 0111101,
30 will produce a response in NAND gate 142. When NAND gate 142
- 22 -
,~ ~145~350
,. .
l is activated by tbe presence o~ an ENTER code, NAND gate 142
2 goes negative and transmits, due to inversion ln amplifer 143,
3, a high signal on line 144 to selector switch 47 ln Flg. 7.
4'ji This signal activates readout by the di~it scan counter.
5l Generation Or the keyboard strobe for the display unit, the
6: original keyboard strobe being delayed, is initiated in the
? circuit o~ FIG. 6 by the ENTER code detected signal transmitted
8 on line 144 which is also transmitted to terminal A of one-shot
9 multivibrator 146. The 8 input to one-shot multivibrator 146
is supplied from one-shot multivibrator 148, which, in turn,
l~ is triggered by the keyboard strobe signal supplied by line
12 118 to input terminal A. Thus, when multivibrator 146 is
13 enabled by the presence Or an ENTER code, an input signal from
14 multivibrator 148 will cause a negative going pulse to be
generated and returned on keyboard strobe line 140 to display
16 unit 6.
17 While the above circuit has been illustrated in con-
18 ~unction with an IBM enter code, lt will be understood by those
l9 skilled in the art that other computer systems may use other
codes in keeping with the protocol in use, and that, whatever
21 the code, the NAND gate used for detection and its inputs, can
22j readily be adapted to respond. Thus, a TAB code used to move
23 a cursor to another field, or a PF or other special function
241 code incorporated for initiating storage could be used.
25l Reference is now made to FIG. 7 whieh shows a diagram
26 of an alternative embodiment of the invention in partial sche-
27 matic and partial block ~orm. By means of this circuit, which
28l is a modification of the circuit o~ FIG. 2, a response time
29j monitor, in addition to performing the described measurements
3.. of the t~me for completion Or a transaction at the keyboard of
. -23-
;'
~5~50
a terminal or the time between transactions, may be equippedto generate data which is a function of terminal traffic as
measured by the number of key strokes employed in each trans-
action. By means of this circuit, information as to the number
of key strokes is coded and made available in the display
unit, along with response time data, for reading into the data
stream of the computer. In addition to the change to the
manual-automatic switch described above, FIG. 7 differs from
FIG. 2 in that it shows a key stroke counter 150, which
receives key strobe pulses on line 118 from keyboard 2. As
was explained earlier, such a strobe pulse is generated each
time that a key is pressed at the terminal. Key stroke
counter 150 is set to zero by a reset pulse from digit scan
counter 12 received from line 42, as were the other counters
described above. Key stroke totals are supplied from key
stroke counter 150 to parity circuits 14 for generation of
parity signals, and to electronic switch 8 which determines
when they will be transmitted to display unit 6. As will be
seen below, additional switch signals, generated by digit scan
counter 12, are transmitted, on lines 154 and 156, to electronic
switch 8 and control the added switching function necessary for
sequencing the extra digits generated in key stroke counter 150
into the display unit.
FIG. 8 is the circuit of FIG. 4, modified to include
the key stroke counting and switching function. For the sake
of simplicity, detail of the wiring which interconnects
counters 70, 72, 74 of response time counter 10 and parity
generators 76, 78 and 80 of response time parity generator 59
with duplexers (dual 4-input multiplexers) 60, 62~ 64, 66 and 68,
all of which has been described in connection with FIG. 4, has
has been omitted from the drawings~ Instead, ihe necessary
connections from individual
- 24 -
.~ I'
1~5~3SO
., .
Ii ,
l,; response time counters 70, 72 and 74 to the response time
2, parity generators and to multiplexing switche~ 64 and 66 are
3~ indicated by a single connecting line 158. Similarly, a
4, single line 160 interconnects response time parlty generator
5ili and multiplexin~ switch 68. As described above in connection
6 with FIG. ~, multiplexing switches 60-68 are controlled by
7 signals S1 and S2 transmitted from JK flip-flops 82 and ô4 of
8 scan counter 72 (FIG. 4) on lines 16 and 18. In FIG. 8, this
9 connection is shown as line 162. Monitor strobe line 40,
which supplies the pulses needed to cause registration of data
ll read out from the monitor in the storage buffer of display
12 unit 6, is extended from its input connection to multiplexer
13 68 to provide a similar input to multiplexer 172.
14 Key stroke counter 150 of FIG. 8 is of the same con-
struction as the response time counter shown in and described
16 in connection with FIG. 3. ~owever, instead of counting timing
17 pulses generated by the clock generator of FIG. 2, counter 150
18, counts the keyboard strobe pulses ori~inating in keyboard 2 and
19 received on line 118. There individual counter stages, con-
nected in cascade, provide a maximum count of 999. This
21 counter capacity is sufficient for many applications. As will
22, be apparent to those skilled in the art, additional counter
23jj stages may be added for each additional decade required, should
24j the need arise. The QA, QB, QCt and QD outputs of each counter
25!j stage are all connected, in the same way as provided for the
26 response time counter, to the 1Cl, 1C2, 1C3 and 2C1, 2C2, and
27, 2C3 inputs of additional switching multiplexers 168 and 170.
281 ~his interconnection is indicated by ~eans of connecting line
29 190.
/J/~///////
,, -25-
1'1
114~8SO
!
l Keystroke counter parlty ~ignals are generated in
2, parity signal generator 161 by means of indi~idual generators
3, which are connected to individual key ~trokes in the same way
41l as were the individual parity counters of the respon~e time
5,i counter in FIG. 3. ~he outputs of the keystroke parity gen- !
6. eratorq are connected via connecting lines, generally ~hown as
7 192, to appropriate 1C1, 1C2 and 1C3 inputs of additional
8 switching multi-plexer 172.
9 Other connectionQ to the added multiplexers of elec-
tronic switch 8 are as follows:
ll Monitor strobe pul~es arriving on strobe line 40, in
12 addition to being connected to inputs 2C1, 2C2 and 2C3 on multi-
13 plexer 68, are connected to inputs 2C1, 2C2 and 2C3 on multi-
14 plexer 172. The other inputs to multiplexers 60, 62, 64, 66,
and 68, are as they were shown in Fig. 3, and serve the same
16 purpose.
~7 Additional connections made to added switching multi-
18 plexer~ 164, 166, 168, 170 and 172 include connections from
l9 the 1Y outputs of each of the multiplexers 60 to 68 to the 1CO
inputs of each of the multiplexers 164 to 172. Similarly, the
21 2Y outputs of multiplexers 60 to 68 are connected to the 2CO
22 inputs of multiplexers 164 to 172.
23ll Switching instructions for multiplexers 164 to 172
24, are generated by JK flip-flops 1g4 and 196, which have been
25, added to scan counter 12. Switchlng signals S3 and S4 are
2~ transmitted on lines 154 and 156 to the SA and SB input
27j terminal~ Or ~witching multiplexers 164 to 172. Last JK
28, flip-flop 198 in scan counter 12 now generates the re~et
29~ sign~l for line 42, in the same way as ~a~ descri~ed above,
3 except that now key stroke counter 150 is also provided with a
. . .
i -26- !
'!
5~35
.
li; reget ~ignal.
2 Operation of the reqponse time monitor with read-out
3, of the added key stroke counting circuit is ~imilar to that
4l described above in connection with the reading out of Qignals
5!1 from main counter 10. Response time counter 10 functions in
6 the same way that it did previously, responding to count pulses
7 transmitted to it, for example, when the keyboard lock signal
8 goes negative. Similarly, counting in counter 10 stops when
9 the keyboard lock signal returns to a high condition. When the
keyboard lock signal goe~ high, scan counter 12 is activated as
11 before, provided that switches 46 and 48 are in the position
12 shown.
~3 Meanwhile, keyboard strobe pulses supplied to key
14 stroke counter 150 on connectin~ line 118 from keyboard 2 are
accumulating in the counters of that unit. Since every action
16 taken by the operator requires a key stroke, everything that
17 the operator does generates a stroke signal for counting in key
18 stroke counter 150. When the keyboard is locked, operat~on of
19 the keys is prevented; no more signalc can be generated by the
operator and the previously generated count of the stroke
21 signals remains stored in the keyboard stroke counter until
22 the keyboard lock signal goes high. Scan counter 12 then causes
23i~ the switching duplexers to read out the accumulated sig..aLs in
24jl successlon from response time counter 10 and key ~troke cûunter
25l! 150. Under command of the S1 and S2 signals first generated by
26 the flip-flops of scan counter 12, the data in response time
27 counter 10 ls rirst scanned out and transrerred to the output
28jj terminal~ of multiplexer~ 64 and 66. As berore, duplexers 60
29, and 62 transm~t rixed voltages tû complete the EBCDIC numerical
3; code of the IBM system used here to $11u~trate the lnvention.
i! -27_
!l I
1145850
Similarly, but under control of switching signals S3
and S4, the contents of key stroke counter 150 are sequentially
read out by multiplexers 168 and 170, immediately following the
numbers from response time counter 10. When multiplexers 164
to 172 are not activated, the data transmitted to the lC0 and
2C0 inputs from the lY and 2Y outputs of duplexers 60 to 68 is
transmitted through to the associated transmission line leading
to display unit 6. As is the case with switching multiplexers
60 and 62, switching multiplexers 164 and 166 also transmit
fixed voltage signals completing the makeup of the high order
components of the IBM EBCDIC signal.
Parity and strobe signals are transmitted in a similar
manner: key stroke count parity signals are supplied on line
192 to one portion of multiplexer 172 and stroke signals, gen-
erated by the monitor, are transmitted from line 40 to like
sections of both multiplexers 68 and 172. As before, keyboard
parity signals arriving on line 116 and keyboard strobe
signals arriving on line 118 are fed to the lC0 and 2C0 inputs
of multiplexer 68, being passed straight through to multiplexer
20 172 when the multiplexer 68 is not activated.
The principles of the method and/or apparatus taught
by the invention have obvious utility beyond the gathering of
"time and motion" data to which they have been applied in this
specification. Thus, data other than response time or key
stroke counts can be inserted, by connection to an encoder
which translates it into numerical form and makes it avail-
able for connection into the buffer by a switch at an appropri-
ate time. Also, the number of inputs coded need not be limited
to the two shown in FIG. 8, but can be expanded to a much larger
number.
- 28 -
., ., l!
~ ~ ~11458SO
Stlll ~urth,or ~lexlblllty ln sy~t~m operatlon csn be
2 reallzed by utlllzlng the prlnclple~ o~ tho lnventlon set rorth
- 3 bo~e. For oxample, ln ~omo olroumatanoe~, genera~1on Or
on~t,orlng d,ata ln exc-~ Or th- cap-clty Or tho d1~play burror
,
5 ~,,l,ght oau,~o ~,rap-around" whereby return or the burfer polnter
to t~e b~ginn~ng o~ the ~oroen burrer oan result ln an attempt
to,,~;-nt~r data ln a re~trlotod rlold, oau~1nR the soroen to lock,
8~ or ln ovorlay and de~truotlon Or pre~lously entorod dsta By
9 ~ ~n~ o~ a g-te olrcult llke that connected to the key~troke
0~¢ount~r or FIC 6, a pr-d-t-rmlned threshold count ln the key-
atr,oke ¢ounte,r can er~ect dolay o~ generatlon Or the keyboard
.~ .
t,rob~ ~16nal an,d pr-~ent ntry o~ data untll the next cyole
, ' In the preo,edlng deaorlptlon the ln~entlon wa~ de-
14 Jorlb-d a~ lt oan b- ~plled to a type 3277 Interactlve
T,er~1nal,, ~anur-otur-d by th- Internatlonal Bu~lne~ Maohlno~
~1C Corporatlon In that ter~lnal, lnrormatlon l~ enood~d by the
,~ 17,'koyboard 1,nto~a EBCDIC ood~ rOr tran~ml~lon to the dlsplay
~ rn'th~ sy~te~ e~ployod ln that termlnal, the eleotrle slgnals
,~ ~9
r~pr-sentlng-the ooded data are present at the output rrom the
kq bo-rd untll anoth-r key 19 depressed When ~uch a ~y~tem
21
W ~,d, tran~or o~ coded data lnto th~ dl~play l~ lnlt~ated
~by ~ Jtrobe pu1~- generatod ~lmultaneou~ly wlth the coded data; , " ,;~ b,y,~ac,h keyJtrok ; thl~ l~ the proc-~, de~cr'lbed~ln conneotlon
with FIG~ 8 abo~. ;- -
lth oth-r ~y~t _J, ~uch a~ may be uaed ln termlnals
re the d~play pollJ the keyboard or where a ~lcroproce~or
28~ u~ng~an lnterrupt structure l~ employed, a "hand~hake~ pro-
c~ ur- 1~, o~d~S~o brlng about the dat~ tran~er ~n su¢h ca~e-
~
'' th!e ~,trob- ~lgnal generated by the keyboard do~ not dlrectly
b~rlng about the tran~r o~ data Instead, lt elther arms
-29-
.,
.
::-
-: 11458SO
1 a clrcul~ ln th- dl~play ~hlch re~pond~ to a polllng oporatlon
or 1t gonerate~ an lnterrupt wlthln tho dlJplay olrcultry Tho
3 s~;tr,ob- go~n~ratod by tho koyboard Jlgn~ o~otlme~ known a~ a
dst,a r- ~ n-g~, an "~ntorrupt r-qùe~tn; or a "data a~llable
~ 5~ ~lg,na1~ ~ In th, Çollowlng, tho tor~`~d-ta avallable ~trobe~
,~- , ' 6~ ll;bo u~,~ed.~,~tt-r~reoolpt, thon, o~ a data ava~lable ~trobo
, 7 ,ln~th~e d-i~play, actual tran~or Or data to tbo di~play take~
8 pl,a~ wh~n th- d'l~play ~-nd~ a hand~hak-~ ~lgnal, herelnarter
~` 9 oal,l~d a~n~data acknowledten ~trobo, to the keyboard whlch
, r-~r,u~at~ tranJ~r~or th- data
In th~ ~b,odl~-nt Or FIG. 9, the clrcult Or FIG 3
,' l~,~o;dl,r~d tor u~o ln a t~r lnal whlch utlllzo~ a data acknow-
3 ~l-d~ ~otr,obj- bot,wo-n th- dl-play and korboard to lnltlate the
,d~t~ tr-n,~t-r ,The ~trobo al8nal, ~enoratod whon a key ln key-
~ 5 b"o ~ 2 1~ dopro~ d,~l~ rorwardod ~ro~ tho koyboard on vla
,, ; ~' l6 ~ 118-~nd,~w,~,toh 68, aJ be~oro, but lt l~ ~ent to the key-
,; ~b,o,~ d aJ a~data ,~v-llablo ~trobo In FIC 9, provlslon 19 made
, ~ ~l8,~ or-~tr~blq~ th~dat-~rro~ pro~lou~ly do~crlbed eleotronlc
9 J~tcb-~ 6~o to 68 or tbo onltor unlt lnto the dl~play when a
; ~ 20 da- ackno~ledgo ~trobo 1~ rocol~od ~ro~ the dl~play; l e , the
,, 2l r-a,dln,g out Or Jlgnal~ rrom tho ~wltcheJ 1J enabled by tho data
",," , 22- ;a,oknowlodg- Jlgnal
Th- ~data oknowl-dg-" ~lgnal, the "hand~hako" from
t`h- dl~play iJ rcturn,ed to tho monltor unlt ln FIC 9 by mean~
or ¢onne,cti~g llno 152 to which ~wltch control t~rolnalJ St
and S2 o~ all ~wltohen 60, 62, 64, 66 and 6~ are connected ln
parallol (Tho~e tor~lnal~ wero grounded in the clrcult Or FIG
3 nd~, th,~r-ror-, dld not contiol ~wltch actlonj Now, when
'' ,lino 15~ goo~ hlgh, ~wltche~ 60, 62, 64, 66, and 68 aro ln-
~h~l,t-d an~ data rrOo oountor~ 70, 62 and 74 wlll not be read
-30-
.
- . ,
1145850
. .
`:
l out to t~h,o dl~play ~hen tho data aoknowlodgo ~lgnal oau~oo
- 2 llno 152 to go low, howevor, tho S1 nd S2 tormlnal~ are, ln
3 o~root, 6roun~od, and roadout ot data ~rom eountor~ 70, 72, and
~- 74 undor oontrol Or th- wlteh eontrol,olgnals appllod to
ter~inalo S~ and SB Or tho o~ltehoo l~ enablod and ooeurs ln the
6 ~oamo way~aJ dl~ouoo-d, ln the deoerlptlon ot FIC 3 abo~o
; ~, 7 ~ Ther- hao beon llluotr-tod ln tho foregolng a ~y~tem
8 whleh $~ wid-ly~adaptable to a ~arlety Or eomputer~ and whleh,
'9 boe-u~- lt 1~ lnt$mately a~ooelatod ln lt~ eoneept and runetion
~O,~ ~lt,h tho oporatly mode o- a ¢o puter termlnal, l~ well
-,ll l,n~ ~ ated rrom r-~loion~ o~ eo~putor protoeol ~ueh a~ ~roquent-
- ,~l,~ ly oeeur ln largo y~temJ Slne- anythlng that l~ dono by way
,~, 13' ot ohanglng op-rat?ng mod-'~nq protoeol of a'compu~er u~t tako
14 l~,to'aee,oNnt ,th- oharaetorl~tleJ Or tho termlnal, revl~ion~ ln
th,~ eo~pu~or op~ratl~g o~atem, whlch wlth oth~r typeo Or '
'- 1"6 '~o~ltorlng~yoto o would noe-~oltato ro~lolon'o~ the modo o~
17 o p r-tlo-n o~ the ~onltor, do not arreet the pre~ent ln~entlon
, ,18,, St wlll bo apparont to tho~e ~kllled ln tho art that
; ,l~ thé, aouremont Or oomputer operatlon, procoss or tran~a¢tlon
~-~, 9~ tl~o, -o~deocrlbod abovo, lnelude~ any tlme delayo lntroduced
, ~, . . . .
,by'tho eentral proe-~lng unlt, a,ny aoso¢iated teleproce~ln~
~ 2,2 oontroll r attaebed-to the eomputer, moderno or othor ol~nal
: ~n~ e,o~dltlonln~ devleeJ ln tho eom~unieatlon llnk, thc communlca-
; 2~ ;tioa~,-lln,k lt~,-lr, an,d any elrcuitry, dovloe, controller, or
-, ~, -2,5" d~o~trlbutod pr~ceooor ln lln- wlth the communlcatlon~ path to
and rrom the t,or~inal
.
~' It wlll aloo bo apparent that the prlnclples o~ thc
28 lnventlon, a~ llluotrated ln the present e~bodl~ent ln con-
~29, nec,tlon wlth a partlcular Intoraotlve Tormlnal ln a computor,
3 oan b- utlllzod wlth a varlety Or lnput and output unltJ, elther
-31-
. ~
~5t350
with the computer described above or with other computers,
by utilizing process related, or other signals passing
between the computer and the terminal to activate the cir-
cuitry and to translate measurement or other signals into
coded data in a format which is compatible with that already
in use for communicating between an existing terminal key-
board or other input and display. Therefore, the below
appended claims should be construed in keeping with the
spirit of the invention, rather than limited to the illus-
trative embodiments &escribed above.
- 32 -
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