Note : Les descriptions sont présentées dans la langue officielle dans laquelle elles ont été soumises.
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FIXED GATING SEQUENCE APPARATUS
AND METHOD FOR AN INVERTER
The present invention relates generally to
control apparatus and methods for generating with an
inverter a~ outoing signal of variable magnitude and
frequency and, more particularly, to an appaxatus and
method which in one aspect causes the inverter to be
cycled to and stopped at a preselected gating sequence `!
when an idle condition occurs, and which in another
aspect causes the gating pulse signals effectively not
to be provided to the inverter from when the idle
condition occurs until a designated one of the gating
pulse signals is furnished.
Methods and apparatus are well known for
generating an outgoing signal of variable magnitude and
frequency in accordance with control signals. One
such well-known approach is the use of an inverier
that converts an incoming DC signal to an outgoing
signal of variable magnitude and frequency in accordance
with control signals. In one of the more common three-
phase versions of the inverter, variable direct current
(DC) power is applied to a six conduction controlled
rectifying device bridge having a pair of series
conduciion controlled rectifying devices, such as
thyristors, associated with each leg of the three-
phase outgoing signal. Control signals, such as gating
pulse signals, are effectively supplied to the gating
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terminals, or gates, of the conduction controlled
rectifying devices in the inverter. The gating pulse
signals cause respective ones of the conduciion con-
trolled rectifying devices to which they are effectively
supplied to go to the conduction state, causing the
outgoing signal of desired magnitude and frequency to
be genera~ed.
It is oflen desirable to cause the inverter
to generate an outgoing signal in accordance with
certain of Ihe conduction controlled rectifying devices
being in the conduction or gaied state when, for
example, the frequency of the outgoing signal is below
a preselecied level in~ica~ive of a low load operation.
In Ihe case of an inverter used to generate an out-
going signal provided to drive an AC electric motor, itoften is important to be able to provide the out-
going signal to particular stator windings when the
frequency of ihe outgoing signal is below a preselected
value, for example, substantially zero Hertz, so that
the orientation and magnitude of the flux produced
by the DC outgoing signal is known.
Conventional inverters and their associated
conirol circuitries, however, do not assure that certain
thyristors are in the conduction state when the frequency
of the outgoing signal is below the preselected value
(indicative of low load operation) because the inverter
is randomly stopped at any position of thyristors in
the conduction or gated state. When the preselected
frequency value is substantially zero Hertz indicative
of an idle state, it becomes unlikely for the system
ever to reach the desired gated thyristor pattern in
he inverter if thisj desired gated state of thyristors
. is stopped at ~ because the outgo1ng signal is
substantially DC and, therefore, no further gating of
the inverter thyristors takes place.
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It is also desirable to cause the inverter not
to receive gating signals when the frequency of
the outgoing signal goes below the preselected value
(indicative of low operation loacl) until a designated
one or group of the gating signals is furnished by the
inverter control circuitry. By blanking the gating
signals, the inverter i~ prevented from cycling through
its conduction or gated states, and consequently providing
an outgoing signal at relatively high frequency, when
the conduction state o the thyristors of the inverter
is shifted from the conduction state at which the invertex
was randomly stopped until the designated one of the
gating signals is furnished by the control circuitry
of the inverter. Conventional inverters do not
provide this capability of blanking the gating pulse
signals from when the inverter is forced into the
idle state until the designated pattern of gating
signals is furnished by the control circuitry associated
therewith.
It is an object of the present invention to
provide an apparatus and method for causing an inverter,
when sequencing into an idle condition, to provide an
outgoing signal of variable magnitude and frequency in
accordance with a desired fixed gating sequence of the
conduction controlled rectifying devices in the inverter~
It is another object of the present invention
to cause the shift register of the control circuit of
the inverter to cycle to and stop at a desired fixed
gating position, irrespective of the gating sequence
being provided by the shift register when the inverter
first entered the idle condition.
It is another object of the present invention
to provide an apparatus and method for not furnishing
the gating signals provided by the shift register of the
control circuit to the inverter from when the inverter
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goes lo the idle state until the desired ~ixed gating
pattern is provided by the shift register.
It is a further object of the present inven-
tion to provide an apparatus and method for the control
circuit e~fective to cause the inverter to cycle
direcily io the desired co~duction state a~ter the
idle condition oCcurs wlthout the inverter providing
an output signal of substantial ma~nitude and/or
frequency.
These and other objects have been achieved
by the apparatus and method of the present invention.
A ~ixed gating sequence apparatus and
method is disclosed for a control circuit of an inverter,
which inverter generates an outgoing signal of variable
magnitude and frequency in accordance with gating
signals from the control circuit provided to the con-
duction controlled rectifying devices of the inverter.
In one aspect, the present invention causes
the inverter to generate the outgoing signal in
accordance with a desired fixed gating sequence of the
conduction controlled rectifying devices of the inverter,
irrespective of the gating sequence provided by the
shift register of the control circuit when an idle
state occurs.
Gating signals to the inverter are provided
by the shift register of the control circuit in response
to a clocking signal. The clocking signal is provided,
for example, by a voltage controlled oscillator, at a
rate set in accordance with a frequency control signal
when an idle conlrol signal (indicative of an idle
control statel is absent. When the idle control signal
is present, the clocking signal is provided at a
cycling rate set in accordance with voltage signals o~
predetermined magnitude until the shift register
provides the desired fixed gating sequence to the
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inverter, whereupon the clocking signal is no longer
provided to ihe shlft register causing it to stop at
the stage which furnishes the desired fixed gating
pattern. The shift register remains unchanged until
the idle condition is no longer present, whereupon
the shift register is again provided a clocking signal
at a rate set in accordance with the frequency control
signal.
In another aspect of the present invention,
the gating signals from the shift register effectively
are not provided to the inverter from when the idle
condition occurs until the desired fixed gating
sequence is provided by the shift register. In one
embodiment, gating means, such as electronic switches,
are connected between the lines from each of the stages
of the shift register (except the stage which provides
the desired fixed gating sequence) and the respective
gate drives. The gating means are normally in the
closed state, but are adapted to be switched to the
open s~ate in response to an inhibiting signal provided
from when the idle condition occurs until the desired
fixed gating sequence is provided by the shift register.
The gating means thus act to blank the gating sequences
provided by the shift register from when idle condition
occurs uniil the desired fixed gating sequence is
provided.
The present invention in both of its aspects
has particular application in an AC elecrric motor drive
system having an AC electric motor producing a rotation
in response to an outgoing signal of variable magnitude
and frequency.
Figure l is a schematic diagram o~ a basic
inverter circuit as known in the art and such as is
preferably usecl in the present invention.
Figure 2 is a schematic diagram sho~ing the
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fundaments of a control system for the inverter o~
Figure 1 and showing an embodiment of the present
invention associaced therewith within dashed-line box
100 .
Figure 3 depicts tables listing typical
gating sequence signal patterns as might be used in
the syscem of the present invencion.
Figure 4 is a schematic diagram showing the
fundaments of a control system for the inverter of
Figure 1 and showing an embodiment of the present inven-
ion associated therewith within dashed-line box 401.
Figure 5 is a block ~iagram of an AC electric
motor drive system employing a desired level of
roiation in which the present invention is utilized.
Figure 6 is a block diagram of an AC electric
motor drive system employing a desired level of torque
in which the present invention is utilized.
Referring now to Figure 1, an inverter system
as is known in the prior art and such as is generally
20 applicable to the present invention is shown in basic
schematic form. The inverter system utilizes a plurality
of conduction controlled rectifying devices, for
example, thyratrons, mercury arc rectifiers such as
ignitrons and excitrons, and thyristors. Thyristors
are now the most commonly used conduction controlled
rectifying`device and will be used as a generic term
herein. In ~igure 1, only the basic conducting elements
have been shown in relationship to the total system,
and such things as snubbing circuits, commutating
circuits, etc. have been omitted because these do not
play any part in the understanding of the present
invention.
The sys~em of Figure 1 includes a three-
phase semiconductor bridge 10 which is comprised of
three positive thyristors Pl, P2 and P3 and three
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negative thyristors Nl, N2 and N3. Bridge 10 is con-
nected to a source of variable DC power by way of a pair
of buses 12 and 14. The source can supply variable DC
voltage and/or current in accordance with the nature
of the actual operational status of bridge 10. As well
as being grouped as positive and negative thyristors,
grouping of the thyristors of the inverter system may
also be made according to phase. Line 16 is connected
at the junction of the series connected thyristors Pl
and Nl as a first phase input to a load 22, such as an
AC electric motor while thyristors P2 and N2 are con-
nected by way of phase line 18 to the load. In a
similar manner, the third leg of the bridge, comprising
series connected thyristors P3 and N3, is connected
by way of phase line 20 to the load.
In the illustrative embodiment of the inverter
system of Figure 1, ihe thyrisiors are rendered
conductive by the appropriate application thereto of
gating pulse signals on leads 23 connected to the gate
electrodes of each of the thyristors. The actual
gating pulse signals are developed by an inverter
control 24, the nature of which will be determined in
accordance with the type and overall desired function
of the inverter.
Referring now to Figure 2, one well-known
version of the inverter control 24 used in inverter
systems like that depicted in Figure 1 is shown in
fundamental form by the circuitry outside dashed-line
box 100; the circuitry within dashed-line box 100 makes
up one aspect of the present invention and is discussed
below in detail.
A shift register 102, shown in a generic form
in Fig. 2, includes, for example, six stages, designated
respectively stages 112, 11-1, 116, 118, 120 and 122.
Shift register 102 may be of~any suitable type well
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known in the art, but normally would be comprised of
series connected flip-flops such that a digital quantity
(typically a binary one) stored in one of the flip-
flops, for example, stage 1~2 is -~ransferred to and
stored in siage 114 and thence in stage 116, etc. with
each occurrence of a clocking signal or pulse provided
to a clock input 136 and a shift right signal furnished
to a shift right input 140. (It is noted that right
and lefi herein is referenced with respect to Figure 2.)
Conversely, a digital quantity, such as a binary one,
stored in, for example, stage 122 is trans~erred to and
stored in stage 120 and thence in stage 118, etc. with
each occurrence of a clocking signal or pulse provided
to clock input 136 and a shift left signal furnished to
a shift left input 144.
Lines 124, 126, 128, 130, 132 and 134, labeled
"gating pulse signals", sense the individual binary
states of the respective stages 112, 114, 116, 118, 120
and 122 and serve to initiate the respective gating
pulse signals for application to respective thyristors
of the inverter bridge circuit (Figure 1). In the
typical system, the gating pulse signals via lines 124
through 134 would not be directly applied to the gates
of the respective thyristors of the bridge, but would
serve to operate gate drivers (not shown~ which serve to
apply the actual gating pulse signals. This, however,
is well known in the art, and further explanation is
believed unnecessary.
Since the exact nature of shift register 102
is not important to the present invention, the details
of originating the register contents have not been shown.
If, for example, the regisier were of the well-known
prior art type employing recirculation, binary ones
would be placed in two mutually adjacent stages and
recirculated through the register by way of a return
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path (not shown) at a rate governed by a clock input on
line 136 and in a direction in accordance with the
presence or absence of direction steering signals on
lines 140 and 144 (respectively, "shift right input" and
"shift left input"). In this case the relationship
between the register stages and the generation of firing
signals for the thyristors of bridge 10 (Fig. 1) is a
one-to-one basis as shown by Table 1 of Fig. 3.
Preferably, however, the present invention
employs a bidirectional open-ended shift register which
in response to specified bit patterns within the register
automatically loads the register at specified times (first
prior to original bridge operation and subsequently
during operation) with a single binary on~ which is, as
before, shifted at a rate governed by the clock input
on line 136 ana in a direction determined by the signals
on lines 140 and 144. This sytem shifts out and
eliminates undesirable or spurious gating signal
designations from the shift register and is the subject
matter of U.S. Patent No. 4,258,416 dated March 24, 1981
entitled "Inverter Power Conversion System Having
Improved Control Sch'eme", to Loren H. Walker and John H.
Cutler and assigned to the assignee of the present
invention. The relationship between regis~er content
and the gating of the bridge thyristors in this case is
illustrated by Table 2 of Fig. 3.
In one aspect, the present invention provides
an apparatus and method for effectively causing the
generation of the outgoing signal to be in accordance
with a predetermined gating signal effectively applied
to respective thyristors of the inverter when an idle
condition occurs, irrespective of the gating sequence
at which shift register 102 is rand'omly stopped at when
the idle condition first'occurs.
The idle condition is indicative of low load
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operation. It can take several forms, including the
condition where the frequency of the outgoing signal is
below a preselected frequency va:Lue, for example, less
than or equal to 3 Hertz. Typically, the preselected
freq~ency value is approximately zero Hertz. As is
shown with respect to the use of the present invention
with the AC electric motor drive systems of Figures 5
and 6, discussed below, the idle condition can occur
when specific system parameters are less than respective
preselected values. Specifically, with regard to the
AC eleciric motor drive system of Figure 5 employing a
desired level of rotation, the idle condition is present
when Ihe torque command signal and at least two of the
rotation reference signal, the actual rotation signal,
and the rotation difference signal are less than
respective preselected values. With respect to the AC
electric motor drive system of Figure 6 employing a
desired level of torque, the idle condition exists when
the torque reference signal and the actual rotation
signal are less than respective predetermined values.
When the idle condition occurs in accordance with any
of these parameter schemes, an idle signal is generated.
This system of developing the idle signal forms the
subject matter of Canadian Patent Application Serial
~25 No.3~ r~, "Zero Rotation and Zero Torque Detector
and Method for an AC Electric Mo~or Drive" by Loren
H. Walker and John H. Cutler, filed ~ ~; ~ PD
and assigned to the assignee of the present invention.
The circuitry within dashed-line box 100 of
Figure 2 is one embodiment of the apparaius and method
of the present invention in accordance with the first
aspect. For purposes of illustration, a desired fixed
gating sequence is assumed to be the gating sequence
supplied by stage 116 on line 12~. ~ first logic
stage, which includes an AND gate 152 of conventional
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design, provides a first control signal at an output
154 when the idle signal supplied to a line 150 con-
nected to a first input 156 is true (a binary one) and
the predetermined gating signal supplied by stage 116
via line 128 to a second input 157 is also a binary
one. Absent either of these two conditions, the output
on line 154 is in the false or binary zero state. Thus,
gale 152 provides a ~ nal in the false, or binary
zero, slate on line except when the idle control
signal on line 150 is in the true ~binary one)
state and the predetermined gating signal is provided by
stage 116. ~S~
Output line ~ is connected to a first input
(inveriing) 160 of a second logic stage, designated
generally by reference numeral 162. Second logic
stage, for example, can be an AND gate. A second input
164 of the gate 162 is connected to a source of the
clocking signal. The source of the clocking signal can
be of any suitable type; for example, ~he clocking
signal can be a serial stream of clocking pulses of
controllable rate. One suitable form for the source
of the clocking signal is a voltage controlled
oscillator 166 of conventional design, which provides
the clocking signal to the second input 164 at a rate
controlled in accordance with the voltage magnitude of
a control signal supplied on a line 198 which, in turn
has a value determined by the position of a switch 192
as will be explained.
Line 150 is also connected to a noninverting
3Q input 184 of an AND ~ate 182. An inVertin~ input 186
of gate 182 is connected to line 1280 AND gate 182
provides a signal on an output line 188 in the true
(binary one) state when the idle control signal is true
and the predetermined gating signal is not provided
by stage 116 via line 128.
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Output line 188 is connected to a concrol
inpuc 190 of an electronic switch 192 of conventional
design. The output of switch 192 has one of two
values as determined by its position under the control
5 ai input 190. A voltage signal having a predetermined
magnitude (corresponding to a clocking rate de~ired
during entry into the idle condition) is supplied by
line 194. For example, the voltage signal (line 194)
can have a predetermined magnitude so that the voltage
10 controlled oscillator 166 is caused to provide a
clocking signal of a predetermined rate; e.g., cor-
responding to 12 Hertz. Switch 192 provides the voltage
signal of predetermined magnitude on an output line 198
when the signal on line 188 is in the true state.
The output signal on an output 168 of the
gate 162 is provided to the clock input 136 of shlft
register 102. The clocking signal from voltage
controll~d oscillator 166 at a rate set in accordance
with the frequency control signal is normally supplied
20 by second logic stage 162 to clock input 136 when the
idle control signal is absent and at a different
cycling rate in aceordanee with the voltage signal of
predetermined magnitude on line 19~ ~rom when the
idle control signal is first provided until the
25 desired ~ixed gating signal is supplied on line 128
by shift register 102 (during which cycling time period
the frequency control signal may be forced to zero,
as discussed with regard to Figures 5 and 6).
The operation of the embodiment of the
30 present invention shown in Figure 2 is now explained.
Assume operation of shift register 102 with no idl~
control signal is present on line 150. The output
from gate 152, provided to input 160, is in the false
state allowing the cloeking signal from voltage con-
35 trolled oscillator 166 set in aeeordance with the
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frequency control signal to be supplied via output 168
to clock input 136 of shift register 102. When
the idle signal is initially provided on line 150, the
frequency control signal is typically of a value causing
voltage controlled oscillator 166 to provide a clocking
signal of substantially zero frequency, and this signal
is still being provided to clock input 136. Thus,
shift register 102 is momentarily prevented from cycling
and provides a random gating sequence that has a
high probability of not being the desired fixed gating
position. However, the voltage signal of predetermined
magnitude (line 194) is immediately thereafter provided
to voltage controlled oscillator 166 causing it to provide
clocking signals at a moderate shift frequency; e.g.,
corresponding to 12 Hertz, to clock input 136. This
clocking signal on clock input 136 causes shift register
102 to shift through the gating sequences until the
desired fixed gating position is provided on line 128,
whereupon the present invention no longer allows the
shift register 102 to shift because th~ output of gate
152 changes to the true state and gate 162 prevents
pulses on line 164 from reaching the clock input 136.
The shift register 102 remains at the desired fixed
gating position until the idle control signal is no
longer provided to line 150, whereupon shift register
102 provides the gating sequences at a rate controlled
in accordance with the frequency control signal (line
130). It should be noted that the predetermined
frequency set by the voltage signal on line 194 is
low enough so that a motor load connected to the
inverter (Figure 1) does not produce appreciable torque
as shift register 102 is cycled to and stopped at the
desired fixed gating sequence.
In another aspect, the apparatus and method
of the present invention inhibits the furnishing of
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the gating sequence signals from shif-t register 102 to
inverter 10 (Figure 1) from when the idle control
signal condition is provided until the desired fixed
gating se~uence signals are supplied by the shift
register 102.
Turning now to Figure 4, an embodiment of the
second aspect of the present invention is shown.
Like numbers refer to corresponding components in
Figures 2 and 4, and only the new components of Figure
4 are discussed.
A switching current comprising an individual
gate or switch is provided for the respective lines
124, 126, 130, 132 and 134 of stages 112, 114, 118, 120
and 122 of shift re~ister 102. Specifically, a gate or
an elec.ronic switch 400 has an input connected to line
124 and an output 402. Switch 400 is normally in the
closed state, and is adapted to be switched to the open
state when a high state, or inhibiting, signal on a line
445 is furnished ~o a switching input 404.
A gate, or electronic switch, 406 has an input
connected to line 126 and an output 408. Switch 406
is normally in the closed state, but is adapted to be
switched to the open state when the high state, or
inhibiting7 signal is furnished on line 445 to a
switching input 410.
As was stated above, for purposes of illustration,
stage 116 is designated as the stage providing the
predetermined gating signal, which produces the
desired fixed gating sequence of inverter 10 when
inverter 10 is caused to be in the idle state. Thus,
in accordance with the second aspect of the present
invention, no switch or gate is interposed on line 128
between stage 116 and the gate driver (not shown).
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A gate, or electronic switch, ~12 has an input
connected to line 130 and ar. output 414. Switch 412
is normally in the closed state, but is adapted to
be switched to the open state when a high state, or
inhibiting, signal is furnished on line ~45 to a
switching input 416.
A gate, or eIectronic switch, 418 has an input
connected to line 132 and an output 420. Switch 418
is normally in the closed state, but is adapted to be
switched to the open state when a high state, or
inhibiting, signal is furnished on line 445 to a
switching input 422.
Finally, a gate, or electronic switch, 424
has an input connected to line 134 and an output 426.
Switch-~24 is normally in the closed state, but is
adapted to be switched to the open state when a high
stage, or inhibiting, signal is furnished on line 445
to a switching input 428.
Electronic switches 400, 406, 412, 418 and 424
can be any suitable type, such as a logic gate, bipolar
transistor or field effect transistor switches or
electromechanical relays.
The inhibiting or blanking signal supplied
via line 445 to switching inputs 404~ 410, 416, 422 and
428 is provided to prevent inverter 10 ~rom being
furnished gating signals from the time when the idle
control signal is first furnished on line lS0 until
shift register 102 has been cycled to and stopped at
the desired fixed gating sequence, causing inverter 10
to generate the outgoing signal in accordance with the
desired fixed gating sequence.
The blanking signal is generated by a first
logic stage and a second logic stage. The first logic
stage generates a first control s:ignal in the high state
when either the idle control signal is present on line
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150 or when the desired fixed gating sequence signal is
furnished on line 128 by shift register 102. Specifi-
cally, the first logic stage, designated generally by
reference numeral 430, may include, for example, an
EXCLUSIVE OR circuit 432. The EXCLUSIVE OR circuit
432 has a first input connected to line 128, which
provides the predetermined gating signal. A second input
of EXCLUSIVE OR stage 432 is connected to a line 434,
on which the idle control signal from line 150 is
supplied. An output 436 of EXCLUSIVE OR stage 432 is in
the high state when either, but not both, of the inputs
are in the high state. Thus, output 436 is not in the
high siate when the idle control signal and the pre-
determined gating signal are both in the low state or
are boih in the high state.
A second logic stage, designated generally
by reference numeral 438, provides a high signal on its
output 440 when the signals on its first input 442 and
Ihe signal on its second input 444 are both in the high
stage. One suitable form for the logic stage 438 is an
AND gate. Output 436 of EX~LUSIVE OR 432 is connected
io input 442. The idle signal line 434 is connected to
the second input 444. Thus, output line 440 of the
second logic stage 438 is in the high state from when
the idle control signal is furnished on line 434 until
the predetermined gating signal from stage 116 is
furnished. It is seen ihat the second aspect of the
present invention prevents inverter 10 from being cycled
through its various gating states when the first aspect
of the present invention causes it to cycle through to
Ihe desired fi~ed gating sequence after the idle con-
dition occurs.
Turning to Figure 5, a schematic block diagram
of a preferred embodiment is shown of the fixed gating
sequence apparatus and method of the present inveniion
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utilized in an AC electric motor drive system employing
a desired level of rotation. The apparatus of the
presen~ invention of the embodiments o~ Figures 2 or ~
is principally within dashed-line box 401; the circuitry
outside box 401 is a conventional AC electric motor
arive system employin~ a desired level of rotation
command.
The apparatus and method of the present
invention can be utilized in other types of electric
drive systems. The system shown in Figure 5 is only for
purposes of illustration/ and is similar to the system
disclosed and claimed in Canadian Patent Application
Serial No. 331,769, entitled "Controlled Current
Inverter and Motor Control System," to P.M. Espelage et
al, filed July 13, 1979, assigned to the assignee of
the present invention. Another suitable electric
drive motor system is shown in A.s. Plunkett, D'Atre,
J.D., Lipo, T.A., "Synchronous Control of a Static AC
Induction Motor Drive," IEEE-/IAS Annual Meeting-Con-
ference Record, 1977, pp. 609-15.
.
Referring to Figure 5, a variable frequency
inverter 514 (corresponding to inverter 10 of Figure 1)
provides an outgoing signal, such as a drive current,
of variable magnitude and frequency via a line 516 to
a load, such as AC motor 518. AC motor 518 can be of
any suiiable type, but preferably is an AC induction
motor.
Inverter 514 can be of any suitable type for
converting a DC input signal to a drive current of
variable frequency under control of a variable frequency
gating signal, also referred to as a frequency control
signal, on an input line 520. One preferable form for
inverter 514 is an autosequentially commutated
con~rolled current inverter having a 6-thyristor bridge,
such as invert~r 10 of Figure 1, which generates the
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drive current of variable magnitude and frequency in
accordance with the gating of the thyristors.
The DC input current to inverter 514 can be
provided by any suitable variable DC current source.
One preferred embodiment for the variable DC current
source is a converter 522, which supplies variable
magnitude DC current via a DC link 524 to the input of
inverter 514. Converter 522 eonverts AC power supplied
through terminals 528 under control o~ phase eontrolled
gating signals on lines 526 to a DC eurrent of variable
magnitude. The phase controlled gating signals are also
referred to herein as the current control signal.
Converter 522 can be of any suitable type but, most
typically, would be a`6-thyristor phase con~rolled
converter whose thyristors are provided with gating
pulses by the current control signal on line 526.
The DC current of variable magnitude (IDc)
is provided to inverter 514 via DC link 524. DC link
524 can take any suitable form, but preferably includes
an inductor 530 connected in series between eonverter
522 and inverter 514. Inductor 530 acts as a filter.
Thus, the magnitude of the drive current
supplied by inverter 514 to line 516 is eontrolled by
the eurrent control signal supplied to eonverter 522,
and the frequency o~ the drive current is varied in
accordance with the frequency eontrol signal furnished
on line 520 to inverter 514.
The electric motor drive syst m shown in
Figure 5 is a closed loop system having the following
feedback paths. The aetual rotation produeed by motor
518 is sensed and used to generate an actual rotation
signal on a line 534 proportional to the meehanieal
rotation. One suitabIe form -or generating
the aetual rotation signal is a DC tachometer 532.
Furthermore, other approaches for generating the actual
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21-DSH-2520
-- 19 --
rotation signal are contemplated by this invention.
A desired level o~ rotation is used to
establish a rotation reference signal proportional
thereto. The desired level of rotation can be furnished
5 from either a system or user command; and most typically
is in the form of a rotation user command from an
operator settable rheostat 538 having a wiper arm 540
connected to a user or operator rotation control lever
(not shown).
The rotation reference signal from wiper arm
540 is provided to a first input of a summing junction
542. The actual rotation signal is negatively ~ed
back and provided to a second input of summing junction
542. The output of summing junction 542 is a rotation
15 difference signal, which is representative of any
difference between the rotation reference signal and the
actual rotation signal and is provided to the input of
a rotation regulator 544. Rotation regulator 544 can
be of any suitable type to generate on a line 546 a
20 torque command signal as a function of the rotation
difference signal. One suitable form for rotation
regulator 544 is an operational amplifier configured to
operate as a gain amplifier having, for example, a
transfer function of k 1 + st, where s is a LaPlace
25 operator, t is a time constant, and k is a gain
constant.
Line 546 is connected to the input 665 of an
electronic switch 664. Electronic switch 664 is adopted
to connect its output 666 effectively to electrical
30 ground in response to a switching signal or idle control
signal applied to a switching input 667 so as to cause
the torque command signal effectively to assume a
substaniially æero value. Electronic switch 664 can be
of any suitable type, such as a bipolar transistor or
35 field effect transistor switch or an electromechanical
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21-DSH-2520
- 20 -
relay.
The tor~ue command signal is applied via
switch 664 to the input of an ab~olute value staye 656
of conventional design. The absolute value version of
5 the torque command signal at the output of the absolute
value stage 656 is applied to the input of an electronic
switch 658. Electronic switch 658 normally connects its
input to a first output 65~, but is adapted to connect
its first output`659 to a second input 660 in response
to a switch signal or idle control signal applied to a
switching input 661. Electronie switch 658 can be of
any suitable type, such as a bipolar transistor or
field effect transistor switch or an electromechanical
relay. When the first output 659 of electronic switch
658 is caused to be connected to the second input 660,
the level of the tor~ue command at the first output 659
is caused to be forced to a leveI corresponding to a
predetermined current level, whereby the magnitude of
the drive current is forced to a predetermined level.
The first output 659 is applied to the first
input of a summer 662 of conventional design. A shunt
668 is eonnected to sense the magnitude of the DC eurrent
(IDC) through the induetor 530 connected to inverter
514. Shunt 668 provides on a line 669 a signal indicative
of this magnitude level. The signal on line 669 is
negatively fed back and provided to a second input of
summer 662. The`output of summer 662 provides to an
input 548 of a current control stage 550 a signal
representative of the difference between the absolute
30- value version of the torque eommand signal and the
signal indicative of the magnitude of the DC current
( DC)-
Current control stage 550 can be of any suitabletype for generating the eurrent control signal on line
526 in accordance with the signal at input 548. One
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21-DSH-2520
21 -
suitable ~orm for current control stage 550 is that of
a ramp and pedestal gating control of conventional
design.
The torque command signal on line 547 is also
applied to the first input of a summer 670 of con-
ventional design. The actual rotation signal is
positively fed back and provided to a second input of
summer 670. The output of summer 670, which is a signal
proportional to the sum of the torque command signal and
the actual rotation sig~al, is provided to input 552
of frequency control stage 554. Frequency control
stage 554 can be of any suitable type for generating the
frequency control signal as a function of the signal
proportional to the sum of the torque command signal
and the actual rotation signal. The frequency control
signal is provided to line 180 of the preselected
gating circuit 401 of the present invention. Circuit
401 is the circuitry depicted, as appropriate, in
Figure 2 or Figure 4.
The conventional drive system shown in Figure
5 allows the mechanical rotation and torque generated
by AC induction motor 518 to be controlled in accordance
with the desired level of rotation.
An idle control signal is furnished in the
electric motor drive system o~ Figure 5 when the system
is in the conventional substantially zero rotation and
substantially zero torque mode where the frequency of
the drive current is substantially zero. An apparatus
and method for furnishing the idle control signal is
claimed in Cànadian Patent AppIication Serial No.
350,526 entitled "Zero Rotation and Zero Torque
Detector and Method for an AC Electric Motor Drive," to
Loren H. Walker and ~ohn H.- Cutler, filed April 24, 1980
and assigned to the assignee of the present invention.
.~
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21-DSH-2520
- 22 -
In the case of a drive system utilizing a
desired level of rotation, the idle control signal is
furnished when the torque reference signal and at
least two of the rotation reference signal, the actual
rotation signal, and the rotation difference signal are
less than respective predetermined values. Alternately,
in ihe case of a drive system utilizing a desired level
of torque as shown in Figure 6, iche idle control signal
is furnished when the actual rotation signal and the
torque reference signal are less than respective
predetermined values.
Referring again to Figure 5, a preferred
embodiment of the apparatus o~ the present invencion is
shown for a drive svstem employing a desired level of
rotation. An absolute magnitude circuit 600 has an input
conne ~ d via line 602 to the torque command signal on
~~~ line . Absolute magnitude circuit 600 can be of
any suitable type for providing on an output line 604
an absolute magnitude version of the torque command
signal.
The absolute magnitude version of the torque
command signal is provided to a first input of a
voltage comparator 606, whose second inp.ut is connected
to a source o~ reference voltage 608. ~he level of
the reference voltage corresponds to the respective
predetermined value below which the absolute magnitude
version of the torque command signal must have in order
for the system to be in the substantially zero rotation
and subslanicially zero torque mode. Reference voltage
source 608 can be of any suitable type for generating
a reference voltage.at the predetermined va~ue.
Voltage comparator 606 can be o~ any sui.table
form for furnishing a first output signal on line 610
when the` absolute magnitude version o~ the torque
command signal is less than the level of reference
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21-DSH-2520
- 23 -
voltage source 608. One suitable form for voltage
comparator 606 is that of an operational ampli:Eier
connection in the voltage compar:ison mode.
The input of a second absolute magnitude
circuit 612 is connected via a line 614 io the actual
rotation signal on line 534 for providing an absolute
magnitude version of the actual rotation signal on an
ouiput line 616. Absolute magnil-ude stage 612 can
take any suitable form. The abs~lute magnitude version
of the actual rotation signal on line 616 is provided
to a first input of a voltage coMparator 618. The
second input of comparator 618 is connected to refexence
voltage source 608, and provides at an output 620 a
second output signal when the magnitude of the absolute
magnitude version of the actual rotation signal is less
than the level of reference voltage source 608.
The input of a third absolute magnitude
circuit 622 is connected via an input line 624 to the
rotation re~erence signal at wiper arm 540. Absolute
magnitude circuit 622 provides at an output line 626
an absolute magnitude version of the rotation re~erence
signal. The absolute magnitude version of the rotation
reference signal on output line 626 is supplied to a
first input of a voltage comparator 628, whose second
input is connected to reference voltage source 608.
Comparator ~28 provides on an output line 630 a third
outpui signal when the absolute magnitude version of the
rotation reference signal is less than the level of the
reference voltage signal.
The input of a fourth absolute magnitude
circuit 680 is connected via a line 682 to the rotation
difference signal at the output of summer 542 for
providing an absolute magnitude version o~ the rotation
difference signal on an output line 684. Absolute
magnitude stage 680 can take any suitable form. The
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21-DSH-2520
- 24 -
absolute magnitude version of the rotation difference
signal on line 684 iS provided to a first input of a
vol~age comparator 686. The second input of comparator
686 is connected to reference vo]tage source 608, and
provides at an output 690 a fourth output signal when
the magnitude of the absolute maqnitude version of the
rotation difference signal is less than the level of
reference voltage source 608.
It should be understoocl that voltage com-
parators 606, 618, 628 and 686 each could be connected
to a different referenee signal souree providing
referenee signals of different levels. The use of
differeni referenee sources is one way to provide for
different predetermined levels below which the torque
eommand signal and at least two of the rotation referenee
signal, the aetual rotation signal, and the rotation
difference signal must be in order for the idle eontrol
signal to be furnished.
As ~ wn, the output signals from voltage
20 eomparators ~, 618, 628 and 684 on lines 610, 620,
630 and 690, respectively, are applied to a logic cireuit
640, which furnishes the idle eontrol signal only when
the first control signal and two of the second to fourth
eontrol signals are present. It should be understood
that the present invention ean also be eonfigured to
provide the idle eontrol signal when eaeh of the first
to fourth eontrol signals are present. Normally, only
two of the seeond to fourth eontrol signals are used,
however, beeause the information in the unused eontrol
signal is present in the two control signals that are
used. Logic cireuit 640 ean be of any suitable type,
sueh as an AND gate~. rrhe output from logie eireuit 640
on line 642 iS the idle eontrol signal, and indieates
that the drive system is in the substantially zero
rotation and substantially zero torque mode of
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21-DSH-2520
- 25 -
operalion .
A delay of predetermined time amount can be
introduced before furnishing of the idle control signal
to prevent the idle control signal from being generated
transiently when the drive system momentarily passes
through the conventional substant;ially zero rotation
and substantially zero torque mode. This delay of a
predetermined time amount can be produced by applying
the idle control signal on line 642 to a delay stage
644 which can be of any suitable design, e.g., a one shot
and a gate. Delay stage 644 has a delay on rise and no
delay on fall, for example, 0.1 second on rise.
The idle control signal on output line 650 o~
delay stage 644 causes three functions as represented
15 by block 648. slock 648 represents the three functions
produced by the signal on line 650. In structure,
block 648 may be nothing more than three lines to
conduct the signal on line 650 to the three switches
as shown.
The first function represented by block 648
is to provide a switching signal, i.e., the idle control
signal on line 673 to block 401 to cause the shift
register 102 to be cycled to and stopped at stage 116
to provide the desired fixed gating sequence signal on
25 line 128.
The second function represented by block~648
is to provide a switching signal, i.e., the idle control
signal, on a line 676 to electronic switch 658 effec-
tively to cause the magnitude of the drive current to
be rapidly changed to a predetermined magnitude level
determined by the predetermined current level. The idle
control signal on line 676 for rapidly changing the
magnilude of the current can cause current control
stage 550 arbitrarily to change the current to a
preselected magnitude level in accordance with the
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21-DSH-2520
- 26 -
predetermined current level.
The third function represenced by block 648
provides a switching signal, i.e., an idle control
signal, on a line 677 to electronic switch 664, causing
switch 664 to close so as to reduce rapidly the torque
command signal to substantially zero. As is seen in
Figure 5, this reduction to substantially zero is due
io electronic switch 664 grounding line ~ The
reduction of the torque command signal to zero when the
drive system is in the substantially zero rotation and
substantially zero torque high slip mode prevents sudden
iransients in drive system performance from occurring
when the drive system exits this mode.
Referring to Figure 6, a preferred embodiment
is shown of the fixed gating apparatus and method fox an
inverter of the present invention for use in an AC elec-
tric motor drive system employing a desired level of
torque command. The conventional AC electric motor
drive system employing a desired level of torque command
shown in Figure 6 is outside of dashed-line box 401,
and is similar to the drive system disclosed in the
Espelage et al Canadian patent application, Serial No.
331,769 discussed above. Like numbers in Figures 5
and 6 correspond to identical components; only different
components are discussed herein.
A torque reference signal proportional to a
desired level of torque is provided on a line 700. This
torque referende signal can be provided by the drive
sysiem, or can be furnished by an operator settable
rheostat 702 having a wiper arm 704. The position of
wiper arm 704 corresponds to the desired level of
iorque indicated by the position of a user torque lever
(noi shown~.
The torque`reference signal is provided as an
input of a torque regulator 706, which generates the
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21-DSH-2520
- 27 -
torque commancl signal on line 546 as a function of the
torque reference signal. Torque regulator 706 can be
of any suitable type to generate the torque command
signal in accordance with the torque reference signal.
One suitable form for torque regulator 706 is an opera-
tional amplifier of conventional design configured to
operate as an amplifier exhibiting a suitable gain.
The remaining components of the conventional drive
system shown in Figure 6 correspond to the like
numbered components of the drive system shown in
Figure 5.
In the drive system employing a desired level
of torque, the idle control signal is furnished when
the actual rotation signal and the torque reference
signal are less than respective predetermined values.
The respective predetermined values can be different
for the torque command signal and the actual rotation
signal, but ihe values indi~ate when the drive system
is in the conventional substantially zero rotation
and substantially zero torque mode when the frequency
of the drive curreni is of a very low value so as to
produce the constant slip mode of operation.
Referring again to Figure 6, the actual
rotation signal is applied via line 722 to an absolute
magnitude circuit 720. Absolute magnitude circuit 720
can be any suitable type for providing on an output
line 724 an absolute magnitude version of the actual
rotation signal.
The absolute magnitude version of the actual
rotation signal is applied to the ~irst input of a voltage
comparator 726. A second input of voltage comparator
7~6 is connected to a re~erence voltage source 728,
which provides a reference signal at a value equal to
the respective predeiermined value. V~ltage comparator
726 provides a second output signal when the absolute
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21-DSH-2520
- 28 -
magnitude version of the actual rotation signal is less
than the predetermined value. Voltage comparator 726
can be of any suitable type, for example, an operational
amplifier connected in the voltage comparison mode.
An input line 730 of an absolute magnitude
circuit 732 is connected to the torque reference signal
on line 700. Absolute magnitude circuit 732 provides
an absolute magnitude version of the torque command
signal on a line 734 connected to the first input of a
comparaior 736. The second input of voltage comparator
736 is connected to reference voltage source 728.
Voltage comparator 736 generates a first output signal
when the value of the absolute magnitude version of the
torque command signal is less than the reference voltage
signal equal to the respective predetermined value
furnished by reference voltage source 723. Voltage
comparator 736 can be of any suitable type, for example,
an operational amplifier connected in the voltage
comparison mode.
The first output signal from comparator 736
and ihe second output signal from voltage comparator 726
are applied to a logic circuit 740, which provides the
idle control signal as an output on line 742 when both
of the two output signals are in the high state. Logic
stage 740 can be of any suitable type for providing
the idle control signal when each of the two output
signals are in the high ~tate, for example, an AND gate.
As in the case of the embodiment shown in
Figure 5, the idle control signal at output 74~ of
delay stage 644 causes the same three functions to be
produced by block 648 as were produced by it in Figure
5, and they are therefore not discussed again in detail.
While there have been shown and described
what are at present considered to be the preferred
embodiments of the present lnvention, modifications
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21-DSH-2520
- 29 -
thereto will readily occur to those skilled in the
art. It is not desired, therefore, that the invention
be limited to the specific arrangements shown and
described, and it is intended to cover in the appended
claims all such modifications as fall within the true
spirit and scope of the invention.
`
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