CELLULE DE MEMOIRE A ACCES SELECTIF STATIQUE ALIMENTEE PAR LES LIGNES DE COLONNE

COLUMN LINE POWERED STATIC RAM CELL

Abrégé anglais

COLUMN LINE POWERED STATIC RAM CELL
ABSTRACT OF THE DISCLOSURE
A column line powered static random access memory (RAM) cell and a group
of four mutually contiguous cells in an array of memory cells is disclosed. A common
resistor supply node which is required in a prior art static RAM cell wherein it is
centrally disposed within the group is deleted in the structural layout as disclosed in the
present invention. The common source node remains, which is the ground line. In order
to replace the common resistor supply node to which resistors are attached, the present
invention discloses that the resistors are connected to a DATA line on a first cell, and
to a DATA line on a second cell. Alternatively, these resistors can be connected to a
DATA line find then respectively to a DATA line. A third alternative is where one
resistor is connected to the DATA line and one resistor is connected to the DATA line.
In a preferred embodiment, the principal components of each cell include a plurality of
insulated gate field-effect transistors, each having a source diffusion region and a drain
diffusion region formed within the substrate and a plurality of impedance devices
electrically connecting the column lines to the drain diffusion of the transistors in each
cell. The impedance devices extend radially from the column lines into the interior of
each cell, and at least one of the diffused regions of each transistor in each cell is
formed in common with a diffused region of a transistor of a contiguous cell.

Revendications

1. In an integrated circuit memory comprising, in combination:
a substrate of semiconductor material of a first conductivity type;
an array of memory cells fabricated on the substrate in rows and columns;
each cell of the array including first and second data storage transistors,
first and second enabling transistors, and first and second impedance devices having
first and second nodes, each of the transistors having a gate, and source and drain
diffusion regions formed in the substrate;
the gate of the second data storage transistor being electrically connected
to the drain diffusion of the first data storage transistor, to the drain diffusion of the
first enabling transistor, and to the first node of the first impedance device thereby
defining a first data node in each cell of the array;
the gate of the first data storage transistor being electrically connected to
the drain diffusion of the second data storage transistor, to the drain diffusion of the
second enabling transistor, and to the first node of the second impedance device thereby
defining a second data node in each cell of the array;
the drain diffusion of the first data storage transistor being formed in
common with the drain diffusion of the first enabling transistor of each cell of the
array;
the array including a first group of four of the cells disposed in mutual
contiguous relation to each other in a first row and in a second row adjacent to the first
row, and in a first column and in a second column adjacent to the first column;
the source diffusions of the second data storage transistors of contiguous
cells in the first and second rows of the first group being formed in common,
respectively; and,
the second nodes of the first and second impedance devices being connected
to any of the sources of the enabling transistors.
2. The memory as set forth in Claim 1 wherein both of the second nodes
of the first and second impedance devices are electrically connected to the source of
the first enabling transistor.
-11-

3. The memory as set forth in Claim 1 wherein both of the second nodes
of the first and second impedance devices are electrically connected to the source of
the second enabling transistor.
4. The memory as set forth in Claim 1 wherein the first impedance
device is electrically connected to the source of the first enabling transistor and the
second impedance device is electrically connected to the source of the second enabling
transistor.
5. The memory as set forth in Claim 1 wherein the first impedance
device is electrically connected to the source of the second enabling transistor and the
second impedance device is electrically connected to the source of the first enabling
transistor.
6. The integrated circuit memory as defined in Claim 1 wherein the
common impedance node formed by the interconnection of the second nodes of the first
and second impedance devices is disposed substantially in the geometrical center of the
first group of cells, the first and second impedance devices of each cell extending
radially from the common impedance node to the interior of the cell.
7. The integrated circuit memory as defined in Claim 6 wherein each of
the first and second impedance means of each cell is formed as an integral portion of a
polycrystalline strip which interconnects the common impedance node to the
corresponding first and second internal cell nodes, respectively, each impedance means
including a body of substantially pure polycrystalline silicon defining a first conductive
path and a diffusion of impurities of the opposite conductivity type disposed within a
region of the body defining a second conductive path, a diffused-nondiffused junction
being defined by the interlace of the diffused region with the substantially pure
polycrystalline silicon body, the first and second paths defining a series electrical path
from the common impedance node formed by the interconnection of the second nodes of
the first and second impedance devices to the corresponding internal cell node.
-12-

8. The integrated circuit memory as defined in Claim 1, the array
including an additional group of four mutually contiguous cells identical to the first
group contiguously disposed in the first and second rows and in the first and second
columns on each side of the first group;
the source diffusions of the first and second enabling transistors of each cell
in the first and second columns and first row of the first group being formed in common
with the source diffusions of the first and second enabling transistors of corresponding
cells of the contiguous group of cells disposed in the first and second columns and in the
row immediately preceding the first row;
the source diffusions of the first and second enabling transistors of each cell
in the first and second columns and the second row of the first group being formed in
common with the source diffusions of the first and second enabling transistors of
corresponding cells of the contiguous group of cells disposed in the first and second
columns and in the row immediately succeeding the second row;
the source diffusions of the first data storage transistors of the adjacent
cells of the first group disposed in the first and second rows and in the first column
being formed in common, respectively, with the source diffusions of the first data
storage transistors of corresponding cells of the contiguous group of cells disposed in
the first and second rows and in the column immediately preceding the first column of
the first group;
the source diffusions of the first data storage transistors of the adjacent
cells of the first group disposed in the first and second rows and in the second column
being formed in common, respectively, with the source diffusions of the first data
storage transistors of corresponding cells of the contiguous group of cells disposed in
the first and second rows and in the column immediately succeeding the second column
of the first group;
the gates of the first and second enabling transistors of each cell of the first
group disposed in the first row being formed in common with each other and with the
gates of the corresponding enabling transistors disposed in the first row of the
contiguous groups immediately preceding and succeeding the first group thereby
defining a first row address line common to each cell in the first row of the array; and
the gates of the first and second enabling transistors of each cell of the first
-13-

group disposed in the second row being formed in common with each other and with the
gates of the corresponding enabling transistors disposed in the second row of the
contiguous groups immediately preceding and succeeding the first group thereby
defining a second row address line common to each cell in the second row of the array.
9. The integrated circuit memory as defined in Claim 8 including:
a first conductive strip extending transversely with respect to the common
row address lines across each row of cells, the first conductive strip being electrically
connected to the common source diffusions of the first data storage transistors disposed
in adjacent columns of contiguous groups thereby defining a first source supply line for
each pair of contiguous columns of groups,
a second conductive strip extending transversely with respect to the
common row address lines across each row of cells, the second conductive strip being
electrically connected to the common source diffusions of the second data storage
transistors in each group thereby defining a second source supply line for each column
of groups;
a third conductive strip extending transversely with respect to the common
row address lines across each row of cells, the third conductive strip being electrically
connected to the first enabling transistor source of each cell of each column thereby
defining a first data output line common to each cell of each column, and also
connected to the common impedance node formed by the interconnection of the second
nodes at the first and second impedance devices defining a means of providing cell
standby power without a line used only as a positive supply; and
a fourth conductive strip extending transversley with respect to the common
row address lines across each row of cells, the fourth conductive strip being electrically
connected to the second enabling transistor source of each cell of each column thereby
defining a second data output line common to each cell of each column.
-14-

10. In a Mos static integrated circuit memory of the type including an array of
memory cells fabricated on a semiconductor substrate in rows and columns, each cell
including principal components interconnected to store bits of binary data including
first and second impedance devices having first nodes connected to internal data
storage nodes and second nodes for the supply of voltage to the memory cell, an
improved structural layout for the principal components of each cell in a group of four
mutually contiguous cells of the array comprising:
a common impedance node, formed by the interconnection of the second
nodes of the first and second impedance devices connected to at least one of the data
lines disposed substantially in the geometrical center of the group as defined by the
intersection of a first centerline axis and a second centerline axis disposed substantially
perpendicular to the first axis; and
corresponding components of contiguous cells in each row of the group being
symmetrically disposed with respect to each of the first and second axes.
11. The combination as defined in Claim 10 wherein each cell includes as
principal components a plurality of insulated gate field-effect transistors each having a
source diffusion and a drain diffusion formed in the substrate, at least one of the
diffused regions of each transistor being formed in common with a diffused region of
another transistor of a contiguous cell.
12. The combination as defined in Claim 11, including first and second
insulated gate field-effect data storage transistors and first and second insulated gate
field-effect enabling transistors, the source diffusions of the first data storage
transistors of column contiguous cells being formed in common, the source diffusions of
the second data storage transistors of row contiguous cells being formed in common,
and the drain diffusions of the first data storage transistor and the first enabling
transistor being formed in common in each cell.
13. The combination as defined in Claim 12, wherein the gate of the first
data storage transistor is electrically connected to the drain diffusion of the second
enabling transistor and to the drain diffusion of the second data storage transistor
-15-

thereby defining a first data node, the gate of the second data storage transistor being
electrically connected to the drain diffusion of the first enabling transistor and to the
drain diffusion of the first data storage transistor thereby defining a second data node,
the combination further including first and second impedance devices in each cell of the
group of four mutually contiguous cells, each of the impedance devices electrically
connecting the common impedance node to the first and second data nodes,
respectively, of each cell.
14. The combination as defined in Claim 13 wherein each impedance
device extends radially from the common impedance node, at least one impedance
device of each cell being angularly displaced with respect to the axes by an angle
measuring less than a right angle.
15. An integrated circuit memory comprising:
a substrate of semiconductor material doped with impurities of a first
conductivity type;
an array of memory cells fabricated on the substrate in input rows and
output columns;
the substrate within each cell of the array including first and second pairs of
active surface areas surrounded by a substrate field area, the first pair being the situs
of first and second data storage transistors, and the second pair being the situs of first
and second enabling transistors;
a strip of gate insulating material disposed over a portion of each active
situs area;
a diffusion of impurities of the opposite conductivity type disposed in the
substrate beneath each active surface area on either side of the gate insulating strip
thereby forming source and drain diffusion regions for each transistor, a nondiffused
channel region being defined in the active substrate area beneath the gate insulating
strip and between the source and drain diffusion regions, the source and drain diffusion
regions of each transistor extending through the surrounding field regions of the
substrate for predetermined distances;
a first layer of electrical insulating material being disposed over the
-16-

substrate field area of each cell and around but not over the active situs area of each
cell;
a conductive gate strip deposited on each gate insulating strip, the
conductive gate strips extending transversely with respect to the associated source and
drain regions and across the surrounding field insulation;
the conductive gate strips of the first and second enabling transistors of
each cell of each input row being formed in common thereby defining a common row
address line for each input row;
the source diffusions of the first and second enabling transistors of each cell
in a selected row being formed in common with the source diffusions of the first and
second enabling transistors of contiguous cells of an adjacent row respectively;
the conductive gate strips of the first and second data storage transistors of
each cell extending transversely with respect to the associated diffused source and
drain regions across the field insulation and being disposed in electrical contact with the
drain diffusions of the second and first enabling transistors, respectively, and in
electrical contact with the drain diffusions of the second and first data storage
transistors of the same cell, respectively;
first and second impedance means each having a first and second terminal
portion, the first terminal portion being electrically connected to the drain diffusions of
the first and second data storage transistors of each cell, respectively, thereby defining
a first and second data node in each cell, the second terminal portions of the impedance
means in each cell of a first group of four mutually contiguous cells being electrically
connected together to define a common impedance node connected to one of them or
data lines common to a column of cells;
the source diffusions of the first data storage transistors of each cell in a
second group of four mutually contiguous cells being formed in common thereby
defining a first common source supply node, the cells of the second group being disposed
in the adjacent rows in which the cells of the first group are disposed, one cell in each
row being common to each of the first and second selected groups;
the drain diffusion of the first data storage transistor of each cell being
formed in common with the drain diffusion of the first enabling transistor of each cell;
the source diffusion of the second data storage transistor of each cell being
-17-

formed in common with the source diffusion of the second data storage transistor
disposed in the contiguous cell of the same row and adjacent column thereby defining a
second source supply node;
a second insulating layer deposited over the first insulating layer, the row
address lines, gate strips and impedance devices;
a first conductive strip deposited over the second insulating layer and
extending transversely with respect to the row address lines across each row of cells,
the first conductive strip being electrically connected to each of the first common
source supply nodes defined by a plurality of the second groups, the mutually contiguous
cells of each of the second groups being disposed in adjacent columns, thereby defining
a first source supply line common to each cell in adjacent columns containing the
second groups;
a second conductive strip deposited over the second insulating layer and
extending across each row of cells substantially parallel to the first conductive strip,
the second conductive strip being electrically connected to the common source
diffusions of first enabling transistors of contiguous cells in the column thereby defining
a common data output line for each of the cells in the column, and also connected to
the common impedance node defining a means of providing cell power without a line
used only as a power supply;
a third conductive strip deposited over the second insulating layer and
extending across each row of cells substantially parallel to the second conductive strip,
the second conductive strip being electrically connected to each of the common source
diffusions of the second enabling transistors of contiguous cells in the column thereby
defining a common data complement output line for each of the cells in the column;
a fourth conductive strip deposited over the second insulating layer and
extending across each row of cells of the array and substantially parallel to the third
conductive strip, the fourth conductive strip being electrically connected to each of the
second source supply nodes of each cell in the column thereby defining a second source
supply line common to each cell in the column.
-18-

Description

1~ ~i3~
BACKGROUND OF THE INVENTION
The present invention is concerned with random access
memories of the type fabricated on a monolithic semiconductor
chip using insulated gate semiconductor field-effect transi-
stor technology, and more particularly relates to an improved
structural layout for the principal components of each cell
of an integrated circuit memory.
DESCRIPTION OF THE PRIOR ART
Large scale integration (LSI) techniques have brought
about the construction of large arrays of binary storage
elements on a single chip of silicon. These storage cells,
typically using MOS technology, consist of multi-component
circuits in a conventional bistable eonfiguration. The
immediate advantages of sueh semiconduetor storage devices
are the high paeking density and low power requirements. The
insulated gate MOS transistor has served well in this
applieation area sinee it re~uires less substrate area (there-
by inereasing the packing density) and operates at very low
power levels.
A well known memory cell circuit arrangement which
utilizes insulated gate MOS field-effect transistors is the eross-
coupled inverter stage as disclosed in U.S. Patent 3,967,252.
In that arrangement the gates of a pair of insulated gate
MOS field-effect transistors are cross coupled to a true data
node, referred to as the DATA node, and a complementary data
node, commonly designated as the ~A~A node. Binary information
stored within the cell is maintained by impedance means which
are connected to the data nodes to maintain the potential at
the gate of the transistors at a predetermined level which
corresponds to the logic content of the cell.
@;,;~
~.

`` ~153i~Z
In the static random access memory cells shown in
U.S. Patent 3,967,252, there are two cross-coupled inverters
comprising two load devices and four transistors. In an
effort to minimize the substrate area required for a given
number of memory cells, the two load devices in the static
cell of each inverter have been fabricated as an integral
portion of a polycrystalline silicon strip which interconnects
a common drain supply node with a data node as disclosed and
claimed in United States Patent No. 4,125,854, and assigned
to a common assignee.
There remains considerable interest in minimizing
the dimensions of the cell structure of integrated circuit
memories to provide improved performance and higher
- 2a -

~1531~2
packing density. One prior art approach for minimizing the dimensions of a
conventional cross-coupled inverter stage is illustrated in FIGURE 3 of the drawing
shown in lJnited States Patent No. 4,125,854. In that arrangement, shared diffusion
regions interconnect the principal components of the cell to corresponding components
of adjacent cells in the same row or in the same column. Also, a pair of cells in a single
column are energized from a common drain supply node. An object of the application
issued as United States Patent No. 4,125,854 is to provide an improved structural layout
for the principal components of each cell so that the shared diffusion regions and the
common power supply nodes may be utilized more efficiently.
A related object of the present invention is to delete one of the power
supply nodes found in all static memory cells by connecting the resistors fabricated as
an integral part of the poly (i.e., polysilicon) interconnect to the data (column) lines
rather than to a VDD line, allowing deletion of that VDD line running through the cell
and thus allowing substantial reduction in each cell area.
SUMMARY OF THE INVENTION
A further reduction in the physical size of a memory cell for an integrated
circuit memory can be accomplished by connecting the resistors to the data (column)
lines, eliminating the need for the positive power supply line, VDD, which is routed to
all of the memory cells in prior art static RAM cell layouts. The cell of the present
invention still remains symmetrical about the first and second mutually perpendicular
axis of symmetry, allowing sharing of data (column) contacts between mutually adjacent
cells. In addition, data (column) lines contact multiple load resistors to the cells,
eliminating the need for the positive power supply VDD.
The novel features which characterize the present invention are defined by
the appended claims. The foregoing and other objects, advantages and features of the
present invention will hereinafter appear, and for purposes of illustration of the
invention, but not of limitation, an exemplary embodiment of the invention is shown in
the appended drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGURE 1 is a block circuit diagram of a portion of a random access
memory which utilizes a memory cell constructed according to the teachings of the
present invention;

11~3~2
FIGURE 2 is an electrical circuit diagram of a memory cell which is
representative of the prior art;
FIGURE 3 is an electrical circuit diagram of the memory cell shown in
FIGURE 1 and shows one embodiment of the present invention;
FIGURE 4 is an electrical circuit diagram of the memory cell shown in
FIGURE 1 and shows a second embodiment of the present invention;
FIGURE 5 is an electrical circuit diagram of the memory cell shown in
FIGURE 1 and shows a third embodiment of the present invention;
FIGURE 6 is an electrical circuit diagram of the memory cell shown in
FIGURE 1 and shows a fourth embodiment of the present invention;
FIGURE 7 is a partial substrate layout diagram showing a grouping of
memory cells; and,
FIGURE 8 is an elevation view, in sections, taken along the line VIII-VIII of
FIGURE 7.
DETAILED DESCRIPTION
In the description which follows, the present invention is described in
combination with a random access memory of the type utilizing insulated gate field-
effect transistor technology. The structure as disclosed herein may be fabricated on a
single semiconductor chip and is primarily intended for sllch fabrication.
Referring now to FIGURE 1 and FIGURE 3 of the drawings, a portion of a
random access memory which utilizes circuitry constructed according to the teachings
of the present invention is illustrated. In FIGURE 1, a portion of a random access
memory includes a plurality of static memory cells 10 which are part of an array of
many such cells arranged in rows and columns in the conventional manner. The memory
cells 10 are disposed in separate columns and accordingly connected to separate
complementary data buses Dl, Dl and D2, D2. Since the memory cells are disposed in
separate rows, the rows are addressed or enabled by separate row address lines RA1 and
RA2, respectively. The row address line RAl enables all the memory cells in a second
row.
RAl and RA2 are mutually exclusive in that only one row of memory cells is
selected al one time.

1153~12
A sense amplifier is indicated generally by the reference numeral 12 and is
connected to the output of each of the columns. The sense amp 12 may be of any
conventional type, for example, that which is disclosed and claimed by U. S. Patent
3,967,252. Write control circuits (not shown~ may be connected to drive the column
buses during a write cycle in the conventional manner. Column enable means (not
shown) may be provided to connect different pairs of column buses to a single sense
amp, or a separate sense amp may be provided for each pair of column buses.
One of the main differences in allowing implementation of this proposed new
cell is that the write control circuits used must be different than those in the
10 conventional manner in the sense that when writing the memory cell, any given DAT~
or DATA line must be held low in the write mode for a small percentage of the duty
cycle. Namely, the DATA and DATA lines would normally be held high near VDD, the
positive supply voltage, and during the write mode, one would be briefly brought low,
rather than indefinitely brought low, as on a conventional write circuit. This is
commonly referred to in the art as pulsing the data or DATA lines when attempting to
"write" or input data to a selected cell. If the data and DATA lines are brought low, for
example, for 50 nanoseconds, and the internal time constant on node 1 and node 2 is on
the order of a millisecond due to the use of very high valued resistors (such that the
time constant of Rl times capacitance on node 1 is very long compared with the time
20 that the DATA or DATA lines are brought low), then the nonselected cells will not be
affected by the writing of the selected cell in the memory matrix.
An electrical schematic diagram of the memory cell 10 is illustrated in
FIGURES 3, 4, 5 and 6 of the drawings. The binary memory cell 10 comprises first and
second complementary data input nodes D and D(DATA and DATA) which provide a
direct current impedance path and a relatively higher direct current impedance path
corresponding to each binary logic state. First and second impedance means R1 and R2
electrically connect a source of current to the internal data nodes 1 and 2 from the
column lines D and D which are held high, near VDD in voltage, by the sense amps. This
provides a means of continuous power allowing the cells to be static in the sense that
30 nonoperation of the cells or non-exercising (non-refreshing) of the cells will result in the
cells retaining the previously written data, without a need for refreshing the cells
periodically. This characterizes a static cell as compared to a dynamic cell.

~153~12
Jr~ The structure of the impedance means R1 and R2 is described in detail in
` - United States Patent No. 4,125,8541~whicb~sn~i~p~a~
The me~mory cell lO also includes a pair of cross-coupled insulated gate field-effect
data storage transistors Q1 and Q2' respectively, and are connected by enabling
transistors Q3 and Q4 that are connected to the corresponding row of address lines RA.
The channel between the drain and source terminals of transistors Q1 and Q2
electrically connect nodes 1 and 2 to a source node Vss when conducting.
In the operation of the cells of FIGURES 3, 4 and 5, the row address line RA
is low (logic "O") so that the enabling transistors Q3 and Q4 of the memory cell 10 which
are connected to the row address line RA are turned off. This allows the column lines D
and D to have a voltage level substantially equal to VDD, because there are no current
paths to the source voltage Vss other than through the very high valued resistors R1 and
R2. In a typical circuit, VDD may be five (5) volts, in which case the column lines D
and D would be about five volts. In this state, current will flow through the column
lines D and/or D into the standby resistors Rl and R2 of each cell respectively in which
cell load resistors are connected to that respective D (DATA) or D (D~TO line. On a
given column line, one-half of the cells are connected to the DATA line (as represented
in FIGURE 3), and the other half of the cells are connected to the DATA line (asrepresented in FI~;URE 4), to equalize the standby current from the D and D lines.
Assume that a logic "O" has been stored in the memory cell 10 so that the
transistor Q2 is turned off and data node D is substantially at VDD. Then when the row
address line RA goes high, that is, is raised to a bias potential corresponding to a logic
"1", the memory cell lO is selected by the "turn on" of transistors Q3 and Q4. This
results in a current path to Vss through the transistors Q1 and Q3 and the column line
D. The transistor Q2 is turned off so that no current path is established from the
column line D to ground, exeept through very high impedance standby resistors. As a
result, the data node D remains substantially at VDD, while node D is being discharged
low through Q3 and Ql This al10ws sensing of the correct state of the cell. If, on the
other hand, a logic "1" is stored in the address of the memory cell 10, transistors Q1 and
Q3 are off and Q2 and Q4 are on, discharging the D line rather than D line, allowing the
reverse state of the cell to be sensed. It is important in the read mode that the D and D
discharge levels during readout of the cell be controlled so that nodes D and D do not

i~s3i~2
fully discharge to Vss for substantial periods of time in that this would tend to write all
other cells in the column to the readout state of the selected cell on the column. This
is accomplished by insuring that the read cycle is limited in the respect that nodes D
and 6 discharge less than 50% of the precharge value of VDD. In this way, there is
always a positive supply for the non-selected cells, providing standby current to retain
previously written data.
To write the cell, it is necessary that nodes D or D, namely DATA and
DATA lines, are brought low near Vss, forcing low one of the two internal cross-coupled
nodes 1 or 2, depending respectively on whether it is node D or D that is brought low
10 during the write cycle. Specifically, if node D is brought low when node 1 is high,
transistor Q3 will turn on, pulling node 1 low, allowing transistor Q4 to pull node 2 high,
forcing Q1 on and Q2 off. When RAis then returned to Vss, deselecting the cell, or D
is returned high to VDD, the cell retains the state written into it, since R2 will provide
the current necessary to keep node 2 high, forcing Q1 to remain on, which forces node 1
to be low, keeping Q2 off. In this manner, there is cell data retention in a static
manner with standby power supplied by the column lines through Rl and R2.
In the process of writing the cell, again a DATA or DATA line is brought
low. This condition, if maintained indefinitely, would write other cells on the column
and must be limited to short time periods relative to the internal time constant of the
20 cell. If, for example, Rl is a high valued resistor on the order of 100 megohms and the
internal capacitance on node 1 of the cell is 0.1 pico-farad, the time constant of node 1
or 2 would be very long compared to the necessary write time of the cell when node D
or D is brought low, by several orders of magnitude.
The foregoing procedure allows the selected cell to be safely written
without writing other cells that are not selected on the column line, and allows
elimination of the VDD line that transverses the cell as a connection to resistors Rl and
R2. Specifically referring to United States Patent No. 4,125,854, VDD as shown in
FIGURES 3, 4, 5 and 6 of said patent application has now been eliminated and the
connections through contacts 42 are made with D or D. Eliminating VDD in this manner
30 allows the memory cell area to be substantially reduced with favorable improvements in
the cost of production and allows fabrication of integrated circuit memories with
greater bit densities.

~i5311Z
In one preferred embodiment of the present invention there is provided an
integrated circuit memory comprising a substrate of semiconductor material of a first
conductivity type; an array of memory cells fabricated on the substrate in rows and
columns; each cell of the array including first and second data storage transistors, first
and second enabling transistors, and first and second impedance devices, each of the
transistors having a gate, a source diffusion region, and a drain diffusion region formed
in the substrate; the gate of the second data storage transistor being electrically
connected to the drain diffusion of the first data storage transistor, to the drain
diffusion of the first enabling transistor, and to the first impedance device thereby
10 defining a first data node in each cell of the array; the gate of the first data storage
transistor being electrically connected to the drain diffusion of the second data storage
transistor, to the drain diffusion of the second enabling transistor, and to the second
impedance device thereby defining a second data node in each cell of the array; the
drain diffusion of the first data storage transistor being formed in common with the
drain diffusion of the first enabling transistor in each cell of the array; the drain
diffusion of the second storage transistor being formed in common with the drain ofthe
second enabling transistor in each cell of the array; the array including a first group of
four of the cells disposed in mutually contiguous relation to each other in a first row
and in a second row adjacent to the first row, and in a first column and in a second
20 column adjacent to the first column; the source diffusions of the second data storage
transistors of contiguous cells in the first and second rows of the first group being
formed in common, respectively; and at least one of the first and second impedance
devices of each ceU of the first group being electrically connected to the source of at
least one of the enabling transistors.
The impedance devices are electrically connected in several different
embodiments such as (1) wherein both of the first and second impedance devices are
electrically connected to the source of the first enabling transistor (see FIGURE 4~; (2)
wherein both of the first and second impedance devices are electrically connected to
the source of the second enabling transistor (see FIGURE 3); (3) wherein the first
30 impedance device is electrically connected to the source of the first enabling transistor
and the second impedance device is electrically connected to the source of the second
enabling transistor (see FIGURl~ S); and (4) wherein the first impedance device is

~5;3~2
electrically connected to the source of the second enabling transistor and the second
impedance device is electrically connected to the source of the first enabling transistor
(see FIGURE 6).
Referring now to FIGURE 7, a substrate layout of a grouping of four
mutually contiguous memory cells is illustrated. The common impedance node 18 isconnected to the complement data line D. The complete absence of a power supply to
the common impedance node 18 should be noted.
The memory cell 10 is disposed upon a substrate 26 of an extrinsic
semiconductor material of a first conductivity type, for example, P-type
monocrysta~line silicon. Each of the field-effect transistors Q1 ~ Q4 include a source
region 28 and a drain region 30 (FIGURES 7, 8) in which impurities of the opposite
conductivity type, for example, N-type, have been diffused and extend substantially
parallel to each other in the conventional manner through an active region 32 of the
substrate 26. A layer 34 of field insulation is disposed over the surface of the substrate
26 and is formed in a relatively thin layer 36 in the gate zone which lies directly over
the active region 32. A diffused polysilicon layer 38 serves as a gate interconnect
portion for the transistor Ql formed over the active region 32. A layer 40 of the
electrical insulation, preferably oxide, is formed over the gate strip 38 and over the
field insulation 34.
The semiconductor material which forms the conductive gate strip 38 is the
same elemental semiconductor type as is the substrate 26, and is preferably constructed
of a continuous layer of polycrystalline silicon. Extrinsic impurities are diffused within
the gate strip 38 and may be either N-type or P-type. In a preferred embodiment, the
extrinsic impurities diffused into the gate strip 38 are of the opposite conductivity type
relative to the conductivity type of the substrate 26. For example, for a P-typesubstrate 26, the impurities diffused into the gate strip 38 are N-type, so that the
diffusion of the gate strip 38, source and drain regions 28, 30 and impedance devices Rl
and R2 may all be formed during a single diffusion step of an isoplanar silicon gate
process.
Each of the load impedance devices Rl and R2 include a body 42 of
substantially pure intrinsic semiconductor material defining a series conductive path
within the polysilicon gate strip 38. An intrinsic-extrinsic junction 44 is defined by the

~lS3~X
interface of the diffused gate strip 38 and the undiffused intrinsic body 42. Each series
path formed by the composit resistor/gate strip interconnects the data lines D, D (FIG.
3, 4 respectively) to the corresponding data nodes 1, 2. As used herein, the phrase
"intrinsic semiconductive material" means elemental semiconductor material which is
undoped and which has not been diffused or otherwise implanted with impurities.
The connection of the common impedance node 18 to the DATA line
comprises a metallization deposit 46 which is bonded directly to the oxide layer 40.
In conjunction with the embodiments described hereinbefore, it is preferred
that the structural layout include the common impedance node 18 disposed substantially
10 in the geometrical center of the first group of cells, the first and second load
impedance devices Rl and R2 of each cell extending radially from the common
impedance node to the interior of the cell.
In conjunction with the embodiments described hereinbefore, it is preferred
that the structural layout be such wherein each of the first and second impedance
means Rl and R2 of each cell is formed as an integral portion of the polycrystalline
silicon strip 38 which interconnects the common impedance node 18 to the
corresponding first and second internal cell nodes "1" and "2", respectively, each
impedance means including Q body of substantially pure polycrystalline silicon 42
defining a first conductive path and a diffusion of impurities of the opposite
20 conductivity type disposed within a region of the body defining a second conductive
path, a diffused-nondiffused junction 44 being defined by the interface of the diffused
region with the substantially pure polycrysta~line silicon body, the first and second paths
defining a series electrical path from the common impedance node 18 to the
corresponding internal cell node.
What is claimed is:
-10--