Note : Les descriptions sont présentées dans la langue officielle dans laquelle elles ont été soumises.
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The present invention relates to a digital switch for handling
time division multiplexed (TDM) pulse code modulation (PCM~ intelligence.
It is known in such switches for the PCM words or bytes received
over TDM highways into the switch to be converted from serial to parallel
format for handling within the switch, often with the reverse conversion
at the output side of the switch. In addition the thus converted data is
super-multiplexed within the switch so thatJ for instance, with P bit words
these words from eight PCM highways are super-multiplexed onto one highway
within the switch. Such a process is used separately for G0 and RETURN
paths. Such an arrangement has been found to give economies as compared
with the switching of lndividual serial highways.
An object of the present invention is to provide an improvement
to a switch of the above type.
According to the invention there is provided a digital remote
line concentrator for a system using time division multiplexed transmission
for communicating between a plura]ity of subscriber lines and a central
exchange controlling said concentrator, in which said system employs pulse
code modulation (PCh~ within the concentrator and between the concentrator
and the exchange, in which there are separate forward highways for commun-
ication from said subscriber lines through said concentrator directed to-
ward said exchange and reverse direction highways from the exchange toward
the subscriber lines, and in which the pulse code modulation employs a
plurality of channels allocated for the transfer of call communication
intelligence to and from the lines, the invention comprising a loop back
path within the concentrator between the forward highways and the reverse
highways for completing calls within the concentrator, said path including
means for introducing delay into all calls being completed over said loop
back path, the delay means comprising a memory for storing intelligence
from said channels for a period of one half of a PCM time frame, a time
frame being defined as a period during which intelligence from each of
said channels is transmitted.
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According to the invention there is furkher provided a remote
line concentrator for a time division multiple channel system having an
exchange or receiving digital data from the concentrator for comple~ing
calls from said concentrator to said exchange and from said exchange to
said concentrator, said concentrator terminating a plurality of groups of
subscriber lines, an outgoing network coupled to said concentrator to
transmit digital data from the lines to the exchange, an incoming network
coupled to said concentrator to transmit digital data from the exchange
toward said lines, each outgoing network comprising storage with capability
of at least one byte of intelligence from each channel, in which control
of transmission from said storage originates at the exchange and is forwar-
ded to said concentrator for transmission of an addressed byte over said
outgoing network in byte interleaved format, the invention comprising a
loop back path from said outgoing network to said incoming network, storage
means in said loop back path in said concentrator for storing outgoing
bytes of intelligence, said storage means imposing a delay of fixed dura-
tion on bytes of intelligence in said loop back path, and selected means
for transmitting bytes of intelligence from said loop back path storage
means to said incoming network to complete the transfer of bytes of intel-
ligence within the concentrator from a line of said concentrator to a line
of said concentrator.
It will be appreciated that with such a system if the output
side of the switch should fail, local calls can still be set up via the
loop-back connectionO Further, such a switch, with only the loop-back
connection at the "output" side is usable as a small local exchange.
An embodiment of the invention will now be described with
reference to the accompanying highly simplified block schematic drawlng.
The arrangement shown in the drawing serves a number, eight in
thi~ case, of blocks of subscribers, each consisting of 256 subscribers,
and served by eight PCM systems, each serving 32 subscriber lines, each of
which is allocated one time slot on his PCM system. The systems are
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"four-wire", i.e. separate forward and reverse highways are provided, and
PCM words or bytes are received from and sent to the subscribers~ lines in
serial byte-interleaved orm. As will be seen, the internal highway within
the switching arrangement is organised in parallel byte interleaved manner
with a bit rate of 2.048 Mb/s. After switching, the intelligence is conver-
ted back to serial form for transmission over eight thirty-channel PCM
systems. These latter are also "four-wire", and are similar to the PCM
systems leading to the lines, with the difference that two slots are
allotted to signalling and synchronisation functions.
The intelligence in the parallel byte-interleaved form may be
looped back from the forward side of the switching arrangement to the
reverse side with a half frame delay. This enables local calls to be set
up within the switching arrangement, which is useful if the arrangement is
a line concentrator remote from a parent exchange and if the connections
to the parent exchange should fall. In such a case the concentrator can
continue to handle local calls. Furthermore, the arrangement can be used
as a small local exchange or PABX, with some connections to a remote
exchange.
Referring now to the drawing, the arrangement is in two parts,
that above the dashed line for the forward direction, and that below the
line for the reverse direction. The arrangement can switch up to 2048
subscribers to 256 time slots in a 125 ~sec. frame, i.e. the PCM byte rate
is 8 KHz. The subscriber's lines are grouped in blocks of 256, each block
served by eight 32 channel PCM highways, on which intelligence is received
in serial byte-interleaved form. The arrangement shown has eight line
receiver and staticiser blocks such as 10 each of which receives eight PCM
forward highways. This block includes such pulse re-shaping and amplifi-
cation as is needed, and staticizes each received byte, for application to
a serial-to-parallel converter 11, from which the intelligence passes to
a second stage multiplexer 12 and to a RAM 13. The converter 11, like most
of the blocks included in the drawing is a "custom" chip.
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The "parallelised" bytes are thus stored sequentially in the
locations of the RAM 13~ which is a 256 byte store, each byte location
being able to accommodate an eight bit byte during the first half of a
2.048 MHz time slot These bytes now await switching, which is controlled
from the cen~ral control ~no~ shown) of the system using the arrangement
shown. To switch the bytes from one subscriber's line, the central control
sends an eleven bit address in a selected time slot (on the 2.048 MHz high-
way) to define the line whose byte is to be switched to that time slot.
This address, received over the connections shown at 15 is applied to all
of the RAMs such as 13 and to the multiplexer 12. Eight bits of the address
selects the same-numbered location in all RAM's such as 13 while ~he other
three bits are applied to the multiplexer 12 to cause it to select the
block from which a byte is to be switched. This addressing is effected
in the second half of the 2.048 MHz time slot. Note that the multiplexer
12 has inputs from all eight of the converters such as 11.
The output from the multiplexer 12, which is in parallel byte-
interleaved "super multiplexed" form is applied to a so-called ROM system
17, and if it is speech during an established connection it passes through
the system 17 unaltered. This system includes a read-only memory, and its
function is tone generation and injection, and in some cases pad switching.
Pad switching is necessary where lines w;th widely varying attenuation
characteristics are present, in which case for some at least of the calls
to be set up, pads may have to be switched in. This system is controlled
from the central control over an input CB, via which central control sup-
plies a control word for each of the 256 time slots to define whether the
output of the ROM system 17 is unattenuated speech, or attenuated speech
~in which case the control word indicates which pad is to be cut in), or
whether a tone, suitably cadenced, is to be injected into the particular
time slot.
From the ROM system 17 the speech or othcr intelligence passes
to a paraliel-to-serial converter 18, which may be the same "custom" chip
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as the converter ll but used "in reverse", the output of which is eight 30
channel PCM highways. As already mentioned, only 30 channels are usable
on these highways since channels 0 and 16 are used for synchronisation
and signalling.
The output of the ROM system is also applied to a fixed delay
RA~I 19 and stored therein and read out half a frame later to give the loop-
back facility. As will be seen later, this provides the facility whereby
local calls can be set up wholly within the arrangement shown.
In the reverse direction, byte-interleaved serial intelligence
l~ arrives via eight 30 channel PCM highways at a serial-to-parallel converter
20, The output of this converter is applied to a select unit 21, to which
the output of the fixed delay RAM 19 is also connected, and at which it
is multiplexed with the output of the RAM 19. The central control deter-
mines the loop-back status of each time slot, i.e. it decides whether that
time slot is in use for intelligence from the converter 20 or the RAM 19.
This control is effected via an isolation bit input IB.
The data which leaves the block 21, which in normal operation is
usually the bytes received from the converter 20, passes therefrom to
another ROM system 22, which is very similar to the system 17. Thus,
dependent upon the control word applied to it from the central control via
the input CB, this block 22 passes unattenuated speech, attenuated speech,
or cadenced tones.
The intelligence in both directions is aligned at this point, so
the same eleven bit address is used to control both reverse and forward
switches. Thus the three high order address bits enable the write pulses
for one of the eight reverse-direction RAM's such as 24, Intelligence is
read from the sequential RAM locations in the first half of a 2.048 ~læ
on all eight blocks of 256 subscribers, but only one of these is effective
due to the selection due to the first three bits. To effect this, the
write enable gating 23 controls writing into the selected one of the
RAM's 24,
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From the appropriatc one of the RAM~s Z4 the intelligence goes
to a parallel-to-serial converter 25 from which it passes to a staticiser
and line driver block 26. The output of this latter is eight 32-channel
PCM highways~ and these give access to the lines served.
The fixed delay RAM 19, which introduces a half-frame delay,
enables local calls, i.e. calls in which both lines are in the same 2048,
to be set up without proceeding further into the system. If the arrange-
ment shown is at a concentrator, this means that for a local call the
parent exchange is not involved. In addition, if the links to the parent
exchange all fail, then the concentrator can still function for local calls.
Note that such a call uses two time slot channels separated in time by half
a frame.
If the communication to the parent exchange fails when there are
local calls in existence which do not use the loop-back connection, these
calls can in some cases be re-arranged so as to use such connections under
control of the controlling program of microprocessors in the various blocks
shown. When such a re-arrangement takes place it is extremely unlikely
that the subscribers involved in the re-arranged calls would realise that
anything had happened.
Normally in a concentrator system charging is effected at the
parent exchange: in the present system if the communication to the parent
exchange fails normal telephone calls set up via the RAM 19 are not
charged during the failure period.
A system as described with or without the blocks 18 and 20 can
be used as a local exchangeJ or a PABX, with links to a main exchange or
~in the case of a PABX~ an exchange in the public network.
Only 240 of the 256 time slots on the internal "super multiplex"
are available for speech, as two time slots out of each 32 are used for
synchronization and signalling. In the forward direction the remaining
- 30 16 time slots are assigned to multîfrequency signalling (e.g. M~4), and
the ROM system 17 outputs for these time slots are stored in the block 27
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and then transmitted over a serial PCM link to a V~ receiver.
Considered from the "equipment practice" aspect, each level of
switching provides four cards for 512 subscribers, plus one card for each
additional 512 subscribers.
In the interest of system security, the arrangements shown in
the drawing are triplicated, with the outputs from blocks 18, and 26,
taken via majority decision gating ~not shown~. This functions in known
manner to give a majority decision output, and gives an alarm in the event
of any discrepancies being detec~ed. The majority decision gating and the
alarm circuitry associated therewith are not shown to avoid needlessly
complicating the drawing.
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