CIRCUIT DE COURANT EN RAPPORT GEOMETRIQUE

CURRENT MIRROR CIRCUIT

Abrégé anglais

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Abstract of the Disclosure
A current mirror circuit in which error between
input current and output current is small and which
can operate with low voltage. First and second current
mirror transistors of a first conductivity type have
their emitters each connected to a power supply, their
bases connected together and their collectors connected
to an input terminal and an output terminal respec-
tively. A current amplification factor compensating
third transistor of the first conductivity type is
provided which has its emitter connected to the bases
of the first and second transistors and its collector
connected to a reference potential point. A fourth
transistor of a second conductivity type is provided
for level shifting. This transistor has its collector
connected to the emitters of the first and second
transistors, its emitter connected to the base of the
third transistor and its base connected to the collector
of the first transistor. A current source is connected
between the third transistor and the reference potential
point.

Revendications

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A current mirror circuit comprising:
a first transistor of a first conductivity type having
a first emitter, a first base and a first collector, the
first emitter and first collector being connected to a power
supply and a current input terminal, respectively;
a second transistor of the first conductivity type
having a second emitter, a second base and a second collector,
the second emitter, second collector and second base being
connected to the power supply, a current output terminal and
the first base, respectively;
voltage level shift means including a third transistor
of the first conductivity type having a third emitter, a
third base and a third collector, the third emitter being
connected to the bases of said first and second transistors
and the third collector being connected to a reference
potential;
a fourth transistor of a second conductivity type having
a fourth emitter, a fourth base and a fourth collector, the
fourth collector, the fourth emitter and the fourth base
being connected to the power supply, the third base and the
first collector, respectively;
a current source connected between the reference poten-
tial and the third base; and
a resistor connected between the emitter of said fourth
transistor and the base of said third transistor.

2. The current mirror circuit according to claim 1 wherein
a fifth transistor of the first conductivity type is pro-
vided which has its emitter connected to the collector of
said second transistor, its collector connected to said out-
put terminal and its base connected to the emitter of said
fourth transistor.
3. The current mirror circuit according to claim 1 or 2
wherein the first conductivity type is PNP type and the
second conductivity type is NPM type.

Description

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This invention relates to a current mirror circuit
suitable for a low voltage inteyrated circuit.
A current mirror circuit is usually used as an active
load of a differential amplifier, and various types of
current mirror circuits are known and Figs. l(a) to l(c)
are circuit diagrams of examples of such known current
mirror circuits whereas Figs.2 to ~ are circuit diagrams
of current mirror circuits according to the invention.
Fig. l(a) shows a known current mirror circuit which
has transistors Qal and Qa2 with their respective base-
emitter paths connected in parallel. This circuit arrange~
ment has a drawback in that an error of a comparatively
large magnitude is provided between an input current Iin
and an output current Iout due to the base current of
transistors Qal and Qa2 as is well known in the art.
Fig. l(b) is an improved current mirror circuit
which comprises a compensating transistor Qb3 of the
~ same conductivity type to transistors Qbl and Qb2.
;~ The transistor Qb3 has its emitter connected to the
bases of transistors Qbl and Qb2, its base connected
to the collector of transistor Qbl and its collector
connected to circuit ground. According to this circuit
arrangement, the effect of the base current of transistors
Qbl and Qb2 on the input current Iin can be reduced by
a factor of the current amplification factor of transistor
Qb3. In this circuit, however, a supply voltage at the input

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terminal supplied with the input current Iin must be
lower than Vcc by the sum of the base-emitter voltages
(about 0.7 volt in case of a silicon transistor) of
transistors Qbl and Qk3. This involves a disadvantage
that a relatively high supply voltage, which is about
1.4 volts or above, is necessary for operating the
circuitO
Fig. l(c) shows still another improved current
mirror circuit. This circuit comprises emitter-coupled
NPN transistors Qc3 and Qc4 in addition to current
mirror PNP transistors Qcl and Qc2. Transistor Qc3
has its collector connected to a supply voltage Vcc
and its base connected to the collector of transistor
Qcl. On the other hand, transistor Qc4 has its
collector connected to the bases of transistors Qcl
and Qc2 and its base connected to a reference voltage
Vref. The emitters of transistors Qc3 and Qc~ are
connected through a current source of current value
I0 to circuit ground. The current I0 is set to be
higher than the sum of the base currents of transistors
Qcl and ~c2.
With this circuit the error between the input
current Iin and the output current Iout is I0/~3 at
maximum (~3 is the current amplification factor of
transistor Qc3). It will be understood that, since
I0 is relative~y low, the error is small. Transistor
Qc3 is provided for the level shift, and thus the
, ~

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supply voltage at the input terminal is determined by
Vref. Namely, the circuit of Fig. l(c) can be operated
from a low supply voltage so long as Vre~ has such a
magnitude to render all the transistors conductive.
However, this circuit arrangement is complicated in
construction in that the generation of the reference
voltage Vref applied to the base of transistor Qc4
is required.
An object of the invention is to provide a current
mirror circuit, in which the error between an input
current and an output current is small, and which can
operated from a low supply voltage and is simple in
construction.
In accordance with this invention, in a current
mirror circuit which comprises first and second
transistors of a first conductivity type having their
emitters each connected to a power supply, their bases
connected together and their collectors respectively
connected to an input terminal and an output terminal,
~0 and a third -transistor of the first conductivity type
having its emitter connected to the bases of the first
and second transistors, its collector connected to a
reference potential point and its base connected to
the collector of the first transistor, a fourth
transistor of a second conductivity type complementary
to the first conductivity type is provided which has
its collector connected to the power supply, its

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emitter connected to the base of the third transistor and
its base connected to the collector of the first transis-
tor, and a current source is connected between the base
of the third ~ransistor and the reference potential point.
This invention can be more fully understood from
the following detailed description when taken in conjunc-
tion with Figs. 2 to 4 of the accompanying drawings,
referred to hereinbefore.
Fig. 2 shows a current mirror circuit embodying the
invention. Like the well-known circuit, current mirror
transistors Ql and Q2 of PNP type are provided with
their emitters connected to a voltage source Vcc and
their bases connected together. The collectors of
transistors Ql and Q2 are respectively connected to an
input terminal 11, supplied with an input current Iin
and an output terminal 12 from which output current Iout
is led out. A PNP transistor Q4 i'3 provided for current
amplification factor compensation. This transistor Q4
has its emitter connected to the bases of transistors
Ql and Q2 and its collector connected to a reference
potential (circuit ground). An NPN transistor Q3 is
provided for level shifting, which has its collector
connected to voltage source Vcc, its emitter connected

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to the base of transistor Q4 and its base connected to
the collector of transistor Ql. Between the base of
transistor Q4 and circuit ground is connected a current
source IS for providing current I0. The magnitude of I0
is set greater than the base current of transistor Q4.
According to this circuit arrangement, the current
I0 of current source IS is set as follows:
I0 > Iout
~ x~
where ~1 is the current amplification factor of current
mirror transistors Ql and Q2 and ~2 is the current
amplification factor of transistor Q4. Namely, the
current I0 of current source IS can be set 1/~ lower
than in the prior art circuit of Fig. l(c). This means
that the base current of transistor Q3 which causes an
error can be reduced. Further, since the level shifting
transistor Q3 is provided, the voltage level at input
terminal 11 may be lower than Vcc by the base-to-emitter
voltage VgE of a single transistor (about 0.7 volt).
This means that the current mirror circuit of the
invention can be operated from a relatively low supply
voltage.
Fig. 3 shows another arrangement of the current
mirror circuit of the invention in which a resistor R
is connected between the emitter of transistor Q3
and the base of transistor Q4. With this circuit
arrangement, the level shift voltage can be increased

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up to VBE + IOR. Namely, the voltage loss of this
circuit becomes VgE - IOR and the loss voltage can be
reduced to the level just prior to ~he saturation of
first transistor Ql. Therefore, the circuit can be
operated from a supply voltage lower than the circuit
of Fig. 2~ `
Fig. 4 shows still another arrangement of the
invention in which a PNP transistor Q5 is provided for
improving the linearity of ~he current mirror circuit
by reducing the Early effect of transistor. Transistor
Q5 has its emitter connected to the collector of
transistor Q2, its collector connected to output
terminal 1~ and its base connected to the emitter of
transistor Q3. According to an experiment using such
circuit arrangement in which the collector-emitter
voltage VCE Of transistor Q2 is 0.3 volt, the bias
current in a zero-signal condition 200 microamperes
and the signal amplitude 100 microamperes, the total
harmonic distortion at 1 ~Hz was 0.1%. With the circuit
of Fig. 3, the total harmonic distortion is 3%.