Note : Les descriptions sont présentées dans la langue officielle dans laquelle elles ont été soumises.
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01 The present invention relates to an apparatus Eor
02 obtaining the histogram of the separation times between
03 successive events.
04 In known apparatus or measuring instruments of this
05 type, one simply counts the number of events occurring in a
06 given time period, then the ratio between the number of events
07 that occurred and the number of time units is calculated.
08 Such known apparatus do not allow one to carry out a
09 fine analysis of events occurring in pacXets or occurring
grouped in time.
11 Other known analysis systems allow only the recording
12 of the separation time between successive events such that the
13 separation time histogram can only be obtained later.
14 One object of the present invention consists of
providing an apparatus capable of establishing in real time,
16 histograms of the separation times between successive events.
17 Another object of the present invention consists of
18 providing an apparatus capable of carrying out a fine analysis
19 and a classification of events grouped into packets.
Another object of the present invention consists of
21 providing such apparatus that can be associated with an
22 appropriate circuit allowing one to know the occurrence of
23 events and to record the results.
24 According to one characteristic of the invention, an
apparatus is provided comprising a time base whose output is
26 connected to a first set of decade counters which are
27 associated with the detection means of the counter that keeps
28 track of the state of the counter which counts and which has
29 not yet overflowed, a corresponding set of AND gates each with
an input connected to the output of the corresponding detection
31 means and the other input connected to the source of events,
32 the detection means CLR input also being connected to said
33 source, through a delay circuit, the output of each AND gate
34 being connected to a second set of decade counters, each
associated with a memory, a timer whose input is connected to
36 the time base and whose output is connected to the transfer
37 control means of the contents of each counter of -the second set
38 to its associated memory, means for reading the controls of the
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01 memories to recording equipment, a second delay circuit whose
02 input is connected to the output of the timer and the output to
03 the CLR inputs of the counters.
04 The characteristics of the invention mentioned above,
05 as well as others, will appear more clearly upon reading the
06 description of an embodiment, the said description being made
07 in relation to the accompanying drawings, among which:
08 Figure 1 is a general block diagram of an apparatus
09 according to the invention;
Figure 2 is a schematic view of the memory and counting
11 circuits of the apparatus of Figure 1,
12 Figure 3A to 3G are timing diagrams illustrating the
13 operation of the apparatus of Figure l; and
14 Figures 4 to 7 are more detailed block diagrams of the
circuits of the apparatus of Figure 1.
16 In Figure 1, the events, whose timing separations are
17 to be analyzed, are applied, in the form of logic signals, to
18 terminal 1 which is connected to one input of a synchronization
19 circuit 2 whose second input is connected to the output of a
time base 3. The output of time base 3 is also connected to
21 the input of a timer 4 and to the input of a counting interval
22 determination circuit CID 5.1. The output of the
23 synchronization circuit 2 is connected to the input of a first
24 zero resetting circuit or CLR circuit 6 and to the input of an
inhibit circuit 7. The output of timer 4 is connected to the
26 input of a transfer circuit 8 and to the input of a second zero
27 resetting or CLR circuit 9.
28 In fact, the apparatus comprises a battery of CID
29 circuits 5.1 to 5.X, the counting input of a CID circuit 5.J
being connected to the carry output of CID circuit 5.(J-l).
31 The output of CLR circuit 6 is connected, in parallel, to the
32 zero resetting inputs of CID circuits 5.1 to 5.X.
33 The apparatus is comprised of another battery of
34 validation circuits 10.1 to lO.X. Each signal input of a
validation circuit 10.1 to lO.X is respectively connected to
36 the signal output of the corresponding 5.1 to 5.X CID circuit.
37 The apparatus is also comprised of a set 11 of counting
38 and memory circuits which is shown in greater detail in
39
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01 Figure 2. This set 11 is comprised of the circuits 111.1 to
02 lll.X, 112.1 to 112.(X-1), 113.1 to 113.(X-2),
03 ll(X-l).l and ll(X-1).2 and llX.l. The inputs of
04 circuits 111.1 to lll.X are respectively connected to the
05 outputs of circuits 10.1 to lO.X. The inputs of circuits
06 112.1 to 112.(X-l) are respectively connected to the
07 outputs of circuits Xl.l to Xl.(X-l), and so on, the inpu-t
08 of circuit llX.l being connected to the output of circuit
09 11 (X-l ) . 1 .
In other respects, the outputs of circuits 111.1 to
11 111.1 are connected in parallel to the signal inputs of a
12 multiplexer 12.1. Similarly, the outputs of circuits 112.1
13 to 112.(x-1) are connected, in parallel, to the input of a
14 multiplexer 12.2, and so on, the output of circuit llX.
being connected to the input of multiplexer 12.X.
16 The outputs of multiplexers 12.1 to 12.X are
17 respectively connected to the corresponding inputs of a
18 recording instrument 13. They are also connected, in parallel,
19 to the input of a detection circuit 14.
The output of transfer circuit 8 is connected in
21 parallel to the transfer control inputs of circuits 111.1 to
22 llX.l The output of CLR circuit 9 is also connected, in
23 parallel, to the zero resetting inputs of circuits 111.1 to
24 llX.l.
Finally, the output of the synchronization circui.t 2 is
26 also connected to the validation inputs of the validation
27 circuits 10.1 to lO.X. The validation input of the inhibit
28 circuit 7 is connected to the output of CLR circuit 9 and its
29 output is connected to the validation input of a recording
circuit 15 of which one output is connected to the input of an
31 inhibit circuit 16 and of which the other output is connected,
32 in parallel, to the control inputs of multiplexers 12.1 to
33 12.X. The network of detection circuit 14 is connected to the
34 inhibit input of inhibit circuit 16 whose output is connected
to the control input oE a recording apparatus 13.
36 The time base 3 is made up of, for example, a quartz
37 oscillator generating impulses at a frequency which is at l.east
38 equal to the maximum frequency at which the events to be
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01 counted can occur.
02 The synchroni~ation circuit 2 is a conventional circuit
03 which, for each signal applied at 1, generates at its output a
04 signal in phase with the time base impulse which immediately
05 follows the application of the signal in 1. In practice,
06 circuit 2 is comprised of an RS flip-flop 17, Figure 4, whose S
07 input is connected to the input 1, whose Q output is connected
08 to the D input of a D flip-flop 18 whose rI input is connected
09 to the output of the time base 3. The R input of 17 is also
connected to the output of 3. ~ence flip-flop 17 is activated
11 by each signal received from 1 and flip-flop 18 recopies the
12 state of 17 and is read at each impulse received from the time
13 base, the first flip-flop being reset to the rest state upon
14 reading the second flip-flop.
The timer 4 is a counter which operates like a
16 frequency divider by delivering periodically an impulse to
17 circuits 8 and 9 in order to trigger the recording into
18 apparatus 13 of the data in memory in circuits 111.1 to
19 llX.l. The capacity of the counter in timer 4, which
determines the frequency of impulses delivered to 8 and 9, is
21 chosen as a function of the maximum recording speed of
22 recording apparatus 13.
23 The transfer circuit 8 is a monostable circuit,
24 operating as a delay circuit and generates a transfer impulse a
certain time t after the signal emitted by 4.
26 The CLR circuit 9 is also a monostable circuit, also
27 fulfilling the role of a delay circuit. The delay introduced
28 by 9 is larger than that brought by 8, the time differential
29 between the two corresponding to the times allotted to carry
out the data transfers from circuits 111.1 to llX.l to the
31 multiplexers 12.1 to 12.X
32 The CLR circuit 6 is also a monostable whose purpose is
33 to introduce a delay which covers the time required to record
34 an event in circuit 111.1 to lll.X.
The CID circuits 5.1 to 5.X are divided by 10 counters,
36 linked in cascade. These coun-ters thus each deter~ine time
37 windows of multiple duration. Thus the DIC circuit 5.1
38 determines a time window lasting ten unit intervals, one unit
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01 interval being equal to the period of the time base 3. The CID
02 circuit 5.2 determines a window lasting between "11" and "100"
03 unit intervals, following the initial instant, and so on the
04 CID circuit 5.X determining a window lasting between (X+l) to
05 10X unit intervals. The DIC circuits 5.1 to 5.X each have a
06 state output which is in the enable state, when a counting
07 impulse is applied to the counter during the first counting
08 cycle following a resetting to zero by circuit 6 or circuit 9.
09 In practice, as an example, the CID 5.1 circuit, Figure 5, is
composed of a decade counter 19, of a D flip-flop 20 whose H
11 input is connected to the counting input "1" of 19 and whose D
12 input is connected to the Q output of an RS flip-flop 21 whose
13 S input is connected to the carry output of 19 and whose R
14 input is connected to the output of an OR gate 38 one input of
which is connected to the output of 6 and the other to the
16 output of 9. The signal input of 19 is connected to the time
17 base 3. The CLR input of 19 is connected to the output of 38.
18 The validation circuits 10.1 to 10.X each consis~ of
19 AND circuits one input of which is connected to the output of
circuit 2 and the other input to the corresponding output of
21 circuit 5.1 to 5.X.
22 As shown in Figure 6, the circuit 111.1 is comprised
23 of a counter 22 whose signal input is connected to the output
24 of validation circuit 10.1 whose zero resetting input is
connected to the output of CLR circuit 9, whose carry output is
26 connected to the signal input of the corresponding counter 22
27 of circuit 112.1, whose counting outputs are connected to the
28 corresponding inputs of a memory 23 and whose transfer control
29 input is connected to the output of a transfer circuit 8. The
outputs of memory 23 are connected to the corresponding inputs
31 of the corresponding multiplexer. Of course, the other
32 circuits 111.2 to 11X.l are each comprised of a counter 22
33 and a memory 23. For all the circuits 111.1 to 11X.l, the
34 signal inputs of counters 22 are respectively connected to the
outputs of the corresponding validation circuits. For the
36 other circuits 112.1 to llX.l, the signal inputs of counters
37 22 are respectivelly connected to the carry outputs of counters
38 22 of the circuits in the adjacent inferior row.
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01 As shown in Figure 2, the set 11 is made up of a
02 triangular matrix of circuits, in which there are X circuits in
03 the first row, (X-l) circuits in the second row, ... , and 1
04 circuit in row X.
05 Each counter 22 counts up to 10, such that the counters
06 22 in one column of the matrix of Figure 2 form a cascade of
07 dividers by 10. Each memory 23 is constituted by four D type
08 flip-flops. The signal outputs of counters 22 are obviously
09 four in number in order to binary code a number between 0 and
9. The transfer of the count contained in a counter 22 to its
11 associated memory 23 is carried out at each impulse transmitted
12 by circuit 8. The counts thus transferred remain stored in the
13 memories 23 until the following transfer command.
14 The inhibit circuit 7 is a flip-flop which is set to
the rest state by the output of the CLR circuit. As soon as an
16 event signal is generated by the circuit 2, the flip-flop 7 is
17 set to the on state.
18 The inhibit circuit 7 may be an RS flip-flop 24, Figure
19 7, whose R input is connected to the output of CLR circuit 9
and whose S input is connected to the output of circuit 2. As
21 soon as an event signal is generated by circuit 2, the Q output
22 of flip-flop 23 is activated.
23 The recording control circuit 15, Figure 7, is
24 comprised of an AND gate 25, one input of which is connected to
the Q output of flip-flop 24 and the other input to the output
26 of CLR circuit 9. The output of AND gate 25 is connected to
27 the zero resetting input of a timing circuit 26 which is made
28 up of a counter whose outputs control the connections of
29 multiplexers 12.1 to 12.X. The counting input of counter 26 ls
connected to the output of a time base 27 whose frequency is
31 chosen as a function the characteristics of the recording
32 instrument. The output of AND gate 25 is again connected to
33 the S input of an RS flip-flop 28 whose R input is connected to
34 the last output X of counter 26.
The detection circuit 14 is an OR gate whose inputs are
36 respectively connected to the outputs of multiplexers 12.1 to
37 12.X.
38 The inhibit circuit 16 is comprised of an AND gate 29
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01 of which one input is connected to the Q output of flip-flop 28
02 and the other input to the output of OR gate 14. It is
03 comprised also of an RS flip-flop 30 whose S input is connected
04 to the output of AND gate 29 and whose R input is connected to
05 the output of time base 27. 'rhe Q output of flip-flop 30 is
06 connected to the control input of recording instrument 13.
07 We shall first describe the operation of the circuits
08 concerned with the recording per se. We assume that a transfer
09 command has been sent by circuit 8, which brings about, in each
memory 23 of a validation circuit, the transfer of counter 22
11 into that memory. A bit later, the CLR circuit 9 transmits a
12 signal which resets the counter 22 and, in other respects,
13 triggers the operation of the timer 26 in circuit 15 via gate
14 25, the flip-flop 24 having presumably been set to the enable
state earlier. 'rhe circuit 26 forces the operation of
16 multiplexers 12.1 to 12.X, which start by connecting the
17 circuit lll.X to instrument 13. If the content of lll.X is
18 not zero, the OR gate 14 allows the flow of a non-zero signal
19 which actuates flip-flop 30, via AND gate 29 whose other input
is activated by 25 through 28. The Q output of flip-flop 30
21 commands the recording of the actual contents of memory 23 of
22 111 .X into 13 via 12.1. At the next impulse from time base
23 27, flip-flop 30 is reset and the multiplexers 12.1 and 12.2
24 connect the circuits lll.(X-l) and 112.(X-l). If the
contents of the memories of these circuits are not simultaneous
26 zero, gate 14 activates 30 and recording continues as
27 previously. 'rhe sequence of recording phases is continued as
28 such until multiplexers 12.1 to 12.X connect circuits 111.1
29 to llX.l. If, in one of the phases, all the memories 23 in
one column are empty, the OR gate 14 does not cause flip-flop
31 30 to change state such that recording is inhibited and the
32 printer of circuit 13 does not advance. When the counter of 26
33 has reached count X, the flip-flop 2~3 is reset which, one
34 instant later, inhibits recording. 'rhe time of Elip-flop 28 is
long enough to cover the recording operation of the contents of
36 the memories into 13.
37 In other respects, if in a time in-terval given by timer
38 4, no event signal has been generated by 2, flip-flop 24 of 7
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01 remains at rest, which preven-ts the triggering of circuit 15.
02 We shall now, by referring to the timing diagrams of
03 Figures 3A to 3G, illustrate how the events are accounted for
04 in counters 22 of circuits 111.1 to lll.X. In Figure 3A,
05 we have shown the impulses generated by time base 3. In Figure
06 3B, we have shown the impulses generated by timer 4, these
07 impulses defining, among other things, the counting starting
08 times. In Figure 3C, we have shown a sequence of signals
09 generated by circuit 2, that is to say signals which reflect
applied events, in the form of electrical signals, to the
11 apparatus of the invention. Figure 3C illustrates a single
12 event 32 generated 6 unit intervals after the first impulse 31,
13 Figure 3B, the unit intervals being defined by the interval
14 between the impulses of Figure 3A, and a group of events 33, 34
and 35 generated for 200 unit intervals and separated one from
16 the other by a single unit interval, and an event 36 generated
17 8000 unit intervals after 35 and finally a last event 37 before
18 the next impulse 31 and generated 13 unit intervals after 36.
19 When 32 occurs, the counter 19 of CID 5.1 has not yet
overflowed, therefore flip-flop 30 is set which entails the
21 flow of 32 through the AND gate of 10.1 to the counter 22 of
22 111.1.
23 When 33 occurs, the counter 19 of CID 5.3 has not
24 overflowed yet, however those of CID 5.1 and 5.2 have.
Therefore we have a count in counter 22 of 111.3.
26 When 34 occurs, at the next unit interval 33, the
27 counters 19 have been reset to zero such that flip-flop 20 of
28 CID 5.1 is once again set by the arrival of 34 and the counter
29 22 of 111.1 is incremented. The same occurs with the arrival
of 35.
31 When 36 occurs, the count of counter 22 of 111.4 is
32 increased by one unit.
33 When 37 occurs, the count of counter 22 of 111.2 is
34 increased by one unit.
We therefore have in counters 22 of 111.1 to 111.4,
36 the respective counts: "3", "1", "1", "1". As we mentioned
37 above, the counting and memory circuits are arranged in columns
38 and the counters 22 have a capacity of 10, which allows, by the
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01intermediate of multiplexers 12.1 to 12.X, the obtaining of
02direct decimal writing by column.
03A recording by instrument 13 thus appears in the
04following form:
05 0
06 03
07 154
08 0010
09 25312
10 003427
111032470
1200000420
13 _ 9 _
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