Note : Les descriptions sont présentées dans la langue officielle dans laquelle elles ont été soumises.
`` 1175507
BACKGROUND OF THE INVENTION
Field of the invention: The invention relates in
general to the operation of phase locked loop employing aided
frequency acquisition. This application relates to my other
application "DIGITAL PffASE/FREQUENCY LOCKED LOOP" filed June
15, 1982 in Canada with Pat. No. 1153795.
Descri~tion of the Prior Art: For a fast frequency
pull-in phase locked loop, a number of aided frequency
acquisition techniques including frequency sweeping, frequency
discriminators, and bandwidth-widening methods have been
mentioned in a text n Phaselock Techniques" by Floyd M. Gardner.
A digital sweeping circuit is also mentioned in IEEE Trans. on
Inst. & J,Ieans. dated Sept., 1982 with title named ~a phase-
stablized local-oscillator" by T. L. Landecker. Another
similar circuit is also disclosed in Can. Pat. 1012619 by
Apple, G. G. Frequency sweeping's speed depends heavily on
the loop's bandwidth and thus is limited. Furthermore,
Landecker's circuit applied a voltage comparator after the
loop filter of which a phase step can trigger a false sweeping.
In my other patent (Can. Pat. 1153795) filed June, 1982, I
have disclosed a digital phase/frequency locked loop with a
fast acquisition and low noise output. I have stated that the
normal phase difference needs not be a zero degree at steady
state unless the voltage controlled oscillator is adjusted.
Therefore, it is an object of this invention to provide a loop
3. with a fast acquisition, low noise and also able to be locked
phase error zero without voltage controlled oscillator adjustment.
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SUi~lr~RY OF THE INVENTION
According to the invention, a phase locked loop
is disclosed. This phase locked loop's frequency acquisition
is aided by a digital frequency comparator. During steady
state, the digital frequency comparator is f~ozen i and a D.C.
signal outputed from the comparator representing the approximate
control voltage of the required frequency is applied to the
voltage controlled oscillator. The error signal outputed from
the phase detector is used to compensate the phase error and
any slight frequency offset. Because of this, the amplitude
of error ripple signal is very low and causes the intermodula-
tion of the voltage controlled oscillator to be minimum. In
addition, there is a frequency monitor circuit to determine
when another frequency acquisition is required (due to start-
up or a certain level change of input frequency). This circuit
senses the input frequency amplitude and is less affected by
any phase step.
Brief DescriPtion of ~rawin~s
Figure 1 is a block diagram of the preferred
embodiment of the frequency guided phase lcoked loop of the
invention,
Figure 2 is a schematic diagram of a representative
implementation of the frequency monitor shown is figure 1, and
Figure 3 is a schematic diagram of a representative
implementation of the digital frequency comparator shown in
figure 1.
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Detailed Description of the Figures
The preferred embodiment of the frequency guided
phase locked loop of the invention is shown in figure 1. An
input signal source is applied at an input terminal 10. The
signal source can be any sine wave or square wave source which
requires phase locking to. The input signal at terminal 10
is applied to an input of phase detector 12 and an input of
hard limiter 13 via line 11. The output of the phase detector
12 which is the phase error signal is connected to input of a
low pass filter 19 through resistor 15. The output of the low
pass filter 19 is connected to one input of a voltage summing
device 25 through resistor 21. The output of summing device
25 is connected to input of voltage controlled oscillator 27.
The output frequency source of voltage controlled oscillator
27 is connected to input of hard limiter 29 and one input of
phase detector 12 via line 28. The digital output of the hard
limiter 29 is connected to one input of AND gate 33 via line
31. The digital output of hard limiter 13 is also connected
to one input of AND gate 32 and input of frequency monitor 38.
The output of frequency monitor 38 which indicates the valid
period of acquisition is connected to inputs of AND gates 32
and 33, switches 40 and 41. Switches 40 and 41 may be a type
of analog switch or relay. Outputs from AND gates 32 and 33
are connected to corresponding inputs of digital frequency
comparator 36 via lines 34 and 35. The output of the digital
frequency comparator 36 is connected to other input of summing
device 25 via line 37.
In operation, input signal, which can be generated
by an oscillator or derived from another source which is to
be locked, is applied at input terminal 10. It is then compared
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with the feedback signal from voltage controlled oscillatror
28 by phase detector 12 to produce a phase error signal on line
14. On the other hand, the input signal is also limited to a
digital level signal and received by a frequency monitor 38.
The operation of frequency monitor 38 will be described in more
detail later. However, it functions to sense any certain
level change of frequency and provides a pulse output indicating
frequency acquisition required. During this pulse valid period,
the digital frequency comparator 36 is enabled by AND gates 32
and 33 to have input signal and feedback signal inputing and
thus permitted to navigate (self-acquisition) the new control
signal representing the approximate input signal's frequency
at line 37. The operation of the digital frequency comparator
36 will be described in more detail later. At the same time,
switches 40 and 41 are activated. Thus input to the low pass
filter 19 and one input of summing device 25 are grounded.
Resistors 15 are 21 are lov.r value ones used just to prevent
any shorting of the detector's and low pass filter's outputs.
As a result, the system behaves as a frequency locked loop
with fast acquisition. When the pulse generated by frequency
monitor 38 is low again assuming the frequency acquisition
completed, inputs to digital frequency comparator 36 are disabled
and switches 40 and 41 are deactivated. The output of digital
frequency comparator 36 is frozen to the last latched value.
The detected phase error signal from phase detector 12 is now
connected to input of low pass filter 19. The filtered error
signal from low pass filter 19 output is applied to the input
of summing device 25. The summation of this filtered signal
and the D.C. signal latched by the digital frequency comparator
36 is produced at the output of summing device 25 to control
the voltage controlled oscillator 27. As this time, the error
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signal from phase detector 12 is used to compensate the phase
acquisition and any slight offset in frequency. And after the
phase signal is locked in, there will be a low level D.C. signal
superim~osed with a very low ripple signal outputed from low
pass filter 19. Thus the output of voltage controlled
oscillator 27 is very stable, low drift and low noise frequency
source ~hich has an almost zero degree phase error ~ith the
input signal.
Contra to conventional discriminator aided frequ-
ency acquisition circuit, the invention provides a means to
disable the phase detector output during frequency acquisition.
During the frequency acquisition, the phase detector 12 may
have passed many times of cycle slipings which generates a
wrong compensation signal. This signal contains a beat-note
A.C. signal which cannot be filtered completely by the low
pass filter (especially a second-order loop with high damping
factor). It counteracts with the output from the frequency
comparator 36 and actually slows the acquisition time. Furth-
ermore, due to the nature of digital frequency comparator
applied in this invention, it provides an optimal time and
frequency deviation during acquisition which can be hardly
achieved by conventional analog integrator.
Now turning to figure 2, a preferred embodiment of
a frequency monitor is described. The digital level of the
input signal is received at line 30 and is applied to clock
inputs of synchronous counter 100, flip-flop 116 and NOR gate
111. Several most significant bits output of the counter 100
are connected to inputs of subtractor 104 and latch 102. The
parallel outputs of latch 102 are connected to other inputs of
subtractor 104. The diffference outputs of the subtractor 104
except the least significant bit are connected to inputs of
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OR gate 107. All the difference outputs of the subtractor 104
are connected to inputs of NAND gate 108. The outputs of OR
gate 107 and NAND gate 108 are connected to two inputs of NAI~
gate 109. The structure of connected subtractor 104, OR gate
107, NAND gate 108 and NAI~ gate 109 is an absolute relative
difference detector 106. The Q output of flip-flop 116 is
connected to one input of NAND gate 109 ~hich indicates the
sampling period. The output of NAI~D gate 109 is lo-~ if the
absolute relative difference of inpv.ts to subtractor 104 is
more than one.
A fixed local oscillator source 119 produces a
frequency output and its duty cycle represents the gating
period of counter 100. The leading edge of the clock signal
from local oscillator 119 is received by the clock input of
flip-flop 11~ via line 120 and causes fli~-flop 114 set. The
D input and S input of flip-flop 114 are co~lected to a logic
high source ?U. The Q output of flip-flop 114 is connected to
D input of flip-flop 116. The Q output of flip-flop 116 is
connected to one input of NAND gate 109. The Q output of flip-
flop 116 is connected to R input of flip-flop 114 and SR
synchronous reset input of counter 100. S and R inputs ol
flip-flop 116 are connected to logic high source ~U. nip-
~lops 114 and 116 are connected as a s~chronous latch to
synchonize the leading edge signal from local oscillator 119
by the input digital source at line 3G. The output of NAND
gate 109 is connected to one input of NOR gate 111. The
input signal at line 30 is also fed to another input of NOR
gate 111. The output of NOR gate 111 is connected to clock
input of latch 102 so as to clock the most significant bits
output of counter 100 into latch 102 and is also connected
to a trigger input of
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a retriggerable monostable multivibrator 113 so as to
generate a pulse output at line 39.
In operation, the input signal one line 30 counts up
the synchronous counter 100 and reset indirectly by the leadin~
edge of local oscillator 119 sov.rce. Normally, the loczl
oscillator's frequency s'nould be much lower than input signal
at line 30 so as to allov~ the counter 100 accumlating enough
count value each period and the counter 100 is permitted to
overflo~!~ counting also. Near the end of counting period, a
pulse of input signal clock width is generated at Q output of
synchronous flip-flop 116 due to the triggering of a positive
edge of local oscillator 119 output. This high level pulse is
applied to one in~u.t of I~Al~ gate 109 and enables the result
Oî the absolute relative difference detector 106 at the output
of I~i~1D gate 109. Then it is further gated with the input
signal at NOR gate 111. Thus if the absolute relative differ-
ence calculated is more than one, a second half inpv.t clock
period of high level pulse is generated at the output of I~JOR
gate 111. This high level pulse triggers the one-shot 113
generating a pre-determined pulse period output and cloc~s
the most significant bits output of counter 100 into latch 102.
The duration of pulse generate~ by one-shot 113 normally
represents the maximu~m time of frequency acquisition ~hich
relates to the input signal's frequency, gain of digital
freqv.ency co~arator 36 and gain of voltage controlled oscill-
ator 27 in figure 1.
As a result, the circuit measvres the input signal's
frequency for a period of time provided by the local oscillato~
119. The cou~t result is proviaed at the output of counter 10-~.
At the end of counting period, upper ~ost significant bits are
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compared with ones latched before at the output of latch 102.
The lower significant bits of counter 100 are not sensed for
providing a frequency threshold. The absolute relative diff-
erence detector 106 provides a means comparing outputs from
counter 100 and latch 102 to have a difference more than one
(thus eliminating roll-over of a count problem). The threshold
frequency range relates to the gain of digital frequency
comparator 36, gain of voltage controlled oscillator 27 and
normally should be less than the lock-in range of phase
detector 12 in figure 1. At steady state, the average frequ-
ency of the input signal at line 30 should be stable. Thus
for each period of measurement, the output of synchronous
counter 100 should be same or only with a slight difference
as before. The absolute relative difference detector 106
output at NAND gate 109 should be low all the time and no
pulse should be generated at the output of one-shot 113. If
there is a certain large change of frequency of during start-
up, the output of the absolute relative difference detector 106
senses the change and provides a high signal at NAND gate 109
output during sampling period. The ne~! count output of counter
100 is latched by latch 102 and the one-shot 113 is triggered.
Not~ turning to figure 3, a digital frequency co~pa-
rator 36 is disclosed. It is basically frequency/phase
detector disclosed in my other Canadian patent number 1153795.
It provides a linear detection of frequency difference over a
very broad range and a defined limited state for the non-linear
region. The data D and S terminals of flip flop 200 and 209
are connected to a logic high source PU. The Q output of flip
flop 200 through a delay device 201, the output of AND gate 208
and the output of NAND gate 20~ are connected to correspondinng
inputs of NAND gate 202. Delay device 201 is used to guarantee
the low pulse width of the NAND gate 202
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output. The out ut of NAI~D gate 202 is connected to count-up
C`~ input of up-down counter 221, an input of NAND gate 204 and
an input of AND gate 205. The output of AI~ gate 205 is con-
nected to ~ terminal of flip-flop 200. The Q output of ~li-
flop 20? through a delay device 210, the output of AI~ gate
208 and the output of NAI~ gate 213 are connected to crrresp-
onding inputs of I"~AI"~ gate 211. Delay device 210, is used to
guarantee the low pulse width of the I~AND gate 211 output.
The output of NAND gate 211 is connected to count-dwon CD input
of up-down counter 221, ar. input of Ai~D gate 214, and an input
of NAii~ gate 213. The output of AND 21L~ is connected to R
terminal of flip-flop 20~. Furthermore, the outputs of NAI~rD
gates 204 and 213 are connected to inputs of OR gate 206. The
outpvt ol OR gate 206 is connected to one input and the other
through delay device 20, of AND gate 208. The out ut of AI~
gate 20~ is connected to inputs of NA~ gates 202,211 and A~
gates 205, 214. All pre-set inputs of up-douTn counter 220 are
connected to a logic high source PU. The parallel outputs of
up-down counter 220 are connected to corresponding inputs of
a digital to analog converter 224. Digital to analog converter
224 is a type with current integration built-in and a voltage
output source is provided at line 37. The borrow B output of
up-do~.Tn counter 220 is connected to its reset I~ input through
an inverter 222. The carry C output of up-down counter 220
is connected to its pre-set enable ~E input.
In operation, assuming that a positive edge appears
at line 34, causing the Q output of flip-flop 200 to go high,
if there is simultaneously a low level on the Q output from
NAI~ gate 202 after delayed by delay device 201. Due to the
low level of NAI~ gate 202 output, the flip flop 200 is reset
through Al~D gate 20~. The low level Q output of flip-flop 200
delayed by delay device 201 causes NAI~ gate 202 high again.
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Thus a narrow low level ?ulse is generated at the output of
NAI\~ gate 202. This low level pulse is applied to the count-up
input CU of the up-down counter 221 via line 203 and causes
the up-dot~ co-mter 221 to count up by one count.
Sir.ilarly, the presence of a ~eedback positive edge
appears on signal path 35, cavsing the Q ovtut of flin-flo
209 to go high. If there is simulaneously a low level on the
Q output of ~lip-flop 200, there will be a low level output
fro~n NAI~ gate 211. Due to the low level of NAI~ gate 211
ovtput, the flip-flop 209 is reset via AI~ gate 107. The low
level Q output of flip-flop 209, delayed by delay device 210,
will set output of NAI~ gate 211 high again. Thus a narrow
low level pulse is generated at the output of NAND gate 211.
This lo:- level pulse is applied to the count-do~ input C3 of
the up-down counter via line 212.
If a positive edge is applied to fli~-flop 209 on
line 35 slightly later than one applied to flip-flop 200 on
line 34, either the Q output of flip-flop 200 is high or the
output of NAND gate 202 is low. In either case, one input o~
NAT~D gate 211 ~ill be low so that its output is held high.
Flip-flop 20~ will latch the high signal unt-l the output of
NAr~ gate 202 is high, at which time its output goes low,
flip-flop 209 is reset, etc. as before. Similarly, if a
positive going pulse edge is applied to flip-flop 200 slightly
later than one applied to flip-flop 209 on line 35, one
input of NAI~D gate 202 will be low so that its output is held
high. Flip-flop 200 will latch the high signal until the output
of NAr~D gate 211 is high again to enable NAI~ gate 202, at which
time its output goes low, flip-flop 200 is reset,etc.
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~f positive going pulse edges arrive at flip flop
20Q and 209 at almost the same time, the outputs of NAND gates
204 and 213 could both go low which would rrean a deadlock
condition. This condition is sensed by OR gate 206 which,
with both inputs low, produces a low output. This low level
signal is applied to reset flip flop 200 and 209 through AND
gates 208, 205 and 214. Delay device 207 is used to provide
temporary disable of any illegal low pulse generated at the
output of NAND gate 202 or 211 which is due to reset timing
offset of flip flops 200 and 209 during the time that OR gate
206 output resetting action is in progress.
It has been found that the invention described
above operates as a frequency and phase comparator, of a type
which does not lock to harmonics of the input signal. Various
other modifications may be apparent without departing from
the spirit of the invention. One major obvious example is to
stablize a high gain voltage controlled oscillator with a
stable reference source input (such as crystal oscillator).
At that moment, the deviation of frequency is mainly due to
the output source. Thus the input frequency monitor circuit
should monitor the voltage controlled oscillator's output. Any
out of lock or locked to harmonic case can be sensed. Similarly,
if the input signal source's frequency is very low compared
with the local source in the frequency monitor, the input
signal's cycle can be used as gating period of the counter
and the local clock source as the counting clock pulse.
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