Note : Les descriptions sont présentées dans la langue officielle dans laquelle elles ont été soumises.
~3¢ '3'76
UK9-79-018
MOTOR CONTROL SYSTEM FOR A SINGLE PHASE INDUCTION MOTOR
Technical Field of the Invention
The present invention relates to motor control systems
for controlling a single phase induc~ion motor.
Bac~round of_the Invention
A single phase induction motor comprises essentially a
wound annular laminated stator, which is energized by a
single phase a.c. supply, and a shorted rotor of ~he cage
type in which voltages are induced by the variation of pri-
mary voltage in the stator winding. The application ofsingle phase a.c. to the stator run winding creates an oscil-
lating magnetic field which provides a torque to drive the
motor once it is rotating. Howevex, the oscillating field
alone will not start the motor. In order to start this type
of motor an auxiliary or start winding is provided which is
spatially displaced around the stator from the run winding.
The supply voltage is applied to both windings but is time
phase shifted in the start winding. This phase shift causes
a rotating rather than an oscillating field to be produced,
which is sufficient to cause the rotor to turn.
Many ways of effecting this phase shift are known, the
simplest being to make the run and start windings of
different inductance. This is the so~called "split-phase~
motor. Another equally common technique is to employ a phase
shiEting capacitor which allows a more efficient 90 phase
shift to be introduced. The start winding is switched out of
circuit when the motor is rotating so that the motor runs
solely on the single phase a.c. supplied to the run winding.
This aspect of single phase motor operation is very well
)3~
UK9 79-018 2
known and is discussed in various books on the subject (eg
Chapter 7 of "Electric Motors Handbook", McGraw-Hill Book
Company, 1978).
A single phase supply motor which is not only started
but also run as a two-phase motor by a somewhat different
method is shown in UK Patent 146~454 As with conventional
single phase motors, two spatially displaced windings are
provided on the stator one of which is supplied dirPctly with
a.c. The other winding is centre tapped and each half of
this winding may be supplied with rectified mains voltage via
a respective thyristor. A gating circuit switches the thy-
ristors alternately at predetermined points in the mains
cycle so that the second winding is enexgized with an alter-
nating, though not sinusoidal, voltage which is phase shifted
from the mains by a fixed amount. Because of the phase shift
a rotating field is produced which starts the motor. In this
case the two phase arrangement is also used to run the motor
as well.
In many applications, the a.c~ supply to the run winding
of a single phase induction motor is not provided directly
from the mains but is provided electronically from, say, an
inverter. UK patent 1347191 shows such a system and points
out that under constant speed and constant load running con-
ditions, the power required to run such a motor is often very
much less than that which is needed for starting. This means
that the inverter must be designed to provide starting
currents very much in excess of those needed during running.
The patent proposes the use of a.c. mains to supply the high
currents needed during starting after which the motor is
switched to the electronically generated a.c. supply for
running. The generated a.c. is synchronized with the mains
prior to switchover. In this way the generating circuit (in-
verter) need only be designed for running conditions.
)3~7ki
UK9-79-018 3
A similar arrangement to that of UK patent 1347191 is
decribed in an article by R C Treseder entitled "Coaxial
Drive for Magnetic Disk File" (IBM Technical Disclosure Bul-
letin, Volume 23, No 3~ August lg80, page 1198) which shows a
four pole three phase induction motor for driving a magnetic
disk file. The optimum supply frequency for the operating
speed of the disk file i5 120 Hæ which is provided to the
motor by an oscillator driven three phase power amplifier.
To provide higher starting torque than would be available
' ` lO from the 120 Hz generated supply, the motor is started by
connection to three phase a.c. mains. ~hen the motor has
reached its mains synchronous speed, which is sufficient for -
the heads to fly, the mains is disconnected and the 120 Hz
supply switched to drive motor.
Disclosure_of the Invention
Thus the prior art has recognised the benefits of mains
starting and electronically driven running for a.c. induction
motors in certain applications. Considering further the
example of a magnetic disk file in which normally flying
transducer heads start and stop in contact with the disks, a
- high starting torque is essential to achieve the minimum
flying speed as soon as possible thus minimising wear on the
disks. This high starting torque can best be provided by the
mains. To maximise the starting torque with a mains supply a
four pole motor is desirable. This is because the
synchronous speed of an induction motor is determined by the
number of poles and by the supply of frequency and the
maximum torque is attained at a speed just below synchronous
speed. In the case of a mains frequency four pole motor the
synchronous speed is 1500 r.p.m. at 50 Hz and 1800 r.p.m. at
60-Hz which speeds are sufficient for the heads to fly.
;3~
UK9-79-018 4
The torque/speed characteristics of induction motors are
such that the torque, after reaching a maximum just below the
synchronous speed, then falls sharply to zero at the syn-
chronous speed. The typical operating speed of a magnetic
disk file is around 3000 r.p.m. and cannot, therefore, be
reached by continuing to run the motor with the mains
frequency torque/speed characteristic which is employed to
start it. If the frequency of the supply is approximately
doubled, howeYer, the synchronous speed is doubled and the
10 motor can attain the necessary operating speed.
Once the heads are flying, high acceleration is no
longer required to reach operating speed. Also, once at
operating speed, the load remains constant and the running
power is relatively low. Thus, an electronics (inverter)
supply at twice mains frequency need only provide about one
tenth of the power required during starting to complete the
accelera~ion and run the motor. The lower power requirement
and the doubled frequency also have the advantage that the
motor runs in a relatively defluxed state thereby signi-
ficantly reducing vibration.
- The system proposed in the Treseder article, referenced
above, appeaxs capable of offering some of these advantages
but shows a three phase motor which necessarily requires a
three phase mains supply and a three phase inverter supply.
Three phase mains supplies are rarely available and three
phase motors and inverters are more complex than single
phase. The system would be considerably simpler and cheaper
if a single phase induction motor could be used requiring
only a single phase mains supply and a single phase inverter.
This is achieved in combination with an economic
starting technique for a single phase induction motor accor-
3 1'~
UK9-79~018
d`ing to ~he present invention which provides a motor control
sys~em for controlling a single phase induction motor having
a cage rotor and a stator with first and second windings
spatially displaced in phase from each other, the system com-
prising sequencing means for sequentially indicating stagesof motor operation including an initial start s~age, a switch-
able mains connecting means arranged to connect single phase
alternating mains voltage to the first stator winding during
the start stage and to disconnect the mains voltage from the
, ~ lO first winding at the end of the start stage , a driver
circuit responsive to a periodic drive control signal to
apply a correspondingly alternating voltage to the second
stator winding, and drive control signal generating means for
providing such a periodic drive control signal to the driver
circuit both during and after the start stage, the drive con-
trol signal having, during the start stage, a fixed phase
shift with respect to the mains voltage so that a rotating
magnetic fiela is created to start the motor.
By employing the alternating single phase voltage from
the driver circuit not only to run the motor after the start
stage but also to provide an out of phase voltage to the
second stator winding during the start stage, the need for
additional phase shifting components such as capacitors is
avoidedO Furthermore, the need for the second winding to be
balanced with the first and to carry mains current is
removed. Instead the second winding can be optimized for run
conditions (e.g. number of turns and wire diameter) rather
than have to be a compromise between start and run con-
ditions.
Preferably the drive control signal generating means is
arranged to increase the frequency of the drive control sig-
nal subsequently to the start stage allowing advantage to be
'376
UK9-79-018 6
taken of the altered torque/speed characteristics which
result from the frequency increase. The frequency can be
increased in ramp fashionO
The drive control signal generating means can advan-
tageously includes mains sensing means for deriving a firstdrive control signal from the mains voltage, and a variable
frequency signal source for generating a second drive control
signal of variable frequency, the system further cGmprising
'.~ switchable connecting means responsive to indications from
the sequencing means to connect the first drive control sig-
nals to the driver circuit during the start stage and to
connect the second drive control signals to the driver cir-
cuit subsequently to the s~art stage.
Another preferred feature of the invention is that the
driver circuit power output is limited so that the major pro-
portion of power to the motor during the start stage is pro-
vided by the mains. The drive circuit only has to provide
enough power during starting to get the motor to turn. It is
not necessary that the drive to the run and start windings be
balanced during the start stage. Thus the driver circuit can
be designed to provide only the relatively low power consumed
during running. The limitation of driver circuit power is
preferably achieved by limiting the current through a power
amplifying device in the circuit. This may be done by gating
off the power amplifying device whenever a predetermined cur-
rent is exceeded.
Another preferred feature of the invention is that the
drive control signals should be square waves, the driver cir-
cuit being a switched bridge driver responsive to the sense
of the drive control signals to connect a voltage of a res-
pective polarity across the second stator winding. This
;3'76
~K9-79-018 7
arrangement has the advantage that a sinusoidal waveform does
not ~ave to be provided and the motor will start and run with
a simple square wave drive from the electronic supply.
_ ief Description of the Drawings
The invention will now be described, by way of example
only, with reference to a preferred embodiment thereof as
illustrated in the drawings, in which:~
-
Figure 1 is a schematic block diagram of a motor control
system according to the present invention;
Figure 2 shows a start driver circuit employed in the
system of Figure 1;
Figure 3 shows a run driver circuit employed in the sys-
tem of Figure 1;
Figure 4 shows a counter buffer forming part of a con-
trol circuit employed in the system of Figure 1;
Figure 5 shows a se~uence controller and other details
of the same control circuit employed in Figure 1;
Figure 6 shows various waveforms occurring in the system
of Figure 1 and circuits of Figures 4 and 5;
Figuxe 7 shows a monitor circuit employed in the system
of Figure 1; and
Figure 8 shows an error latch portion of the control
circuit employed in Figure 1.
3~
UK9-79 018 8
Detailed Descri~tion of the Inv~ntion
In Figure 1 is shown a single phase four pole induction
motor 10 and an associated motor control system. The motor
10 consists of a squirrel cage rotor 11, illustrated sche~
matically, and a wound laminated stator (not shown~
surrounding the rotor and spaced from it by a small air gap.
The windings with which the present invention is con-
cerned are primarily a start winding 13 and a run winding
14. Also provided is a brake winding 15 for braking the
motor. A brake circuit 16 applies d.c. braking current to
the winding 16 in response ~o an input command n -BR~KE n . The
brake circuit is not relevant to the present invention and
thus will not be further described.
A voltage regulator 20 supplies a regulated d.c. voltage
derived from the mains both to the brake circuit 16 and to a
run driver circuit 21 which provides alternating drive
current to tne run winding 14. The run winding is energised,
initially, to help start the mo~or and, subsequently, to keep
it running during normal operation in accordance with the
disclosed invention.
A.C. mains voltage is supplied directly to a start
driver circuit 22 connected to the start winding 13. The
start winding is energised initially by mains voltage and
provides the bulk of the power necessary to bring the motor
up to a minimum operating speed. After the motor reaches
this minimum speed the start winding is disconnected and the
motor continues to accelerate to its final operating speed
under the action of the run winding alone~
~ 9~ 7
UK9 79-018 9
The Start driver circuit 22 is shown in Figure 2
together with the start winding 13. The circuit simply com-
prises a triac 60 for switching mains a.cO through the start
winding. Gating signals for the triac 60 are produced by a
gated oscillator 61 (e.g. a Texas Instruments type 555) in
response to a control signal -START WINDIN~ going low. The
gating signals, which are of a frequency of 10 KHz, are
inver~ed and then amplified in a transistor 62 which supplies
them to the primary of a pulse transformer 63. The resulting
pulses in the transformer secondary all trigger the triac to
pass the applied mains a.c. to start winding 13. If the
signal -START WINDING goes high the oscillator is gated off
and the triac 60 is no longer triggered thus preventing
further energisation of start winding 13.
The run driver circuit 21 together with the run winding
14 is shown in Figure 3. Essentially the winding 14 is con-
nected in a half bridge arrangement between Darlington power
transistors 70 and 71 and reservoir capacitors 72 and 73.
The d.c. power supply across the bridge is obtained from vol-
tage regulator 20 and is applied across terminals 74 and 75.
Antiphase periodic drive control signals -DRIVE 1 and
-DRIVE 2 from a control circuit 26, Figure 1, are applied via
an opto isolator 40 to gated amplifiers 78 and 79 which pro-
vide corresponding switching currents to the bases of power
transistors 70 and 71. When transistor 70 is on transistor
71 is off and vice versaO
Motor drive current thus flows alternately in opposite
directions through the parallel combination of run winding 14
and a capacitor 80 to charge and discharge capacitors 72 and
73 in turn so that the junction between the capacitors
provides a centre tapped supply. The rate of change of vol-
tage through winding 14 is limited by capacitor 80.
'7~-J
uKs-79-al~ 1 o
The current through each of the transistors 70 and 71 is
sensed by means of the voltage developed across one of re-
sistors 83 and 84. This voltage is compared with a pre-
determined reference maximum allowable voltage Vre~ in one
of comparators 85 and 86. If the allowable currPnt is
exceeded the outputs of the comparators gate off their res-
pective amplifiers 78 and 79 for the duration of single shots
87 or 88. The chopping action of this gating circuit reduces
the effective r.m.s. voltage across the run winding. The
-~ lQ regulated supply applied between terminals 74 and 75 is 230
volts so that a maximum of 115 volts can be switched across
the winding 14. However, in the start stage with the motor
cold and winding resistance low the application of this vol-
tage would draw much more current through devices 70 and 71
than they can tolerate. The gating circuit prevents such
high currents being drawn and its action reduces the ef-
fective voltage across winding 14 during starting to some 40
volts. This protective action effectively limits the power
output required of the driver permitting a much simpler lower
rated driver circuit than would otherwise ~e required. The
limitatlon of power corresponds to the power required to run
the motor at operating speed.
Transistors 70 and 71 are protected against transient
overloads when the current through the winding 14 is reversed
by means of diodes 91 and 92. One function of inductances 93
and 94 is, together with capacitance 80, to limit transient
power dissipated in the transistors 70 and 71 when they are
switched. The diodes 95 and 96 together with the diodes 91
and 92 act during switching to clamp the emitter of tran-
sistor 70 to the negative rail or the collector of transistor
71 to the positive rail~ This ensures that neither tran-
sistor is ever subjected to a voltage greater than the full
line voltage.
3~6
UK9 79-018 11
Another function of inductances 93 and 94 is to give
short circuit protection to transistors 70 and 71. Thus, if
both are on as a ~esùlt of some fault the rate of rise of
current will be slow enough for amplifiers 78 and 79 to be
gated off before damage is done to the transistors.
At the heart of the motor control system of Figure 1 is
the control circuit 26 which may be loosely divided into
three sections ~7, 28 and 29 and which are described in
-~ detail in Figures 4, 5 and 8 below. The control proper is
performed by section 28 which is responsive to external
commands from a system interface at 31 such as rSTOP" and
n-START" commands. Another input to the control section 28
is a source of timing pulses at 1.2 second intervals from a
timer 32. The control section 28 primarily comprises a
sequencer for causing sequential performance of the motor
control operations necessary to start, run and stop the
motor. Various stages of motor operation are defined by cor-
responding latches within control section 28 which are set
and reset in a predefined seguence and in response to ex-
ternal commands.
The outputs of these latches are combined within controlsection 26 to provide control signals to various parts of the
motor control system, particularly the winding driver cir-
cuits 16, 21 and 22. The control section 28 also provides
outputs back to the system at interface 33 and, internally,
to the other sections 27 and 29 of the control circuit 26.
.
The control section 27 is basically a buffer between a
counter 35 and a programmable divider 36. The divider 36
receives high frequency 10.93 MHZl input signals from a
crystal oscillator 37. This high frequency is divided down
many times in the programmable divider 36 to produce an out-
3~
UR9-79-018 12
put signal "BRM INn, of freque~c~ between 55 and 100 H~,
whiCh i5 provided as an input to control section 28. The
frequency of B~M IN is detenmined by five input control lines
38 from the bufer 27 which set the division ratio of divider
36. The divider 36 actually consists of a binary rate multi-
plier (e.g~ Texas Instruments no 7497~ to which the control lines
38 are applied and two further fixed ratio dividers in
series. The counter 35 provides four variable inputs to the
buffer 27 with a fifth being generated internally. Depending
on the stage of motor operation either the five inputs are
all gated through the buffer 27 to the lines 38 or else the
lines 38 are set at predetermined values. The counter 35
itself is cleared and preloaded by two signals "CTR
CLEARnand n-CTR LD" generated within the control circuit 26
at times determined by the motor operation sequence. The
counter is incremented by a signal "CTR CLOCK" derived from
the output ~CLOCK IN" of timer 32 within the control circuit
26.
The control section 29 of circuit 26 provides diagnostic
information from a number of error latches by combining the
outputs of a monitor circuit 40, for sensing various motor
conditions, with the latch states indicating the current
stage of the motor operation sequence. This diagnostic infor-
mation is stored internally in further latches within section
29 and output either directly or via a further interface
latch buffer 41 to the system.
The operation of the motor control system of Figure 1,
in accordance with the principles of the invention, may be
followed with reference to the waveforms of Figure 6.
In response to a predetermined combination of input
commands (-START and STOP both low), the control section 28
'76
UK9-7~-013 13
o~ circuit 26 applies the signal - START WINDING (coincident
with START LATCH in Figure 6) to start driver 22 to cause
application of single phase mains a.c. to start winding 13.
The mains frequency may be either 50 or 60 Hz. The presence
of mains voltage is detected inductively by a sense winding
44.
The signal on the sense winding is phase shifted by 120
by phase shifter 45. The phase shifted signal is squared by
-~ an overdriven comparator to produce a signal "START PHASE"
`' lO which is applied to control section 28~ Because the latches
in the control section 28 indicate that the motor 11 is in
the starting stage of operation, the START PHASE sign~l is
gated through section 28 and inverted to constitute a pair of
opposite phase drive control signals -DRIVE 1, and -DRIVE 2A
These signals, which are logic signals, are converted to
power transistor switching signals in a conventional
opto-isolator 48 (for example, Texas Instruments, TIL 112)
and applied to the run driver 21. This circuit, as has been
described in Figure 3, is a switching half bridge driver
supplied with regulated d~co from voltage regulator 20. The
-DRIVE 1 and -DRIVE 2 signals cause the alternate switching
of the regulated d.c. voltage in opposite directions across
the run winding 14. The 120 phase relationship between the
drive signals and the mains voltage to the start winding is
equivalent to a 90 phase relationship between the currents
in the start and run windings. This is because the current
in the start winding lags the applied voltage by about 30.
The out of phase currents in the two windings cause a ro-
tating magnetic Eield to be created in the motor air gap
which starts the rotor turning.
~3t; 3~
U~9-79-01~ 14
Once the rotor is rotating, most of the power needed to
provide a high s~arting torque is drawn from the mains. The
out of phase signal to the run winding is primarily needed to
cause the initial movement and the con-tinued supply of out of
phase drive signals to the run winding has relatively little
effect on the starting torque. The start stage is terminated
after a prede-termined time indicated by counter 35. At this
time the mains supply is disconnected from the start winding
13 in response to a change of state of the control signal
-~ 10 -START WINDING. At this point the motor is turning at around
50~ of its final operating speed.
The motor operation now enters a ramp stage in which the
motor runs on alternating current supplied to its run winding
14 alone and the frequency of that current is increased in
ramp fashion to that corresponding to the final operating
speed.
After the start stage tenminates the control section 27
no longer derives the drive control signals -DRIVE 1 and
-DRIVE ~ from the START PHASE signal ~ut instead from the
variable frequency signal BRM IN from programmable divider
36. At the beginning of the ramp stage, the counter 35 is
loaded in reponse to the signal -CTR LOAD and counter buffer
control section 27 gates the counter output to determine the
division ratio of the programmable divider. With the counter
in a loaded state, the input lines 38 to the divider are in
the state 01111 correspondiny to a frequency of BRM IN of 55
Hz.
During the ramp stage, the counter 35 is incremented
periodically in response to pulses from timer 32 and the fre-
quency of BRM IN is increased in steps from 55 to 100 Hz
The drive signals -DRIVE 1 and -DRIVE 2 also increase corres-
V3~6
UK9-79-018 15
pondingly in frequency with the result that the motor accel-
era~es steadily to reach its operating speed at the end of
the ramp.
The ramp stage of motor operation now termin~tes and the
sequence progresses to the run stage. In this stage, the 100
Hz drive signals continue to be applied to the run winding
until the operation is terminated by the STOP external com-
mand going high or by the occurrence of a fault condition
~~ such as the "DRIVE VNSAFE" signal from diagno~tic control
section 29.
Vpon termination of the run stage the motor operation
sequence enters a braking stage in which the drive signals to
the run winding are removed and the brake winding 15 is ener-
gised via brake circuit 16 to bring the motor to rest.
The employment of the electronically generated signals
-DRIVE 1 and -DRIVE 2 to provide the out of phase starting
current, synchronized with the mains has several advantages.
3ne of these is that mains starting of a single phase in-
duction motor is achieved without the need for a large phase
shifting capacitor. Perhaps more important is that no com-
promise between start and run winding design is necessary.
The two windings do not have to be balanced and carry the
same currents but instead each may be optimized for start and
run conditions respectively. Thus the start winding is
designed for full mains voltages ranging from 180 to 260
volts r.m.s. whereas the run winding is designed for a vol-
tage range of from 40 to 115 volts r.m.s. The run winding to
start winding turns ratio is 3 to 5. If a compromise over
voltages were necessary, the run winding would need more
turns and would produce less torque and run hotter.
33~76
UK9-79-018 16
Details of counter buffer 27 and of the control portion
28 of control circuit 26 are shown in Figures 4 and 5 respec-
tively. The operation of these portions of control circuit
26 will now be explained in detail with reference to the
timing diagram of Figure 6.
Taking first the counter ~uffer of Figure 4 it can be
seen that the four outputs CTR1, CTR2, CTR4 and CTR3 (see
Figure 6) of counter 35 are applied to buffer 27 and inverted
-~~ by inverters such as 200. The four counter bit values and
~ lO ~heir inverses are made available on lines such as 201 and
202 to the control portion 28. The true counter bit values
are also applied to AND gates such as 203 so thatt if a
gating signal -FORCE BRM (Figure 6~ from control portion 28
is high, they appear as signals BRM BIT 1, 2, 4 and 8 on four
of ~he input control lines 38 (Figure 1) to the binary rate
multiplier of the programmable divider 36. If -FORCE BRM is
low all the signals BRM BIT 11 2, 4 and 8 are zero~
A fifth input line 38 carries a signal BRM BIT 16
tFigur~ 6~ which is generated by a iatch circuit whose inputs
are -CTR4 and a signal -LOAD 16 from control portion 28. The
latch is set when -CTR4 is high and reset by the -LOAD 16
signal. The latch consists of NAND 204 and inverter 205 the
outputs of which are dot OR'ed at junction 206 and inverted
by inverter 2070
The control portion 28 of circuit 26 is illustrated in
detail in Figure 5. Various waveforms and signals occurring
in the circuit portion of Figure 5 are shown in Figure 6 to
assist in explaining the operation of the circuit.
At the heart of the circuit of Figure 5 are six latches
of the Set/Reset type, each corresponding to a unique stage
3~6
UK9-79-018 17
of motor or motor control operation. The latches consist of
Test Latch 301, Start Latch 302, Ramp Latch 303, Run Latch
304, Brake Latch 305 and End Latch 306. The latches are set
and reset sequentially by input logic 310 which is a network
of logic gates responsive to the external signals shown
applied to th,e circuit 26 in Figure 1 and also to internally
generated signals from all three portions of circuit 26.
Because of the large number of gates and inputs the inter-
connections within input logic 310 have not been shown in
detail. Instead the inputs to individual gates have been
explicitly identified by name.
The output states o the latches (Q and Q), as well as
being fed back to the input logic 310, are also applied to
output logic 311. Output logic 311 is a network of logic
gates providing the various control and drive signals
emerging frGm portion 27, Figure 1, to other parts of the
motor control circuit, for example the -DRIVE 1 and ~-DRIVE 2
signals to the run driver circuit 21. As with input logic
310 not all the interconnections of the output logic 311 are
shown but instead the inputs to individual gates are ex-
plicitly identified.
Another component of the control circuit portion of
Figure 5 is a latch 312 of the Data/Clock type. In response
to signals from the gates of input logic 310, this latch, at
clock times defined by the signal CLOCK IN from timer 32,
generates RESET pulses which are fed back to the same gates
to step the latches through their sequence.
Two frequently occurring signals which are simply com-
binations of the outputs of certain latches are OPERATION,
which indicates that the motor is starting or running, and
ROTATION which indicates that i-t is starting, running or
37~
UK9-79-018 18
b~aking. An OR gate 313 produces the signal OPERATION and a
further OR gate 314 produces ROTATION.
The sequence of operation is as follows: External
control signals -START and STOP are initially high prior to
m~tor operation and are inverted and com~ined by ~IOR gate 315
to produce a signal BOTH HIGH. This signal passes through OR
gate 316 to produce a signal CLEAR which is effective to
reset all latches 301-306 and also to clear the counter 35.
Before the motor is allowed to start, a checking and
testing cycle is carried out. Firstly, the -START and STOP
signals go low consecutively. The correct operation of the
input control lines carrying these signals to interface 31 is
confinmed by the generation of two negative pulses in the
signal -SPEED GOOD which is provided to the system interface
33. The signal -SPEED GOOD, in this instance, is produced
from NOR gate 317 in response to the application of -START
and a delayed version STOP BUFF of the STOP signal to a N~ND
circuit 318. The output of the NAND 318 is applied to NOR
317 via a dot OR junction 319.
Af ter this line check operation, the -START and STOP
signals both go high again. Subsequently, both lines go low
and this is the start of the motor control operation proper.
A signal BOTH LOW is generated by NAND gate 320 and inverter
321. This signal is applied to an AND gate 325 whose other
inputs are all positive since all latches are in their reset
state. The output of AND 325 via an OR 326 generates the
first RESET pulse from latch 312. This RESET pulse is
applied to another AND gate 327 whose output sets the Test
latch 301. The other inputs to ~ND 327 indicate that no
other latch is set and that, as a result of the application
of the signal CTR CLOCK, the counter 35 has incremented from
3~
UK9-79-018 19
zero. The latter input indicating a non zero count, is pro-
vided by OR 328.
The incrementing of the counter 35 is also a result of
the same BOTH LOW signal which via OR 330 generates a signal
GATE CLOCK. This signal enables the timer clock 32 which
produces the CLOCK IN timing pulse train. The CLOCK IN
signal is inverted to produce a signal ST~OBE which in turn
is applied to an AND gate 331. In the absence of a signal
CTR STOP and providing the Run Latch is rese~, STRO~E is
` lQ gated through AND 331 and inverted to produce the signal CTR
CLOCK which increments counter 35.
The setting of the Test Latch thus indicates that the
necessary clocking signals and RESET pulses are being pro-
perly generated. Before proceeding to the Start stage of
operation, the setting of the Test latch is first used to
cause the control signals GATE DRIVE, -GATE POWER and -BRAKE
(see Figure 6) to be generated for Test purposes. These
signals are generated by three NAND gates 335, 336 and 337 if
any of the inputs to these gates go low. Two of these inputs
are provided by additional NAND gates 338 and 339 which,
while the Test latch is set, go low at counts of 1 and 2,
respectively to cause the generation of respec~ive signals by
NAND gates 335, 336 and 337. While the Test latch is set,
the other inputs to these NAND gates -OPERATION and -BRAKE
LTCH remain high. Setting of the Test latch generates the
signal -SPEED ZERO via an OR gate 340 to the systern interface
33.
When the counter 35 reaches a count of 3, the Start
latch is set upon receipt of the next Strobe pulses by an AND
gate 342. This generates a Reset pulse from latch 312 at the
reset positive clock edge. Since the Start latch is set,
76
UK9-79-018 20
QPERATIoN is now high and an AND 343 resets the Test latch.
Simultaneously, the signal -GATE POWER goes down, activating
the voltage regulator 21, and GATE DRIVE goes up to enable
passage of the signals -DRIVE 1 and -DRIVE 2 to the Run
driver 21.
Once the Start latch 302 is set, the motor is energised
as explained in connection with Figure 1. The signal -START
LTCH is buffered by inverters 344 and 345 and emerges as
-START WINDING. This enables the start driver circuit 22 to
apply mains voltage to the start winding 130
A switching circuit including AND gates 349 and 350
receives both the signals START PHASE and BRM IN as inputs.
NAND 3~9 is enabled by the Start latch to apply the START
PHASE signal to an ~ND gate 351 and its inverse to an AND
gate 352. Thus, the drive control signals -DRIVE 1 and
-DRIVE 2 are provided by the START PHASE signal during the
Start stageO When the Start latch is later reset, the signal
BRM IN constitutes the input instead. The two AND gates 351
and 352 must be enabled by GATE DRIVE and not inhibited by
diagnostic signals DRIVE UNSAFE and SENSE GOOD, the latter
being NAND'ed with START LTCH by ga~e 353.
Thus as a result o the setting of the Start latchr
mains is applied to the start winding and simultaneously
drive control signals are applied to the run driver to cause
a synchronised but out of phase energisation of the run
winding. The resulting rotating magnetic field, as explained
above, causes the rotor to begin to rotate. The high power
available from the mains and the relatively low mains fre-
quency maximise the torque to accelerate the motor as rapidly
as possible up to a minimum operating speed.
3~76
UK9-79-018 21
~ The application of mains to the start winding continues
until the Start stage of the sequence is terminated. This
happens when the counter reaches a count of 7 and the Ramp
latch 303 is set by the immediately following Strobe pulse
via an AND gate 356. This automatically generates a Reset
pulse which resets the Start latch via AND 357. As soon as
the Start latch goes down, the signal -START ~INDING is
removed from the start driver circuit 22 and the start
winding 13 is no longer energized.
Also when the Ramp latch is set the signal -FORCE BRM,
produced by OR gate 358, goes high and the programmable
divider 36 is set in accordance with the contents of the
counter 35 and the value of the BRM BIT 16. These values are
not significant until the Start latch is reset causing the
generation of signals -LOAD 16 and -CTR LOAD from inverter
359. The -LOAD 16 signal forces BRM BIT 16 low and the -CTR
LOAD signal sets all the counter 35 outputs to 1. The pro-
grammable divider 36 thus receives a control word 01111 on
lines 38 which corresponds to an output frequency of approxi-
mately 55 Hz. The frequency of drive signals -DRIVE 1 and
DRIVE 2 to the run driver is thus forced to this value at the
,- start of the frequency ramp as the controlling input is now
BRM IN to AND 350. The frequency of 55 Hz is chosen as a
compromise between the two possible mains frequencies of 50
and 60 Hz.
After the counter 35 has been loaded it is incremented
by the subsequent CTR CLOCK pulses so that the frequency of
BRM IN increases in twelve steps until it corresponds to the
final required operating frequency. This condition is indi-
cated by the setting of the Run latch 304 at a count of 12 by
way of AND gates 362 and 363. The output of AND gate 362 is
a signal CTR STOP which removes the CTR CLOCK signal by in-
~K9-79-018 22
hlbiting AND gate 331~ The counter contents are frozen and
the state of the lines 38 is fixed at 11100, corresponding to
a frequency of BRM IN of approximately 100 Hz. The setting
of Run latch 304 produces another RESET pulse to reset Ramp
latch 303 by way of AND gate 364. The motor is now running
at full operating speed and wil' continue in this state in-
definitely until the external command, STOP, goes high.
When STOP goes high, with -START remaining low, the Run
-- stage of operation is terminated. The buf fered signal STOP
BUFF causes AND 367 to generate a RESET pulse via OR 326 and
- latch 312. This pulse and STOP B~FF are applied to an AND
368 which produces a signal SET BRAKE to set the Brake latch
305 and simultaneously reset the Run latch. At the same
time, a pulse CTR CLEAR, produced by OR 368, clears the
counter 35 and -CTR STOP returns high thus freeing the
counter once again. The signal OPERATION goes low as does
GATE DRIVE, removing the drive signals from the run winding
driver circuit 21. The -BRAKE signal is produced by NAND
337, in response to the setting of the Brake latch, and
causes the operation of the brake circuit 16 which proceeds
to stop the motor by a d.c. braking technique.
After counter 35 reaches a count of 8, the braking is
complete and the End latch 306 is set by AND 370 upon receipt
of the next Strobe pulse. A final RESET pulse is generated,
via AND 370, which, applied to a further AND 371, resets the
Brake latch. The signal ROTATION produced by OR 314 goes low
and the signals GATE CLOCK, -GATE POWER and -BRAXE change
state to terminate their respective operations. Also the
signals -SPEED GOOD and --SPEED ZERO to interface 33 both go
low.
;376
UR9-79 018 23
In response to the dropping of these two signals at
interface 33, the external system subsequently raises the
external signal -START. The signal BOTH HIGH is once again
produced by OR 315 and the resulting CLEAR pulse from OR 316
clears all latches and the counter. The resetting of the End
latch is verified to the system when -SPEED GOOD is driven
high again by the output of NAND 31R.
Should the DRIVE UNSAFE signal have gone high for any
reason during the Run stage of motor operation, as indicated
by the dotted lines in Figure 6, then -SPEED GOOD rises imme-
diately as a result of an output from an AND gate 375 and
GATE DRIVE falls to remove the drive signals from driver 21.
The remaining portion 29 of control circuit 26 is shown
in Figure 8. As shown the circuit i-s simply a number of
latches, each of which captures outputs from monitor circuit
40 details of which are shown in Figure 7.
The inputs to the monitor circuit of Figure 7 are SENSE
which is the output of sense winding 44 ~Figure l), the drive
control signals - DRIVE 1 and - DRIVE 2 and the triac pulses
from Start driver 22.
Considering Figure 7 first, the SENSE signal is compared
with a predetermined voltage reference by a differential am-
plifier 501. The output of the amplifier is applied to
trigger a single shot 502 whose period is 200 m5. Providing
the SENSE voltage exceeds the threshold voltage, its
oscillations will keep the single shot 502 triggered so that
its Q output is always high. This signal is the SENSE GOOD
signal.
3'7~
UK9-79-01a 24
The Q output of single shot 502 is low as long as SENSE
GOOD is high and thus does not alter the initially cleared
state of a flip-flop 503. The Q output of flip-flop 503 is
gated with SENSE GO~D and the signal GATE DRIVE in AND gate
504 to produce a signal DRIVE ON.
The signal DRIVE ON is used to enable a further AND gate
507 to which the drive control signals DRIVE 1 and DRIVE 2
are applied. The DRIVE 1 signal is delayed slightly in delay
508 so that AND 507 produces pul~es whenever DRIVE 1 or DRIVE
2 pulses are present. The output pulses of ~ND 508 trigger a
10mS single shot 509. If drive pulses do not appear for an
interval greater than 10mS, the Q output of single shot 509
goes high and sets a flip-flop 510. The Q output of this
flip-flop is the signal -DRIVE PULSES indicating that the
drive pulses have disappeared. Another AND gate 511 will set
flip flop 510 if either DRIVE 1 or DRIVE 2 is stuck high.
A further output of the monitor circuit is the signal
-TRIAC PULSES~ This, when high, indicates the absence of
triac pulses in the Start driver 22 which should be produced
i`n response to the signal -START WINDING. Again a timing out
single shot 515 and data/clock flip-flop 516 are used.
Finally, the occurrence of an open circuit in the sense
winding 44 is monitored by applying the SENSE signal to a
differential amplifier 519. The output is half wave
rectified and gated by the signal GATE DRIVE through an AND
gate 520 to the clock input of a flip-flop 521. If no pulses
are present the flip-flop 521 will revert from its initially
cleared state to its set state causiny the signal SENSE OPEN
to be produced.
3~
UK9~79--018 2 5
The signal SENSE OPEN bypasses error latches 29 and is
appiied directly to the interface latches 41. The other
signals are however applied to error latches 29 as shown in
Figure 8.
In Figure 8, the SEMSE GOOD signal is inverted and
applied to AND gates 610 and 611 whose outputs set latches
612 and 613 respectively. Latch 612 is set if SENSE GOOD
goes low during the Start stage of operation and latch 613 is
set if SENSE GOOD goes low after the Start stage.
The signal -DRIVE PULSES is gated by GATE DRIVE through
AND 614 to set a latch 615. The signal -TRIAC PULSES is
gated by START LTCH and CTR4 through an AND 616 to set a
latch 617.
Should any of these latches 612, 613, 615 and 617 be
set, the DRIVE ~NSAFE signal is produced by OR 618. All four
latches are initially set by POR and can be reset for test
purposes by the signal RESET CHECK.
The preferred embodiment of the invention described
above with reference to Figures 1 to 8 is only one example of
20 how the invention may be put into practice. Within the scope
of the invention as broadly disclosed and claimed, many
changes and alternatives are possible.
For example, in the preferred embodiment, the drive
control signals to the run driver circuit are derived from
25 sensed mains voltage during the Start stage and from a
separate oscillatcr during the Ramp and Run stages~ It would
be equally possible to derive the drive signals to the run
winding entirely from a variable freguency oscilla~or and
synchronise the oscillator output with the mains by means of
3Q a phase locked loop during the Start stage.
~ f~33'7'S
U~9-79-018 26
Also although the drive control signals applied to the
Run driver are essentially switching signals of square wave
form, there is no reason why sinusoidal signals could not be
employed and applied after amplification by way of triac
devices to the run winding.
Many aspects of the motor control operation in the pre-
ferred embodiment are essentially open loop e.g. the
durations of the start, ramp and brake stages are determined
by a counter~ It would be possible to define these stages by
monitoring the motor speed. If speed were monitored in this
way, closed loop control of the frequency ramp and of final
speed could be employed. In this case a smooth rather than a
staircase ramp function could also be employed.
