Note : Les descriptions sont présentées dans la langue officielle dans laquelle elles ont été soumises.
~L ~
AN IMPROVED SE~IICONDUCTOR CHIP PACK~GE
BAC~GROU~ OF T~IE INVENTION
Thi~ invention relates ~o pack~ging o ~emicon-
ductor ahlp~, and more particularly, to a chlp
package wherein ~he sub~trate i9 prorided wlth a
repea~ing pa~tern of ~onductor ends, with each
pattern defining ~ites to p~rmit the reception of a
varlety o~ different chip~. The ~onductor ends are
wlred to connect both within the ~ame pattern and
with adjacent pattern~O Thi~ permits ~he personali-
zation o~ a common sub~trate to receive many d~~er
~nt co~bination~ of chip~.
In the evolutlon of semiconductor technology,
packag~ng of the chip~ ha~ taken on increasing
1~ lmpoxtanc~. The number o~ circuit3 that can be
placed on a chip ha~ drama~ically lncreased a~ has
the number of ~unctlon3 o~ any given chipo Thera
are chlp~ which are primarily memory, tho~e which
are prima.rily logic, and those which are mixed logic
and memory. A~ miniaturlzation progres3~s it i5
becomlng increa3lngly de~irable ~o placs a number of
dif~erent chip , ana different comblnations of chips
onto a ~lngls ~ub~tra~e. Thi~ ~hip/subs~rate pack~ge
can bs lnserted a~ a unlt into various piece~ of
equipment.
However, wlth prior art t2chnology each module
having a di~er~nt combination o~ chlp~ had to h~e
a juDstrate designed speci~ically for each combina
tion o~ chlps. Indaed, even in a ~ingl~ chip module,
each different chip re~uirad a different ~u~3~.rate
uni~e to the given ship. Prior art examples o~
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technolo~y or providing a substrate .or a glven
chlp or specific combination of chips i8 repra~ented
in U~ S. Patents 4,202,007 and 4"193,802 which
xepresent one technology ~or making ~ubstrate~ with
buried wiring~ and }B~ Technisal Disclo~ure Bulletin,
Vol. 22, i~o. 5 dated Qctober 1979, at pagss 1841-
1842, which xepre~ent~ a different technolocJy. This
prior art, however J show~ only a technigue for
forming substra~e~ which will accept predetermined
0 chip9 OX chip combination~. The nece~sity of design-
in~, producing and stoc~piling a different substrate
for each chip and ~ach dif~rent combination of
chips i~ ~ery expensîve and adds ~igni~icantly to
tllf~ cos~ .
SU~ARY OF T~ ~NTIO~L~
According to the pre~ent invention/ a sub~krate
~or packaging semiconductor chip~ i~ provided havlng
a chip mounting ~ur~ace. The substrate i5 ~truc-
tured with conductors having opposite end~ termina-
~ing at ~aid moun~ing sur~ace with intermecl.iateportions connectinrJ the end3 o~ t~e conductor3. Tile
encls of the conductor~ are arranged ln repeating
pattPrn~ longitudinally along the 3ub~trate separated
by ortho~onal strips on the ~urface which are free
of conductor ends ~o allow for d~n~e ~urface wlring,
The intermediate portions o~ some conductors connect
end3 within a pattern and of 30me conductor3 connect
end~ in ad~acent pattexns. The conductor ends in
each pattern are ~ositioned ~o delinea~e a pluralit~
of chip mounting site3 ha~ing qufficient pacinq
between the conductor end3 to per~it the positioning
*Registered Trade Mark
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of chip mounting means which may be electrically
connected to tne end~ of the conductor~ ~y surrace
me allization.
In this way a ~ingle 3ub trate can be pexsonal-
ized ~o accep~ a plurality of different chlpq at a~ygiven pattern loca~lon and to utili2e two or more
locations to mount chip3 with a~propriate connec-
kions betwe~n.
The sub~trate of the present lnvention utilize3
subsurface conductor3 to pxovide basic interconnec-
~lon within each pattern and be~ween adjacen~ pa~texns
and 3urface wlrlng or the uni~ue personalized chip
mounting and wiringt
DE~CRIPTON OF TH~ DRA~INGS
FIG. l i~ a plan view of a chip pac~age of thi~
invontion ~howing the substrate and chips mounted
thereon;
PIG. 2 i3 a ~ectional view taXen ~ub~tantially
along the plane designated by line 2-2 o~ FIG. l;
FIG. 3 i3 a ~ectional vi~w taken sub3tantially
along the plan~ dQsignated by the line 3-3 o FIG. l;
FIG. 4 1~ a ~ectional vlaw taken sub tantially
along the plane designated by the llne 4-4 o~ ~IG. l;
and
FIG. 5 i~ a per~pective exploded YieW o ~ome
of the laminae utilized to form the ~ub~t~ate oE
FIG. l.
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5~
D~SCRIPTI0~ OF T~E PRE~ERR~D ~ODL~NT
Referring now to the drawing, a substrata
having two repeating patterns of suxface ter~lnation
of conductors i~ sho~n~ I~ is to be under3tood that
5 the substrate could be made lo~ger with additional
repeating pattern~, but two are shown for ~he pur~ose
of illu.stration.
The su~trate, designatad by the refere~ce
charac~er 10, is ~ormed ~rom a plurality of differ
ent lam~nae, 12a, 12b, 12c, 12d, some of which are
shown ln FIG~ 5. Tha laminae ar~ hin 3hee~s s~f
green (uncured~ ceramic or other dielectric material.
Differen~ lamlnae 12a, 12c, and 12d have o~med on
their faces ~31ec~rical conduc:tors 14a, 14c, 14 d,
respectively. The conduc~ors 14a and l~c are in a
pattern that ~tart~ a~ the top edcJe o:f -the lamlna,
extends along the a ::e below the top surfacs and
xe turn~ again to the top sur~ace. The conductors
l~d extend frolll the top surface of the lamlna along
20 ~he ~ace to the bottom surf~ce. Some of the lamillae
represented by laminae 12b may have no conductor~
and are to control lateral 3paclng of the end~ of
t~e corlduc:tors7
The re :auired nurlber of the lam~nae, both with
conductoxs an~ without, are assembl~d in face~to-face
relationship wi~h the conductor sides oriented in
the s~me dix2ction to for~ the ~ubstratP tO ~th
heir top edges forming a chip mo~nting surface 16
and their opposite edges forming a rPverse surface
18. The assembl~d ceramic lamlnaa are cured in a
conYentional manner to form a unitary structure.
.BTJ~9~81--007
The method of foxming the laminae and the substrate
from the lamunae is well known in the art and
descxibed in said U. S. Pate~t~ 4, 202,007 and
4,193,082 commonly assigned.
A~ seen i~ the drawing, the completed sub3tra_e
ha~ on it~ top ~urface two patterns of conductor
ends 20 separated by an area or strip 22 free of
conductor end~. In the drawiny ~le ends of the
conductor~ on the chip mounting surface are shown as
dashe~ ( ) which roughly approximates their shape.
~Yhen surface rletallization connects to the conductor
end~, as will be describe~ infra, thi~ connection i~
~hown by a circle around the dash. The respective
conducto~3 are designated in FIG. 1 by the reference
15 characters 14a, 14c, and 14d at the left hand sida.
~ach da~h on the ame horizontal line is on the same
lamina. The interconnect pattern can be determined
from FIGS. 2, 3 and 4. ~ith this technique al~er-
nate patterns and conductor ~ree strip~ can be
repeated many times.
The spaciny o~ the conductor end within each
of the pattern~ 20 i~ so arranged that there i~
space provided within the pattexnR ~o provide for
chip mounting ~ikes. Th se ~ites can accommodate
chip mounting metal pads 24 which are ~uitable for
flip chip bonding o~ semicondu~tor chips as well as
surface metalli~ation or wiring 26 for connecting
chip pad3, and/or conductor end3. ~This arrangement
can also be ~tili2ed for wire bonding, or o~her types
o~ chip bonding.) Tllese pads 24 can be arranged
within ~he ~ite to accommodate ~elected chips which
are to be mDUn Pd on the sub~trate and intercon-
nected thereto by conventional flip chip solde.r
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bonding tec}~iques. It will be apparent that many
dirferen configurations or chip mounting pad3 24 or
wi~ing metalli~a~ion could be applied at each of the
pattexns to accommodate tne requisite selection of
chip mix which i3 to ~e u~ed on the substrate. Thi3
then allows for the personalization of a single
subætrate to accommodate a wide var~eky and mi~ of
chip~. Four possible chips in two adjacent patternq
axe 5hown, the chips bei~g designated 2~, 30, 32,
and 34.
A com~ination of the subsurface conductors 14a,
l~c, 14d, and mounting 3urface wiring 26 inter~
connect the variou~ chip~ 28, 30, 32, and 34 togethar,
and to input~output (I/O) pins 36 are attached to
the rear surface 18 of the subs~rate. In ~ome casas
other types o~ I/O connections such as edge connec-
tions or "bump" connections may be emplo~Ied
rathar than I/O pins. ~s can be seen in FIGS. 1, 2
and 3, the configuration of the conductor~ 14a and
14c provide 3ub~urface connection between various
poin~s on the chip mounti~g surface. For example,
the conductors 14a provide wiri.ng connbction between
one extreme ~ide of a pattern and the other side,
while the conductors 14c provide wiring connections
wi~hin each pattern as well as subsurface co~nection
'oetween one pattern and the next adjacent pattern
benea~h ~he strip 22 on the mou~ting sur~ac~.
The strip 2~ on the mounting surfaca provides a
relatively large surface area free of ~h4 ends of
conductor to accom~odate a large amoun~ of surface
wiring which may re~uire long ortnogonal segments,
and wnich wiring connect~ both co~ductor end in the
same pattern as well as co~ductor ends f~om one
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--7-
pattern across the strip ~2 to the conductor ends ln
tha next pattern. Thus by the u~e or repeating
conductor end patterrs on the surfac~ interconnected
by ~ub~urface conductorq together with space~ between
the repeating pattern for wiring having long ortho~
gonal segmen~3 a single sub~trate can be used for
many combinat~.on~ o chip~.
It ~hould be noted that the figure3 are some-
what ~implified in several respect~ from conven~
tional actual phy~lcal e~bodimsnt~ for the 2~rpose
of clarification. The modiflcation~ inclu~e showing
only a few laminae forming a ~u~str~te whereas many
~ore coul~ be used to provide denser connection
~nd/or a ~w~der ~ub~trate. A1 op only a sele_ted
sample of ~urface conne~tions and wlring i5 ~hown,
and this wiring could be mu~h ~enser~ Also, mo~t
chips would hav~ more qolder connection ?oint~ ~han
those sho~ we~er, ~'ox the sake o clarlty, ~
minimal showing o~ these vPriou3 el~enk3 i3 made ~o
illu~trate the invention,
Th~ abov~ desoribed tec.~niqu~ of for~ny the
substrate ~rom lamina9 utillzing the e~.ge~ thereo~
to form the chlp ~ounting surface 1~ the ~referred
technolo~y. ~o~.~ever, the technolo~r ustr.g la~.inae
bonded together ln 42ce ~to-face relattonshi~ .~ith
the face of one lz~na as ~he surface as ~t sclo3ed
ln said I~M TQChn~Ca1 Disclo~urs ~ullQtin, ~701. 22,
~o. 5, Oc~ober 1979, a~ page~ 1841 1842 could also
be used.
BU-9-81-007
