Note : Les descriptions sont présentées dans la langue officielle dans laquelle elles ont été soumises.
PHN 9855
The invention relates to a device for digitizing
an analog signal whose mean value is constant, comprising
a delta modulator which is adapted to sample the signal
during successive time intervals, each of which has a dur-
ation corresponding to n pulses of a clock pulse generator,and to supply m ~m ~ n) pulses per time interval, m being
dependent on the difference between the values of the
signal at the beginning and at the end of the interval.
A device of this kind can be used, for example,
for digitizing an ECG signal for ~urther processing. An
ECG signal is a more or less periodic signal whose mean
value equals zero or a (constant) contact potential occur-
ring between the electrodes and the skin of a patient. It
has been found that inaccuracies in the delta modulator add
error signals to this signal which, of course, disturb the
~urther processing. It is an object of the invention to
eliminate these disturbing error signals while maintaining
the useful information.
To this end, a device in accordance with the
invention is characteri~ed in that -the output o -the delta
modulator is connected to a correction circuit which is
constructed as a digital high-pass fil-ter.
The invention is based on the recognition o~ the
fact that the error signals caused by the delta modulator
are of a continuous and slowly decreasing or increasing
nature, so that a high-pass filter can be used to separate
these error signals from an ECG signal which contains
virtually no very low frequency components except for the
unimportant contact potential.
A preferred embodiment o~ the device in accordance
with the invention is characterized in that the correction
circuit is adapted to reduce the signal applied thereto by
PHN 9855 2 15.5.2981
the progressive rnean value of the signal.
The invention will be desc:ribed in detail h.ereirl-
after ~ith reference to the accompanying daigrammatic dra-
wing.
Figure 1 shows a block diagram of an emboclimen-t o-~
a device in aceordance with -the inventi.on.
:Figure 2 shows a eircuit diagrarn of an embodiment
of a delta modulator -to be used in the circuit shown in
~igure 1, and
Figure 3 shows a~ circui t diagram of an embodiment
of an adaptive high-pass filter -to be used in the circuit
shown in ~igure 1.
The deviee shown in Figure -I eompri.ses an input -l
for supplying an ECG si~nal to a delta modulator 3, ~ria an
15 isolating transformer 4, -the outpu-t of the cZel-ta modulator
is connected -to a bidirectional counter 5 ~.hi.ch in :its turn
is eonnected to an adap-tive high-pass filter 7, the output
signal of which i.s applied to the output 9 of the device.
The clelta modulator 3 and the counter 5 are eontrolled by
20 a eloek generator 11 and the bidiree-tional counter 5 is
arranged to increment the eount for eaeh elock pulse in a
direetion determined by the logic state of -the output f.rom
the delta rnodulator 3. The digitizecl.~CG signal appearing
on the QltpUt 9 can be applied to an arithmetic uni-t 13,
25 f`or example, a mic:roproeessor ~or further processing,.
Fi~ure 2 is a more detailecl vie~ of an e~ bodimerlt
of the del-ta modula-tor 3. Tlle modulator comprises a firs-t
input 15 f`or receivirlg the analog ECG signal from the inpu-t
1 and a second input 17 for receiving a reference voltage.
30 The first input l5 is eonnected to a first input 20 of a
corllpa:rator 21 via a first amplifier 19 with a gain of,
for example, 10. The second input 17 is connec-ted, via a
second amplifier 23, to an electrode of a capacitor 25, the
other electrode of which is connec~ed to the second input
2~ of the comparator 21.
The ou-tput of the comparator 21 is connected to
the D-input of a bistable element 27~ the C-input 29 of
~hich is connected to the clock generator 1l shown in
~X~3~3
PHN 9855 3 15.5.1981
:Flgure 1. The outpu-t Q of the bistable elemen-t 27 controls
an e:Lectronic switch 31 and is also connected to i;he
output 33 of the delta modlllator. The elec-tronic switch 31
comprises two switching uni-ts 35 and 37 9 -the ~ormer being
capable of connecting the electrode of -the capacitor 25
which is connected -to the compara-tor 21 to a positive
current source 3g or to a negative current source 41 as
desired, whilst the second switching -unit at the same time
connec-ts the other electrode of the capacitor to a negative
current source 43 or a positLve current source L~5~ respecti-
vely. However, during the intervals between clock pulses
both switches 35 and 37 are in a neutral 9 open circuit
state (not shown).
The operation of this circuit is as follows 1~hen
15 the instantaneous value of the amplified ECG signal on the
first input 20 of the comparator 21 is greater than the
vo~tage on the second input 26 of the comparator, the OUtpllt
of the comparator carries a logic 1 and hence also the
D_input of the bistable element 27. ~s a result, when the
20 next pulse from the clock generator l1 appears on the C-
input of the bistable element 27, the output Qthereof also
carries a logic 1, so -that the switch 31 is se-t -to the
position shown. Consequently, for a brie~ period of time t
which is determined hy the clock geIlera-tor -ll -the capacitor
25 25 is connected -to -the current source 39 wllich s~lpplies a
current IH to the capac:Ltor, so tha-t the la-tter .is cllarged
by an amoun-t IHt, wi-th -the resul-t tha-t the vo:l.-tage on -the
second inpllt 26 of the comparator 21 approaches -that on
the firs-t input 20. ~t the same time the other electrode
30 of the capacitor 25 is connected to the negative current
source 43, ~hich discharges a charge amoun-t I'IIt in order
to preven-t the charge IHt supplied b~ the current source
39 from disturbing the reference voltage.
When the voltage on the input 20 of the compara-tor
35 21 is lower than that on the second input 26, a logic O
appears on the D-input of the bistable element 27, said
logic 0 setting the switch 31 to the other position ia the
Pl-IN 9855 4 15.5.'1981
outpu-t Q, in reac-tion to the ne~t pulse of` -the clock
generatox, so that the capaci-to-r 25 t9 co~lnectecl to the
negative currerlt source 41 fo:r a periocl of -time t and i.s
discharged by an amount IL.t~ ~or compensa.-tion, the posi-ti-ve
cur:rent source 45 applies a charge I'L.-t to t'he other
electrode of the capacitor.
It will be clear from the foregoing that -the
voltages on the two inputs 20 and 26 of the comparator 21
will be equal after a number of periods of the clock
lO generator 11. Any subsequent rise of -the ECG signal means
that a number of logic ones are applied to the output 33,
and any decrease that a number of` logic zeroes are applie~.
Therefore, the value of the ~CG signal can be reconsl;ructecl
at any instant from the series of :Logic ones and ~eroes
5 appearing on the output.
It has been found in practice, ho-rever, that -the
above reasoning is onl~ appro~imately correct, because on
the one hancl the -two curren-t sources 39 and 4l are no-t
exac-tly iden-ti.cal and because on the other hand the input
20 26 of the comparator 21 has a finite input resistance, so
that a small curren-t IB leaks from the capacitor 25. Conse-
quently, when the capacitor 25 has been charged for a
nllmber o:f periods of` the cloclc generat;o:r ll and is sub-
sequently d:ischarged again f`or the same nllmbe:r of periods,
25 the vol-tage on the second input 26 o:t' the comp~rator 2l
will not have retuxrled to the origi.l-lal val-le Conversely, a
s:ignal on the f`lrst lnput 20 whlch t`irst rises from a given
value and subsequently decreases -to its orig:Lnal value
again, ~rill thus produce mequa.l numbers of zeroes and ones
30 on the OlltpUt 33. ~n the d:igi-t:i~ed signal this becomes
mani:~est as a steadily lncreasing ox decreasing voltage
superposed on -the signal.
This will be illustrated hereinafter ~rith
reference to a calculation. .Assume that the leakage current
to the comparato.r as described above equals IB and that
the current sources 39 and 41 are not e~actly iden-tical, so
that
Pl-IN 9(~55 l5.5.l981
~ ~[ (1)
In the position of` the swi-tch 31 sho~rn~ the curren-t to
the capacitor 25 equals:
I = IH ~ IB = I ~ ~ I - IB
Therein:
In the other position of the switch 31, the current of the
capacitor 25 equals:
I~ = IL * IB = I ~ IB
It appears from (3) and (5) that the charging and dischar-
ging process can be described with the unequal current
sources Iu and Id which are an amount ~ I smal].er and lar-
ger, respectively, than an ideal current source I.
If the num'ber of periods n~l during whic~l Iu is
switched on and -the num'ber of periods nl during w}lich Id is
~switched on (nu being the number of ones and nd being ~he
number of zeroes on the output 33, and n = nu + nd) is
counted each time during a fixed number (n) o~ clock
periods, the voltage increase ~ V on the capacitor 25
follows therefrom:
~ ~/ = nu Iu ~ lld Icl = (n~-rld) I ~ (r~ ~rll) . ~ I (~)
Because n~ nd = n
:is consta tl t:
~ V - (nu - nd) . I + c (7)
in which C = n . ~ I (8)
If the signal on the first inpllt ~0 of the
comparator 21 increases b~ an amo~mt ~ S during a given
time interval having a length o:~ n clock periods, the
voltage increase ~ ~ on the capaci-tor 25 will be equal to
S, so that.'
~ S = (nu ~ nd) . I ~ C (9)
It follo~rs there~rom that:
, ~ ~ S - C
~nu ~ nd~ = --I ' ( 10)
If the mean value of -the signal appearing on the i.nput 15
is constant, the mean value of ~ S o~er a prolonged period
PIIN 9~55 6 !5,5.19~1
of time mus-~ he equal -to 0. ~Iowever, it :t'ollows f`rom (-10)
tha-t the ~a1.ue nu ~ nd steadil.y increa.ses or clecreases i.n
-time. This means that the pulse series appearing on -the
output ~3 represents a signal which is composed of -the
signal on the input 15 ancl a ste~dily increasing or
decreasing signal~ Therefore, the value on the output of
the bidirectional counter 5 (Figure 1) will continuously
increase on average. The high-pass filter 7 serves -to
reduce this mean value to a constant amount, so that on the
l0 output 9 a digital signal appears which is an e~act repre-
sentation of the anal.og signal applied to the input 1.
Figure 3 shows an embodiment Or the high-pass
filter 7. The filter comprises an inpu-t 47 which recei.ves
the signal S(t) from thebidirectional coull-ter 5. This input
15 is connected -to a positive i:nput of a firs-t adder ~9 whoxe
OUtp~lt is connected on -the one side to the o~ltpu-t 9 ot` the
device and on the other side to an attenua-tor 51 which
multiplies by a factor ~1. The output of the attenuator
is connected to a ~i.rst posi-tive input of a second adder
20 53, the output of which is conn.ected to a delay element 55
having a delay ~ T. The output of the delay elernent is
connected on the one side to a negative inpu-t of the first
adder 49 and on the other sicle to a second pos:itive :inpllt
of the second adder 53.
The opera-tion of this circu:i-t i.sas ~'ollows. ltt
an instarl-t T ~ ~ T, a cligi.tal s:ignal S(T + ~ T) appears on
the lnput ll7, This signal is redIlced in tlle first adcler by
a signal S(T) ~hich is the progressive mean value at the
instant T of the varying signal S(t). In the attenuator 51,
30 the signal S(T ~ ~ T) - S(T) is multipli.ed by ~ and the
resultant signal ~ ~S(T ~ ~ T) - S (t) ~ is increased
iIl the second adder 53 by S(T). The signal S (T) +
cG f S~T + ~ T) - S(T) } thus formed is delayed by an
amo~mt ~ T in tha delay element 55. The signal which
leaves the delay element at the instan-t T ~ T7 therefore,
is the signal which arrived in the delay el.ement at the
instant T and equals:
P:HN 9855 7 l5.5.1981
S(~ VG ~ S(T) - S(T- ~ ~r) } =(1- ~ )S(T- ~ ~r) ~
~ S(T) = S(T)
This is because -the progressive mean value at ~he ins-tan-t T
is a combination of the "old" progressive mean value at
the i.nstant T ~ ~ T and the ins-tan-taneous value of` the
signal S(t) at the lnstant T9 lt being necessary to mul-tiply
both components by a weighting factor, -the sum of the
weighting factors being equal -to 1.
The progressive mean value of a signal having a
lO mean value zero is substantially equal to zero, whilst the
progressive mean value of a signal which linearly increases
in time is equal to the instan-taneous value of -this signal,
minus a cons-tant amount. Therefore, if the signal S(t)
on the input 47 is composed of a combina-tion of` a variable
15 signal having the mean value zero and a linearly increasing
sigr1al, the signal S(-t) - S(t - ~ T) on -the~utput 9 ~rill
be equal -to -the variable signal having a constant mean
val~le.
In the described embodiment, the high-pass t'ilter
20 is constructed as a combina-tion of t~o adders, an at-tenua~
tor and a delay element. It 1~ill be clear tha-t the arithme-
tical operations to be e~ecuted thereby on the signal can
alternatively be e~ecu-ted by a suitably progr.llllmed
arithmetic uni.-t, t`or example, thc microp:roces~or 13.
