Note : Les descriptions sont présentées dans la langue officielle dans laquelle elles ont été soumises.
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InGaAs FIELD EFFECT TRANSISTOR
This invention relates to a field effect
transistor comprising semlconductor source, drain and
channel regions all of the same conductivity type, the
channel region having an InGaAs composition, source and
drain electrodes contacting the source and drain regions~
and a gate electrode overlying the channel regionO
Many modern technological applications, such as
memories or si~nal processing using in-tegrated circuits and
microwave transmis~ion using discrete devices such as field
effect transistors, require higher speed operation than i5
currently available. Many approaches have been taken in
attempts to obtain such higher speed operation. ~or
example, one approach uses superconducting Josephson
junction devices to obtain high speed operation. Another
approach uses semiconductor materials other than the
commonly-used silicon to obtain higher speed opexation.
The first such semiconductor material extensively
investigated was undoubtedly GaAs, which is o interest
because of its high room temperature electron mobility
which is higher than that of Si. Another semiconductor
material currently of interest, although it has not been
investigated as extensively as GaAs, is In 53Ga ~7As which
may be grown lattice matched to semi-insulating InP
substrates. This semiconductor material is of device
interest, especially for field effect transistor (FET)
applications, because of parameters such as its high
electron mobility, which is approximately 50 percent
greater than that of GaAs. It is also of device interest
because of its low effective electron mass, and the large
energy separation between the central and satellite
conduction band minima. These features suggest that
electrons move faster in InGaAs than in GaAs or Si.
However attractive these parameters make InGaAs
appear as a material for devices, construction of field
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effect transistors whose performance actually benefits from
these favorable parameters has been difficult because of
the low Schottky barriex height for metals on n-type
materials. The Schottky barrier height is only 0.2 eV and
conventional metal semiconductor field effect transistor
(MESFET) gates cannot be fabricated because of the large
gate channel leakage current. As a result, workers in the
field have investigated various schemes for obtaining an
effective low leakage gate structure which could modulate
the electron flow in the InGaAs channel region. One
approach used diffused junction FETs and is described in
Electronics Letters, 16, pp. 353-355, May 8, 1980. The
second approach uses grown Schottky-assisted gate field
effect transistors and is described in Electron Device
Letters, EDL-l, pp. 15~-155, August 1980. Both of these
approaches su~fer the drawback at the present time of
presently requiring custom growth and processing techniques
to achieve a working device and the prospects for large
area uniformity in device characteristics are relatively
small. Yet another approach uses inversion mode metal-
insulator-semiconductor (MIS) structures. Such s-tructures
are advantageous because they offer greater ease in FET
fabrication. A structure using this approach is described
in Electron Device Letters, EDL-2, pp. 73-7~, March 1981.
While fabrication difficulties are somewhat alleviated with
this approach, the device performance, as measured by the
transconductance, obtained has so far been disappointing.
The problems are overcome in accordance with the
invention in a InGaAs field effect transistor in which the
gate electrode is separated from the channel region by a thin
insulator o~ SiN.
Thus, according to the invention there is
provided a field effect transistor comprising semi-conductor
source, drain and channel regions all of -the same
conductivity type, the channel region having an InGaAs
composition, source and drain electrodes contac-ting the
source and drain regions, and a gate electrode
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overlying the channel region, characteri~ed in that the
gate electrode is separated from the channel region by a
thin layer of SiN.
Other structural features cooperate to give
improved device characteristics as will be described below.
In the drawing:
FIG. 1 is a sectional view of one embodiment of a
device according to this invention;
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FIG. 2 is a top view of one embodiment of a
device of this invention; FIG. 3 shows the deplection mode
drain characteristics of a device according to this
invention; and FIG. 4 plots the square root of the
effective gate voltage, horizontally, versus the drain
currentt vertically.
It has been found that ield effect transistors
fabricated on n-type InGaAs and having an insulator
assisted gate electrode with an interfacial insulating
layer between the metal and the channel layers have
desirable device characteristics such as a reduced gate
leakage curren~ and high transconduc-tance. The
semiconductor material of the channel layer comprises
InxGal_xAsyPl_y. Embodiments in which y is approxîmately
equal to one are preferred because oE the higher electron
mobility for these compositions. The insulating layer
comprises silicon nitride in a preferred embodiment. In a
further preferred embodiment, the device has an
In 53Ga 47As channel layer disposed on a high resistivity
buffer layer comprising Al ~8In 52As, source and drain
electrodes electrically contacting said InGaAs channel
layer and a gate electrode having a metal and a layer of
silicon nitride between the metal and the
In 53Ga 47As layer. Devices having a 1.2 ~im gate length
and a net donor doping concentration in the channel of
approximately 5xlO16cm~3 showed a dc transconductance of
130 mS/mm. Both depletion and enhancement mode operation
were observed.
The layers are conveniently grown by ~olecular
beam epitaxy (characterized by crystal lattice matching) on
semi-insulating InP substrates. The silicon nitride layer
is conveniently grown by plasma-enhanced chemical vapor
deposition. The insulator-assisted gate technology of the
invention has significant advantages in fabrication
flexibility and control as compared to other approachesO
For reasons of clarity, the Figures are not drawn
to scale. A device of this invention, indicated generally
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as 1, is shown in cross-section in FIG. 1. The device
comprises substrate 10, buffer layer 13, a channel
layer 16, a source-drain contact layer 19, source and drain
electrodes 22 and 25, respectively, insulator layer 28, and
contact 31. The substrate is typically semi-insulating
Fe-doped InP.
The channel layer comprises n-type GaxInl_
~AsyPl y having a net donor concentration within the range
from 2X1016 to 8xlO16cm~3 and a thickness that is typically
between 0~35 and 1.8 ~m. The channel electrical thickness,
which depends on the channel doping, should be equal to the
maximum calculated depletion width. Lower donor
concentrations are generally undesirable because the
channel will not conduct sufficient current and higher
concentrations are undasirable because the electron
mobility begins to dropO The doping concentration and
thickness are determined by the requirement, for depletion
mode operation, that the channel be depleted at the
expected gate operating voltage~ This condition also
depends on the thickness of the insulator layer 28 as well
as the dielectric constants of the insulator and the
semiconductor.
The buffer layer, which should also be high
resistivity, typically comprises nominally undoped
Al 4~In 52As, although other compositions that have high
resistivities and lattice match to InP may be used. The
resistivity of this layer should generally be greater than
106 ~cm~ The buffer layer is typically between 0.2 and
0.5~ m thick, and although nominally undoped, it is
generally n~type Al 4~In 52As with a donor
concentration of approximately 2xlO15cm 3. If sufficiently
high quality substrate surfaces can be obtained, the
channel layer may be grown directly on the semi-insulating
substrate~ i.e., the high resistivity buffer layer may be
omitted.
The contact layer for forming the source and
draing region 19 is highly dopedy typically
n-type with a donor concentration o approxirnately
8xl018cm~3, and reduces the source and drain parasitic
resistances. The source and drain electrodes 22,25 are
typically ohmic contacts formed by, for example, a
Ge/Au metallization and alloying.
The insulator 28 is a thin, (yenerally between
approximately 150 and 1000 ~ngstroms) layer of silicon
nitride. The insulator layer should be as thin as possible
and the minimum thickness is determined by the maximum
acceptable leakage current under reverse bias. The
insulator layer should also be thin enough or an extended
depletion region without ;nversion. For depletion mode
operation, the holes tunnel into the metal and there is no
accumulation of holes next -to the insulator semiconductor
interface. There is no absolute upper limit to the
insulator layer ~hickness but thicknesses greater than
approximately 250 Angstroms may degrade device
characteristics. Other insulator materials may be used but
silicon nitride has the virtues of being easily controlled
and apparently reducing the surface states. For
enhancement mode operation, a very small leakage current is
desired. Silicon nitride apparently does not undergo any
deleterious chemical reactions with the semiconductor
materials and it creases a minimum of surface energy states
at the interface with the semiconductor. The insulator
material should have as high a dielectric constant and be
thermally compatible with the semiconductor material.
Contact 31 is a metal such as aluminum and forms the gate
electrode.
The advantages of the device are best obtained in
depletion mode operation and the device is not designed for
inversion mode operation.
In a preferred embodiment, y is approximately
equal to 1.0 and x is approximately equal to 0.~7 because
this combination of parameters defines the composition
having the highest electron mobility that can be lattice
matched to InP.
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Device fabrication conveniently begins with the
growth of epitaxial layers comprising, for the embodiment
d~ Al.48In.52AS~ Ga~47In s3As and highly doped
Ga 47In 53AS and which are grown on semi-insulating
InP substrate. These layers are conveniently grown by
molecular beam epitaxy (MBE) although other methods may be
used. It has been found that covering the back surface of
the substrate, i.e., wafer, with silicon nitride prevents
substrate decomposition which is caused by reaction of the
wafer with the indium that is used to mount the wafer for
the growth process. Device fabrication then proceeds with
mesa isolation which begins with pa~tern delineation of a
resist coated wafer that defines the mesas. Isolation is
conveniently accomplished by ion milling at an angle of
45~ Ion milling proceeds until the substrate is reached.
An angle of approximately 45 is preferred because the
shape of the mesa wall facilitates formation of good
source, drain, and gate contacts~ The substrate may now be
conducting and if so, the conducting portion may be removed
by an etchant such as 10 percent HCl in H2O or a
5:1:1 mixture of H2S04, H2O2 and H2O. The source and drain
contacts may not contact the substrate in some embodiments.
In these embodiments, the conducting portion of the wafer
need not be removedO Alternatively, the mesa could be
defined by chem;cal etching.
Source and drain electrodes are then formed by
opening windows for the contacts and evaporating a
AuGe/Ag~Au metallization. This is followed by lift off and
alloylng at a temperature hetween 400C and 460C for a
time of approximately 10-20 seconds. This procedure gives
very low contact resistances on In 53Ga 47As having
n+-doped contact layers. Using the transmission line
method, the specific contact resistance was estimated to be
approximately 5xlO 3~-cm2 which corresponds to 0.01 ~-mm of
device width. Width refers to the dimension perpendicular
to current flow and length to the dimension parallel to
current flow~ The length should be as short as possible
for high speed operation. Other metallizations may, of
course, be used, and for some, no alloying with the
n~ contact layer may be neededO
The channel region is then pattern delineated and
etched using an etching solution such as 5:1 citric
acid/H202, and a photoresist mask. The etching is
conveniently monitored by measuring the current between
source and drain electrodes 22 and 25 and terminating the
etching when the saturated channel current reaches a
predetermined value, usually 80 120 mA per mm of device
width. The etching proceeds through the n+-layer into the
channel layer. This etching procedure permits abrication
of a channel having the desired -thickness. The photoresist
material is then removed and the semiconductor material
cleaned. A thin layer of silicon nitride is then deposited
by plasma-enhanced chemical vapor deposition from silane
(SiH4) and ammonia (NH3) at a substrate temperature that is
typically approximately 300C. This process provides a low
temperature deposition process having an in situ cleaning
capacity. The gate metallization, typically having lengths
between 1.2 and 1.8 ~m, is then ~ormed by aluminum
evaporation and lift off. The gate metallization appears
to contact the channel layer but this does not adversely
affect device performance as the dielectric has been
deposited everywhere and the area covering ~he active layer
is very small. Any metal can be used but aluminum is well
suited for use with lift offO Devices actually tested had
gate widths of approximately 250 ~m.
A top view of a device abricated according to
this processing sequence is shown generally as 11 in
FIG. 2. Shown are substrate 100, mesa 110, source
electrode 220, drain electrode 250 and gate electrode 311.
FIG. 3 shows the drain current-voltage
characteristics of a device having a gate length of
approximately 1.2 ~m and a channel doping of approximately
6xl016cm 3. The channel doping was estimated from gate
capacitance versus voltage measurements and Hall effect
characterization of samples which were grown under similar
conditions. The dc transconductance at a drain bias of
4.5 volts was 130 mS/mmO The unit used is milli-siemenS
per mm of gate width. Both depletion mode, that is, VGs
less than zero, and enhancement mode, that is, VGs greater
than zero, operations were observed with negligible gate
current. With this device, the intrinsic transconductance,
gm, was approximately 150 to 170 mS/mm. The gate source
capacitance was 4~2 pP/mm at zero bias and 1.3 pF/mm at VGs
of zero and a VDs of 4 volts.
The inerred effective velocity of the electrons
in the channel was determined by employing the
relationship:
IDS5 = q VS ND ~a - [2F ~ VG)/q ND] }, (1)
where VS is the electron velocity, a is the channel
thickness, ND is the bulk donor concentration, ~ is the
semiconductor dielectric constant, ~ is the diffusion
potential due to the band bending at the interface, and VG
is the effective gate channel voltage including self-
biasing effects. Differentiating with respect to VG
yields:
dIDSs/d(VG 1/2) = v5 ~ 2~qND (2)
IDSs is plotted as the function of VG1/2 in FIG. 4 where
the source resistance of 4Q-mm and a critical field of
3xlO3V/cm were used. As can be seen, this curve departs
from the linear relationship predicted by Equation (2) and
is probably due to the neglected effects of the built-in
potential ~ and the reductions of insulator voltage at low
gate voltages as well as to the velocity degradation near
the buffer interface at high absolute values of VG. Using
the central portion of FIG. 4, an effective electron
velocity of 2.0+005xlO7cm/sec was found. This is
approximately 50 to 70 percent higher than the values
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g
commonly observed in GaAs MESFETs at room temper~ture and
is somewhat lower than the peak electron velocity predicted
theoretically for this particular composition. The
electrons in the devices are within a few
thousand Angstroms of a heterointerface and this may result
in a decrease in velocity relative to that of bulk
material.
Although the invention has been described by
reference to a particular embodimentl modifications of this
embodiment will be readily thought of by those skilled in
the art. For example, devices may be fabricated with a
gate electrode having two fingers for increased current-
carrying capacityO Additionally, the device may be
constructed in planar embodimentsO In these embodiments,
electrîcal isolation between devices is provided by, for
example, ion implantation which renders the volume between
individual devices nonconducting. Other methods may, of
course, be used.
It is also contemplated that a plurality of
devices may be present on a single substrate. Devices of
this invention may also be integrated on a sinyle substrate
with light sources or photodetectors. Light detection may
also occur in devices of this invention.
