Note : Les descriptions sont présentées dans la langue officielle dans laquelle elles ont été soumises.
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MI CR OCOMP UTE R VA RI AB LE DUT Y
CYCL:E: SIGNAL GENERATOR
Related Applications
This application is related to copending Canadian
patent applications entitled "Computer Bus Interpolator"
and "Microcomputer Retriggerable Interval Counter" which
bear serial numbers 434,867 and 434,885, respectively,
filed on August i8, 1983, in the name Jerrold V. Henning.
Field of the Invention
This invention relates generally to the field of
electronic digital computers and more particularly
pertains to microcomputers connected to control the duty
cycle and frequency of signal generators.
Background o~ the Invention
Signal generators provide signal waveforms consisting
of a train of pulses and may be used for various testing
and other purposes in electronic circuitry. The waveform
of a signal generator consists of a series of signal
levels, with one of the signal levels being considered as
'on" time for the waveform, and each signal duration
between "on" times considered as an "off" time for the
waveform. It is desirable to be able to adjust a signal
generator to produce waveforms having a specified duty
cycle (ratio between "on" time and "off" time) and
frequency of the output signal produced by the generator.
In the past~ signal generators have been produced
which include manually adjustable knobs or dials which
serve to control the duty cycle and frequency of the
signal genera~or output signal.
Because of the advent of the demand for miniaturized
equipment that allows computer processor control over the
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shape of a signal generator waveform, prior signal
generator circuitry has been inadequate to provide the
needed performance.
SUMMARY OF THE INVENTION
In accordance with an aspect of the invention ~here is
provided a signal generator for producing an ou~put signal
having a repeating sequence of signal levels in which a
first signal level for a first time duration is followed
by a second signal level for a second time duration, said
signal generator comprising first storage means for
storing a first number corresponding to said first time
duration; second storage means ~or storing a seco~d number
corresponding to said second time duration; counting means
connected to said first and second storage means for
producing a timing indication after a period of time
corresponding to a number loaded into said counting means
from either said first storage means or said second
storage means; a first switch for controlling the loading
of said first number from said Eirst storage means into
said counting means; a second switch for controlling the
loading of said sec~nd number from said second storage
means into said counting means; and signal gating means
comprising a flip-flop having an input connected to said
counting means to cause said flip-flop to change state in
response to said timing indication; a first AND gate having
inputs connected to an output of said flip-flop and to
said timing indication of said coun~ing means, said first
AND gate having its output connected to said second switch,
to cause the contents of said second storage means to be
loaded in~o said counting means when said output signal is
at said first level and said timing indication is produced;
and a second AND gate having inputs connected to an output
of said flip-flop and to said timing indication of said
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counting means, and having its output connected to said
first switch to cause the contents of said first storage
means to be loaded into said counting means when said
output signal is at said second level and said timing
indication is produced.
It is an object of the invention to provide signal
generator circuitry for producing a pulse train signal
having a duty cycle and frequency which may be varied
under the control of a programmed microcomputer.
It is another object of the invention to provide a
microcomputer having a signal generator integrated
therewith so that a microcomputer contained in a single
integrated circuit package mby be used to provide a train
of output pulses.
Another object of the invention is to provide a signal
generator which incorporates digital storage latches for
containing digital numbers corresponding to the specified
"on" time duration and "off" time duration of the pulses
in the output signal waveform.
It is still another object of the invention to provide
a microcomputer with a signal generator so that once
initiated, the signal generator continues to produce a
train of output pulses without requiring control by ~he
processor of the microcomputer.
Another object of the invention is to provide a
microcomputer with a signal generator having a counter,
the contents of which may be determined by the processor
of the microcomputer so that operation of the processor
may be synchronized with the production of an output
signal by the signal generator.
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The signal yenerator circuitry of this invention acts as a pulse
generator to provide a pulse signal waveform which may be varied under
the control of a microcomputer processor. The pulse generator operates
without r~quiring intervention or control by the processor but varies
its waveform duty cycle and fr~uency in accordance with parameters
specified by the mi~rocomputer processor. The ci~cuitry of the pulse
generator is compatible with the processor circuitry so that the pulse
generator may ~e incorporated into a mi~rocomputer on a single
integrated circuit chip. The pulse generator circuitry is configure~
to be connected dir~ctly to an internal data bus of the microcomputer
so tnat no external interfacing lines between integrated circuit chips
are required in or~er for the processor to control the operation of tne
~ulse generator~
A signal generator is connected to a microcomputer processor in
order to provide a source of a pulse waveform which has a duty cycle
that may be controlled by the microcomputer. The microcomputer is
pIOy~ to select the "on" time and "off" time for the waveform of
the pulse generator so that the duty cycle and frequency of the pulse
generator output may ~e controlled. The pulse generator stores the
information p~ovided by the microcomputer processor and produces a
pulse waveform in ~cordance with the information provided to it. The
pulse generator uses buffer latches to store the data provided by the
processor and includes a counter which is triggered by the
microcomputer clock and which is used to count down from the data
stored by the buffer latches. ~ flip-flop is connected to the
underflow output of the counter in order to produce an output waveform
that makes a transition each time that the counter has counted down to
zero. Logic gates are connected to the flip-flop9 buffer latches, and
counter so that when -t~e counter has reacheb zero, it is reloaded with
aata from ~he appropriate buffer latches. Therefore, the pulse
generator proceeds with the production of an output waveform having the
desired duty cycle by alternately using the contents of the two latches
(the "on" time, and "off" time) without requiring intervention or
control from the microcomputer processor.
Brief Oescription of the Drawings
Figure l is a schematic block diagram of a microcomputer
incorporating an embodiment of the signal generator circuitry of this
invention.
Figure 2 is a s~hematic diagram showing the signal generator
circuitry of this invention.
Figure 3 is a timing diagram of the operation of the circuitry
shown in Figure 2 and displaying the time behavior o~ the output signal
produced.
Description of the Preferred Embodiment
Referring first to Figure l, the microcomputer lû of the preferred
embodiment is a commercially available R~5ûû/l one-chip microcomputer
available from Rockwell International Corporation, Anaheim, California,
U.S.A. The microcomputer lO is a oomplete, hîgh performance, eight bit
NMOS microcomputer on a single chip. The micr~computer lO includes a
central processing unit 12 which includes a clock oscillator l~, second
phase frequency generator circuit 16, timing con~rol logic 18, program
counter 20 (a sixteen bit register divided into two eight bit
sections), instruction register ~2, instructiGn decoder 24, arithmetic
and logic unit (ALU~ 26, accumulator 28, index registQrs X and Y (30
and 32, respectively) used for generai purposes or as displacements to
modify the base address to obtain a new effective address, a stac~
pointer 34, a processor status register 36, and interrupt logic
ci~cuitry 38.
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Tne microcomputer 10 includes memory 40 which includes both read
only memory 42 and random access memory 44. The read only memory 4~
contains the program instructions and other fixed constants for use by
the micrccomputer 10. The random access memory 44 rnay be used for
read/write memory during operation of the microcomputer 10.
~ he microcomputer 10 includes an internal address bus 46,
instruction control lines 48, and an internal data bus labeled 50
and 52. The data bus is labeled as two separate portions, 50 and 52,
in Figure 1 in order to reflect the fact that the data bus is time
multiplexed in synchronism with the timing control 1~ and clock secpn~
phase circuitry 16. This multiplexing of the data bus allows register
and port control operations to proceed on ~he bus as represented in
portion 5~ during one clock phase (referred to as "Cl time"), and
allows data transfer operations to proGeed during the subsequent clock
phase represented as bus 50 in Figure 1 (referre~ to as "C2 time").
A register/port address decoder 5~ provides control over the
addressing of registers and input~output ports by controlling the
operation of the bus 52. A group of input/output ports 56~ 58, 60
and ~2 are provide~ in the microcomputer lD in order to allow the
microcomputer 10 to be ~onnected to external peripheral devi~es -(not
snown). A mode control register 64 is connected to the internal data
bus 50 in order to control the operating mode of the microcomputer 10
and tne handling of interruptsO An edge detector 66 is connected to
the input/output port 56 in order to allow the sensing of transitions
2~ in the signals provided to the input output port 56 from an external
peripheral device (not shown). An interrupt ~la~ register 68 and
AND/NOR gate 70 are connected to ~he inierrupt logic 38 in order to
handle the prooessing of interrupts oy the microcomputer 10. Interrupt
enable register 80 is connected to control the operation of gate 70.
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As mentioned above, the data bus 52 allows register
control operations during a clock phase referred to as "Cl
time". The bus 52 may be used to specify a read or write
operation from CPU 12 and also to specify an address
location (from address decoder 54). The following
description will refer to the contents of the bus 52 as a
read or write comrnand combined with a hexidecimal number
corresponding to a register address.
The operation of the data bus 50 and 52 is further
explained in the disclosure of the Canadian Patent
Application Serial No. 434,867 identified above.
Serial communications are provided in the microcomputer
10 by a transrnitter buffer and shift register 72, status
register 74, receiver buffer and shift register 76/ and
serial communications control register 78.
Counter/latch circuitry 82 and 84 are connected inside
microcomputer 10 in order to interface the microcomputer
10 to external devices (not shown).
Referring next to Figure 2, the counter/latch 84
includes the signal generator circuitry of this invention
for producing an ouput signal on line 86. The signal on
line 86 may be used by ext~rnal devices ~not shown) as a
source of controlled frequency and duty cycle pulses. The
counter/latch 84 is operated by the microco~puter 10 in
order to produce a train or sequence of "on" pulses
separated by "off" spaces. The processor 12 and memory 40
control the operation of the circuitry 84 by controlling
the starting or initiation of the output signal on the
line 86, the stopping or termination of the output signal
on the line 86, and the frequency and duty cycle of the
output signal on the line 86. The processor 12 and rnemory
40 exert control over the circuitry 84 by controlling the
contents of the data bus 50 and 52.
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The counter/latch circ~itry 84 includes a sixteen bit decrementing
counter 8d which is divided into two eight bit register portions, an
"upper counter ~" and a "lower counter B". The counter ~8 produces an
underflow signal on the line ~ after the counter 88 has decremented
its contents to ~ero. The counter 88 may be loaded with a digital
number and is connectea to the timing control circuit 18 (see Figure 1)
so that the numerical contents of the counter 88 are decremented each
time that a clock pulse is received from the circuitry 18.
The pulse/lat~h circuitry 84 also includes storage register
latches 90 and 92 which are preferably sixteen bit buffers for holding
numbers (multibit digital words) that may be loaded into the counter
88. The latch 90 is divided into two eight bit registers, labeled
"upper latch B" and "lo~er latch B". The latch 92 is divided into two
eignt bit registers, labeled "upper latch C" and "lower latch C". The
function of each of the latches 90 and 92 is to store parameter
information (digital numbers) received from the processor 12 and memory
40 through the bus 50 so that the stored numbers may be provided to the
counter 88 for use in producing the output signal on the line 86. The
latch 90 holds a digital number corresponding to the "off" time
duration for the output signal on line 86. The latch 92 holds a
~iyital number corresponding to the "on" time duration for the output
sisnal on the line 86.
~ us gate 94 is connected between the bus 50 and the "upper latch B"
portion of the latch 90O ~us ~ate 94 is shown schematically in
Figure 2 as a field effect transistor and symbolizes an array of eight
such transistors which haYe a control terminal 98 that allows eight
bits of digital da~a to be transferred from the bus 5û and loaded into
the upper eigh$ bits of the la$ch 90. Similarly, gate 96 has a control
terminal 106 and is connected between the bus 50 and the "lower latch
B" portion of the latch 90 so that the lower eiyht bits of the latch 90
may be loa~ed from the bus 50.
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The control terminal 98 for the bus gate 94 is connected to the
output of an OR gate lOû having inputs 102 and 104. The gate
inputs 102 and 104 are connected to respond to selected contents of the
bus 52 (such as "write OOlD" or "write OOlE", respectively) in order to
actuate the bus gate 94. The control terminal 106 is connected to
res,oond to a selected cont~nts of the bus ~ (such as "write OOlC") to
control the actuation of the bus gate 96.
~ uffer gates 108 and 110 have control terminals 112 and 114,
respectively and are connected between latch 9û and latch 92 so that
the contents of latch 90 may be transferred to latch 92, The control
terminals 112 and 114 are connected together to respond to selected
contents of the bus 52 (such as write ûOlD) so that the transfer from
latch 90 to latch 9~ of sixteen bits may be controlled.
Buffer gates 116 and 118 have a common control terminal 120 and are
connected between latch 92 and counter 88 so that the contents of
latch 92 rnay be transferred to the counter 88. Similarly, buffer
gates 122 and 124 have a common control terminal 126 and are connected
between the latch 90 and the counter 88 so that the contents of
l~tch 90 may be transferred to the counter 88. The control
terminal 126 is connected to the output of an OR gate 1~8 haviny
inputs 130 and 132. The input 130 of OR gate 128 is connected to
respono to selected contents of DUS 52 ~such as write OOlE) so that the
loading of sounter 88 from latch a may be controlled by the
processor 1~ and memory 40 through the bus 52.
The underflow signal line 89 from the counter 88 is connected to
the input 134 of OR gate 136. The OR gate 136 also has an input 130'
which is connected together with the input 130 of the gate 128 in oxder
to respond to selected contents of the bus 52 (such as write OOlE).
The output of the OR gate 136 is connected to the toggle input of a
toggle flip-flop 13&, The toggle flip-flop 13~ has oppositeiy phased
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outputs (a togsle outpUtl and an inverse toggle output) connected to
the lines ~6 and 140, respectively. The function of the output of the
gate 136 is to cause the flip-flop 138 to change states so khat the
output signals placed on the lines 86 and 140 make transitions.
AND gate 142 has inputs connected to the flip-flop output 86 and
underflow signal line 89 in order to produce an output 132' which is
connected to the input 132 of gate 128. The function of the AND
gate 142 is to cause the contents of the latch ~0 to be loaded into the
counter 88 after the generation of an "on" pulse on the line 86 has
been complet~d. AND gate 144 has inputs connected to the inverse
toggle output on line 140 and the underflow signal on line 89 and
produces an output 120' which is connected to the control terminal 120
for the Duffer gates 116 ana 118. The function of the gate 144 is to
cause the contents of the latch 92 to be loaded into the counter 88
after the production of an "off" duration has been completed for the
output signal on the line 8~.
Before the circuitry 84 is used by tne microcomputer 10 to produce
an output signal waveform on line 86, the buffer latches 90 ana 92 are
loaded with specification information numbers or parameters
corresponding to the desired "off" time duration and "on" time
duration, respectively, to be produced on the line 86. Tne loading of
the latches 90 and 92 and the initiation of operation of the counter 88
proceeds as follows. First, the processor 12 produces a "write OOlCi'
on bus 52, and places the lower eight bits of the desired "on" time
duration number on the bus 50 so that the number is loaded in the lower
half of latch ~. Second, the processor 12 places a "write OOlD" onto
the bus 52 and places the upper eight bits of the desired "on" time
duration number onto the bus 50 so that the upper half of latch gO is
loaded from the bus 50, and also so that the contents of latch 90 are
transferred in parallel to the latch 92, thus loading the desired "on"
time duration number into the latcn 92. Thir~ly, the processor 12
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places a "write OOlC" command on the bus 52 and places the lower eight
bits of the desired "off" time duration number onto the bus 50 in or~er
to ioad the lower half of the latch 90. Fourth, the processor 12
places a "write ûûlE" command on the bus 52 and places the upper eight
bits of the desired "off" time duration number on the bus 5û so that
the latch 9û is loaded to contain the desired "off" time duration
number, so that the counter 88 is loaded with the "off" duration number
from the latch 9û, and so that the gate 136 is actuated through its
input 13û' in order to toggle the flip-flop 138 and initiate production
ot` the output signal on the lead 8b.
Once operation of the circuitry 84 has been initiated as descri~ed
above, the circuitry 84 proceeds independently to continue to generate
the output siynal on line 86 without requiring intervention from the
processor 12 or other components of the microcomputer 10, excepting
that the clock signal produced by the circuit 18 is used to trigger
decrementing of the counter 88. Therefore~ the circuitry 84
automatically sustains the production of the pulse train output on
line ~6 and allows the processor 12 to execute instructions unrelated
to the signal generator circuitry 84 during the production of the
signal on line 86. Independent operation of the circuitry 84 proceeds
through the action of the AND gates 142 and 144 which respon~ to the
toggling of t~e flip-flop 138 by causing the alternate loading of the
numDers containea in the latches 9~ and 92 into the counter 88. This
independent operation allows the processor 12 to proceed with other
tasks unrelated to signal generation during the time that a pulse train
is produced on line 86, so that the microcomputer 10 may operate more
ef~iciently by ailowing the signal generator circuitry 84 to sustain
the pulse train.
The flip-flop 138 is provided with a "set" input 146 which is
controllea Dy tne mode control register 64 so that operation of the
circuitry 84 i~ producing an output signal on the line 86 may he halted
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under control of the processor 12. Tne input 146 may be controlle~ by
the processor 12 in order to halt the circuitry 84 after a single "on"
pulse has been produced so that the circuitry 84 functions as a
one-shot or monostable mul~ivibrator.
A counter gate 148 has a control electrode 15û and is connected
between the upper eight oits of counter 88 and the bus 50 so that the
contents of counter 8~ may be loaded onto the bus 50 by actuating the
control electrode 150 in response to a selerted hexadecimal num~er
(preferably OOlD) present on the data bus 52. Similarly, counter
gate 152 has a control electrode 154 and is connected between the lower
eight bits of the counter 88 and tne bus 50. The control electrode 154
is connected to the output of an 0~ gate 156 having its inputs
connected to respond to the presence of a read command and the presence
of a selected hexadeeir-l numbers (preferably OOlC or OOlE) present on
the data bus 52. The counter gates 148 and 152 allow the contents of
the counter 88 to be determined by the processor 12 during operation of
the circuitry 84. Gates 148 and 152 will allow the microcomputer 10 to
synchronize its operations to the waveform produced on the line 86.
Referring next to Figure 3, the waveform 158 depicts the output
signai produced on the line 8~, with time increasing from left to right
in the Figure. The e~ge transitions for tne waveform 15~ are marked
with capital letters over each transition; with the letter "~"
corresponding to the transition produced by the signal applied to the
line 13G' in order to initiate operation of the circuitry 8~, the
letter "E" corresponding to the time when the gate 144 is turned on,
and the letter 'iD" correspondiny to the time when the gate 142 is
turned on. The waveform 158 is also labeled with lower case letters
"~" and "p" which correspond to the "off" and "on" time durations,
respectively. Underneath the waveform 158 in Fisure 3, arrows 160
and 162 are shown which point to the time periods during which tne
contents of latch B (latch 90) and iatch C (latch 92), respectively,
are used by the counter 88 for timing the waveform 15&.
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The waveform 158 illustrates that the contents of latches so ana 92
serve to determine the duty cycle of the waveform 158 by allowing the
relative lengths of the durations d and p to be adjusted. Figure 3
also illustrates that the frequency of the pulse train shown in
waveform 158 may be adjusted by selecting the absolute maynitudes of
the durations d and p through selection of the corresponding 3bsolute
magnitudes of the numbers stored in the latches 90 and 92. Therefore,
the numbers provideo inside the microcomputer lû by the processor l2
for storage in the latches 9O and 92 serve to specify the frequency and
duty cycle for the waveform 158 of the output pulse train produced on
the output line 86.
The underflow signal line 89 of the counter 88 may be connected to
the interrupt flag register 68 shown in Figure 1 in order to allow the
processor 12 to respond to operation of the circuitry 84 each time that
the counter 88 times out and produces a transition in the output
w~ve~orm on line 86.
While a preferred embodiment of the invention has be,en shown and
described above9 various modifications and changes may be made without
departino from the true spirit and scope o~ the present invention. For
example, a sixteen bit data bus structure may be utilize~ which does
not require the separate loading of upper and lower eight bit contents
for the latches 9û or 92 or the counter 88. Also, the pulse train
produced on line 86 may have signal levels of any desired size or
polarity, in accordance with the intended application for the
microcomputer lO. ~hile it is preferable that the pulse generator
circuitry 84 be incorporated on a single silicon chip with tne
microcomputer circuitry lO shown in Figure 1, it would be possible to
construct the pulse generator circuitry 84 as a non-integrated circuit.
