Note : Les descriptions sont présentées dans la langue officielle dans laquelle elles ont été soumises.
:~2~:9S59~1
--1--
This application is a divisional of co-pending
Canadian Application Serial No. 415,212 filed November 9, 1982.
This invention relates to a power supply circuit.
More particularly, this invention relates to a power
supply circuit which is connectable to an electronic
transmission line carrying a supply current.
Inasmuch as the present invention has particular
application for use in a telemetry system which may be employed
for sensing remote physical events, it will be described with
respect thereto.
In the field of telemetry, there are a number of
systems wbich employ a variety of sensors for sensing physical
events (e.g., sound, light, msvement, temperature, stress,
etc.) and for transmitting sensor signals over electronic
transmission lines to a central receiving station. One example
of such telemetry system is a towed sonar array system which
comprises a plurality of hydrophones connected to a
transmission line (e.g., a coaxial cable) which is in turn
connected to a central data receiving station. The towed array
is placed in water and is towed by a vessel (e.g., a submarine)
for detection purposes. Each of the sensors is capable of
generating an analog sensing signal which is converted into a
digital data signal by an A/D converter. The digital data
signal is injected onto the transmission line for transmission
to the central data receiving station.
Due to the limited data transmission capacity of
metallic transmission cables, there has been a need in the art
for circuitry which is capable of compensating for the
propagation losses of the digital data signal transmitted on
the transmission lines. Such circuits have, in general~
consisted of repeater circuits and/or resynchronizers which are
.~
~Z~355~1
placed at predetermined intervals along the transmission line
in order to amplify the signal. However, because of the serial
nature of these repeater circuits, sensor array systems
employing these repeater systems are unreliable. That is, if
one repeater in the array fails, data transmission is seriously
attenuated or ceases altogether. In addition the prior art
repeater systems are relatively heavy, making them less
desirable for use in the seawater environment of the towed
sonar array.
There is a need, in a telemetry system, for a power
supply circuit which can connect to an electronic transmission
line carrying a supply current, which is reliable and can
provide the requisite parameters for use in a telemetry system.
In accordance with the present invention, there is
provided a power supply circuit which comprises first means,
coupled to the electronic transmission line, for receiving the
supply circuit and for generating a power signal comprising a
sinusoidal current and a first square wave voltage; the tank
circuit, operatively connected to the first means, for
generating, as an output, a sinusoidal voltage which is
proportional to the sinusoidal current; and second means,
operatively connected to said tank circuit, for receiving the
sinusoidal voltage and for providing local power.
In the above power supply circuit, the tank circuit
preferably comprises an inductor operatively connected to the
first means and a capacitance operatively connected in series
with the inductor and operatively connected to the second
means.
In other embodiments, the first means coupled to the
electronic transmission line preferably comprises a first
filter circuit, operatively connected to the electronic
transmission line at first and second nodes, for receiving the
supply current at the first node, for generating a first
5~1
voltage across third and fourth nodes, and for providing a
filtered supply current to the third node. In this
arrangement, there is also preferably included a push-pull
switch circuit, operatively connected to the first filter
circuit at the third and fourth nodes, for receiving the
filtered supply current at the third node and for generating,
as an output, a second square wave voltage, in dependence upon
the first voltage; and an isolation transformer, operatively
connected to the push-pull switch circuit, for transforming the
second square wave voltage to the first square wave voltage for
input to the tank circuit.
In the above arrangement, the second means
operatively connected to the tank circuit preferably comprises
a full wave rectifier, operatively connected to the tank
circuit, for rectifying the sinusoidal voltage; and a second
filter circuit, operatively connected to the full wave
rectifier, for generating the local power.
In a still further development, there is also
provided a power supply circuit connectable to an electronic
transmission line carrying a supply current, comprising: a
first filter circuit, operatively connected to the electronic
transmission line at first and second nodes, for receiving the
supply current at the first node, for generating a first
voltage across third and fourth nodes and for providing a
filtered supply current to the third node; a push-pull switch
circuit, operatively connected to the filter circuit at the
third and fourth nodes, for receiving the filtered supply
current at the third node and for generating, as an output, a
first square wave voltage, in dependence upon the.first
.
~ 30
.
~2~J554~
voltage an isolation transformer, operatively connected to the
push-pull switch circuitj for generating a power signal
comprising a sinusoidal current and a second square wave
voltage; a tank circuit, operatively connected to the isolation
transformer, for generating, as an output, a sinusoidal voltage
which is proportional to the sinusoidal current; a full wave
rectifier, operatively connected to the tank circuit, for
rectifying the sinusoidal voltage at the output of the tank
circuit to provide a rectified voltage; a second filter
circuit, operatively connected to the full wave rectifier, for
filtering the rectified voltage wave form to provide local
power.
In the above described further development, there may
be further included a regulator circuit, operatively connected
to the electronic transmission line at the first and second
nodes, for providing an alternate path for the supply current
when the first voltage exceeds a predetermined level.
In the above embodiments, the supply current may be a
DC supply current and the filter circuit may comprise a first
inductor operatively connected between the first and third
nodes; a second inductor operatively connected between the
second and fourth nodes; and a first capacitor operatively
connected between the third and fourth nodes.
~2~55i~
Accordingly, with the present invention, the
developments described above can be employed in a telemetry
system which may have a plurality of sensing stations, the
stations having means for receiving power from the transmission
line with means for supplying current on the transmission line;
the telemetry system may include a booster sub-system employing
a switching mode regulator circuit coupled to the electronic
transmission line and for providing local power for operating
each of the components of a sensing station without having
power supply faults - i.e. short circuits, open circuits, etc.
in any one sensing station interfere with power d~stribution to
other sensing stations.
~s will be described herein, when the present
invention is employed in the telemetry system, each sensing
station in the booster telemetry system includes a switching
mode regulator circuit for receiving the power signal which is
present on the transmission line. The switching mode regulator
circuit will thus provide power to each of the circuits present
in the sensing station, so that there is no need for a separate
power source in each of the sensing stations.
The above features and advantages, which will
subsequently become apparent, are more fully described
hereinafter with reference to the drawings illustrating
preferred embodiments only, and wherein like numerals refer to
like parts throughout.
Figure 1 is a block diagram of the booster telemetry
system;
Figure 2 is a block diagram of the booster
sub-system;
Figure 3 is a block diagram of the booster circuit;
Figure 4 is a graph illustrating a digital data
signal, a booster signal and a boosted digital data signal;
l.Z~3SS~
Figure 5 is a graph illustrating how succeeding
booster circuits in an array compensate for the failure of a
booster circuit by boosting the digital data signal so that it
asymptotically approaches its normal level;
Figure 6 is a schematic diagram used for explaining
the procedure for analyzing the performance of the booster
circuit when an array of boosters is connected to a
transmission line;
Figure 7 is a circuit diagram of a first embodiment
of the booster circuit 60 of Figure 2;
Figure 8 is a circuit diagram of a second embodiment
of the booster circuit 60 of Figure 2;
Figure 9, appearing on the sheet containing Figure 6,
is a circuit diagram of a third embodiment of the booster
circuit 60 of Figure 2;
Figure 10 is a block diagram of the switching
mode regulator circuit 56 of Figure 2, and illustrates the
power supply circuit of the invention;
Figure 11 is a circuit diagram of the switching mode
regulator circuit 56 of Figure 10;
Figure 12, appearing on the sheet containing Figure
10, is a circuit diagram of the injector circuit 50 of Figure
;
Figure 13 is a block diagram of the booster
controller circuit 52 of Figure 2;
Figure 14 is a timing diagram illustrating the sync
pulses used in the organizational procedure for assigning a
time slot to each sensing station, wherein each sensing station
will inject a digital data signal onto the transmission line in
its assigned time slot;
Figure 15 is a block diagram of the booster
controller master timing circuit 288 of Figure 13;
Figure 16A is a flow diagram for illustrating the
operation of the timing acquisition controller circuit 322 of
Figure 15;
Figure 16B is a state map for the timing acquisition
controller circuit 322 of Figure 15;
12~5S~l
Figure 17A is a block diagram of the transmission
slot controller circuit 294 of Figure 13;
Figure 17B is a state map for the contention frame
controller circuit 340 of Figure 17A;
Figure 18, appearing on the sheet containing Figure
16A, is a block diagram of the data handler circuit 296 of
Figure 13;
Figure 19 is a block diagram of the watchdog circuit
298 of Figure 13;
Figure 20 is a block diagram of the soft sync circuit
302 of Figure 13;
Figure 21, appearing on the sheet containing Figure
14, is a block diagram of the primary master clock 24
illustrated in Figure l;
Figure 22 is a block diagram of the sync pulse
generator 408 and the mode controller 404 of Figure 21; and
Figure 23, appearing on the sheet containing Figure
17B, is a circuit diagram of an embodiment of the injector
circuit 410 of Figure 21.
Figure 1 is a block diagram of the booster telemetry
system employing the present invention. It is a high-speed
time-division-multiplexed system having a data handling
capability of up to 20 megabits/second. The booster telemetry
system has applications both in military and commercial systems
where a large number of sensors must be monitored. For
example/ the booster telemetry system can be used for land and
sea oil exploration and in the commercial process industry. In
one embodiment, the telemetry system is employed as a towed
sonar array system4 However, the booster telemetry system is
suitable for use in any digital data transmission system having
plural sensors.
Referring to Figure 1, sensing stations 20 are
connected to an electronic transmission line 22 which in
~Z~;3554:1
the preferred embodiment is a single coaxial cable having
a center conductor 23. The number and locatinn of the
sensing stations 20 connected to the transmission line 22
are functions of the type of physical event which is to
05 be sensed. A primary master clock 24 and a backup master
clock~26, for synchroni~ing the operation of the sensing
stations 20, are connected at one end of the transmission
line 22 ad~acent a coax termination 25. A system power
and control subsystem 27 includes a controller/receiver
28 which is a central processing system for generating
command signals for controlling the operation of the
booster telemetry system and is adapted to receive digi-
tal data. For example, the controller/receiver 28 may
include a shipboard computer which is connected to a
towed array. The system power and control subsystem 27
further includes a constant current power supply 30 which
provides power and command tones on conductors a and b of
a triaxial tow cable 32. The controller/receiver 28 pro-
vides a command signal to the constant current power sup-
ply 30 to modulate the constant current, thereby generat-
ing the command tones. The tow cable 32 is required in a
towed array in order to position the array of sensing
stations 20 at a predetermined distance away from the
vessel which is towing the array. A signal-power split-
ter 34 connects the triaxial tow cable 32 to the two-
conductor transmission line 22, so that the power signal,
the digital data signals from the sensing stations 20 and
the command signals from the controller/receiver 28 are
all conducted on the transmission line 22. However, the
digltal data signals are transmitted to the controller/
recelver 28 on conductors b and c of the triaxlal tow
cable 32. Thus, the signal-power splitter 34 splits the
digital data from the power. In the preferred
5541
-9-
embodiment, the signal-power splitter 34 comprises a
capacitor 36 and an inductor 38.
Each sensing station 20 comprises a booster
subsystem 40, sensors 42 and 44 and signal conditioning
05 circuits 46 and 48. Tlle sensors 42 and 44 are used to
sense some physical event te.g., sound, light~ movement,
temperature, stress, etc.). In the preferred embodiment,
the sensors 42 and 44 are hydrophones which are used in a
towed array. The sensors 42 and 44 provide analog data
to the signal conditioning circuits 46 and 489 respec-
tively. The signal conditioning circuits 46 and 48
amplify and filter the analog data and convert the analog
data to digital data. The booster subsystem 40 acts as
an interface between the transmission line 22 and a pair
of channels comprising (1) the sensor 42 and th~ signal
conditioning circuit 46 and (2) the sensor 44 and the
signal conditioning circuit 48. The booster subsystem 40
distributes power to operate the channels and receives
the digital data from the signal conditioning circuits 46
and 4B. The booster subsystem 40 also passes timing and
control signals (e.g., for calibrating the sensors 42 and
44) to the channels. The booster subsystem 40 is capable
of receiving any type of digital data, so that the
booster subsystem 40 could be connected to any type of
sensing circuitry which generates a digital data signal.
Whenever the booster subsystem 40 sends a con-
trol pulse CONT to the signal conditioning circuit 46 on
the DATA/CONT line, the signal conditioning circuit 46
provides 8-bit data, synchronized to the clock signal, to
the booster subsystem 40.
As noted above, the primary master clock 24 and
the backup master clock 26 are connectd to the transmis-
sion line 22 at the end of the array of sensing stations
20. The primary master clock 24 and the backup master
1~05541
-10-
clock 26 have the same internal design and are connected
to each other and to the transmission line 22 in a
slightly different manner so that one assumes the role of
the backup master clock 26 and the other assumes the role
05 of the primary master clock 24. When the sensor array is
initially turned on, the primary master clock 24 begins
functioning and the backup master clock 26 is inactiveO
The system power and control subsystem 27 is capable of
sending a command tone which is sensed by the primary
master clock 24 and the backup master clock 26. If the
command tone is a short tone burst, the primary master
clock 24 will alter the length of one of the sync pulses
(sync pulse No. 2~ to indicate a transition to or from a
calibration mode to the sensing stations 20. If the com-
mand tone is a long tone burst, then the backup masterclock 26 is turned on. Another long tone burst will turn
the backup master clock 26 off. Thus, every time a long
tone burst is transmitted by the system power and control
subsystem 27, the state of the backup ma~ter clock 26 is
changed. When the backup master clock 26 is activated,
it sends a disable signal to the primary master clock 24
to turn the primary master clock 24 off. Thus, the long
command tone burst alternately enables the backup master
clock 26 and the primary master clock 24. Since the pri-
mary master clock 24 and the backup master clock 26 func-
tion in the same manner, only the functlon of the primary
master clock 24 will be discussed below. The primary
master clock 24 transmits a synchronization signal (here-
inafter referred to as a sync signal) including plural
sync pulses on the transmission line 22, and these sync
pulses are received by the booster subsystem 40 in each
of the sensing stations 20. The sync pulses, which are
evenly spaced with reference to their trailing edges, are
used to organize the system timlng so that the ~enslng
~055~
stations 20 will in~ect digital data onto the transmis-
sion line 22 in discrete time slots.
The process of organizing the timing for the
in~ection of digital data onto the transmission line by
05 the sensing stations 20 is best illustrated with refer-
ence to Figure 14 of the drawings. The sync pulses are
generated such that eight pulses define a frame. The
frame is broken do~n into a number of time slots which is
at least as great as the number of sensing stations 20
connected to the transmission line 22. The sync pulses
are spaced equidistantly in the frame and, in general,
each sync pulse is one time slot in width. However, for
example, the eighth sync pulse is designated a frame sync
pulse (to denote the frame length) and is approximately
two time slots long. Further, the pulse width of the
first seven sync pulses may be altered to convey, for
example, changes in mode (e.g., data mode, calibration,
contention mode, etc.) to the sensing stations 20 and to
convey information on system operation to the system
power and control subsystem 27. The length of the first
sync pulse (sync pulse No. 1) is modulated to indicate
whether the system is in an idle mode or a data mode.
The length of the second sync pulse (sync pulse No. 2) ls
modulated to control calibration of the sensors 42 and
44. The trailing edges of the eight sync pulses gener-
ated during a frame are used to maintain fine synchroni-
zation of the system.
As mentioned above, the number of time slots in
a frame must be at least as great as the number of sens- -~
ing stations 20, and each sensing station 20 is assigned
a partlcular time slot for transmitting a digital data
signal onto the transmission line 22. The assignment of
a particular time slot to a particular senslng station 20
is a function of the relative position of the sensing
lZ~.35541
-12-
station 20 along the transmission line 22 with respect to
the other sensing stations 20. When the system is turned
on, the sensing stations 20 are not sending any data and
the system operates for approximately 2000 frames to
05 allow for timing acquisition. Then, the length of sync
pulse No. 1 is modulated from long (indicating idle mode)
to short to indicate that normal operation is about to
start and that the organizatlonal or contention frame is
approaching. In the preferred embodiment there are
actually two contention frames. The nominal performance
of both contention frames is the same. The first conten-
tion frame is employed to check for malfunctions in the
sensing stations 20 and to disable malfunctioning sensing
stations. Hereinafter, reference to "the contention
frame" is to the second contention frame during which
time slots are claimed by the sensing stations 20. When
the next frame sync pulse is received by the sensing sta-
tions 20, the sensing stations 20 recognize that the con-
tention frame is starting. Each sensing station 20
recognizes the sync pulses from the primary master clock
24 and any pulses which are in~ected onto the transmis-
sion line 22 by a prior sensing station 20. A prior
senslng station 20 is defined as a sensing station 20
which is closer to the coax termination 25 (or back end
o~ the array) than the sub~ect sensing station 20 (i.e.,
the first sensing station 20 is closest to the coax ter-
mination 25). For example, if there are N (where N is an
integer) sensing stations 20, then the Kth sensing sta-
tion 20 (where K is an integer less than or equal to N)
can recognize signals in~ected onto the transmission line
by the first through ~K-l)th sensing stations 20. How-
ever, the Kth sensing station 20 will not recognize sig-
nals in~ected onto the transmission line 22 by the Lth
~,~a155~
-13-
sensing station 20 twhere L is an integer and K<L<N).
This is due to the directionality of the system.
When the contention frame begins, during the
f~rst time slot the booster subsystem 40 in each of the
sensing stations 20 transmits a contention pulse on the
transmission line 22 to attempt to claim the time slot
for data transmission. If the booster subsystem 40 of a
particular sensing station 20 recognizes contention
pulses sent by other sensing stations 20, then the
booster subsystem 40 for that particular sensing station
20 does not clalm that time slot for transmission. Thus,
the first time slot will be claimed by the first sensing
station 20, the second time slot will be claimed by the
second sensing station 20, the third time slot will be
claimed by the third sensing station 20 and so on. Once
the booster subsystem 40 of a partLcular sensing station
20 has successfully claimed a time slot, it will not
transmit any more contention pulses during the contention
frame. This allows the booster subsystem 40 of succeed-
ing sensor stations 20 to claim time slots for data
transmission in the frame.
As noted above, the number of time slots per
frame is at least as great as the number of sensing sta-
tlons 20 connected to the transmission line 22. In par-
ticular, the number of slots is equal to 16n (where n is
an integer between 2 and 32). At a certain polnt in the
timing acquisition process, which normally occurs duri~g
the idle mode (prior to the contention frame3, the
booster subsystem 40 estimates the duration of a single
slot (based on the fact that frame sync pulses are
exactly 1.9 slots in duration). The booster subsystem ~0
generates slots of the estimated duration and counts the
number of such slots in a frame. The booster subsystem
40 compares the counted number of slots to the closest
55~
allowable number (16n) a~d alters its estimated slot
duration so that it coincides with the allowable number
of slots per frame.
The organizational process which takes place
in the telemetry system allows the booster subsystem ~0
in each sensing station to be interchangeable. Thus,
it is not necessary to preprogram each booster sub-
system 40 to select a particular slot for data transmis-
sion because the transmission slot i5 determined during
the contention frame shortly after the system is turned
on.
Figure 2 is a block diagram of the booster
subsystem 40 of Figure 1. Although Figure 1 illus-
trates the booster subsystem 40 as connected to the cen-
ter conductor 23 of the transmission line 22 at a sin-
gle point, the center conductor 23 of the transmission
line 22 actually goes through the booster subsystem 40
in a continuous path. The path is continuous in the
sense that data signals entering one end of the booster
subsystem 40 will travel through the booster subsystem
and will exit the opposite end virtually unchanged
whether or not the booster subsystem ~0 is operational.
In addition, there is a constant current which is
traveling from the constant current power supply 30 to
the primary and backup master clocks 24 and 26, and all
current which comes into the forward end of the booster
subsystem 40 (the side closest to the controller/-
receiver 2B) will exit from the back end (the side
closest to the primary and backup master clocks 24 and
26).
Referring to Figure 2, an injector circuit 50 is
connected to the forward end of the transmission line 22.
Injector circuit 50 adds a digital data signal in the form
of pulses onto the transmission line 22 during the
assigned time slot for the particular sensing station
1~3SS41
-15-
20 First and second booster controller circuits 52 and
54 are connected to the lniector circuit 50 and provide
digital data which is received from the channels through
local ports 1 and 2. In particular, local po~t 1 is con-
05 nected to a channel comprising the sensor 42 and the sig-
nal conditioning circuit 46, while local port 2 is con-
nected to a channel comprising the sensor 44 and s ignal
conditioning circuit 48. The booster controller circuits
52 and 54 generate transmit data signals TXD2 and TXDl,
10 respectively.
The transmit data si~nal TXDl from the booster
controller circuit 54 ~s only used by the booster con-
troller circuit 52~ and that use is to determine whether
the booster controller circuits 52 and 54 agree regarding
15 the timing ~or transmission of data onto the transmission
line 22, and thus whether the inJeCtor circuit 5û should
be disabled. The transmit data signal TXD2 from booster
controller circuit 52 is used similarly by the booster
controller circuit 54 and is also transmitted onto the
20 transmission line 22 by the in~ector circuit 50 if it is
not disabled by either the booster controller circuit 52
or the booster controller circuit 54. In the preferred
embodiment, the time slot is 20 bits wide and the trans-
mit data signals TXDl and TXD2 generated by the booster
25 controller clrcuits 54 and 52, respectively, may be high
during 18 bits of the 20 bits in the slot, the remaining
2 bits being reserved as a guard band between slot trans-
missions. The transmit data signal TXD2 from the booster
controller circuit 52 contains digital data pulses
30 throughout the 18 bits and corresponds to the digital
data received from local ports 1 and 2 plus a parity bit
and an identification bit. The transmit data si~nal TXDl
is generally similar to the signal TXD2 except that all
data bits are high.
.
355~
~16-
A switching mode regulator circuit 56 draws
power from the transmission line 22 and provides power
for the booster subsystem 40 and the signal conditioning
circuits 46 and 48. The switching mode regulator circuit
05 56 passes current therethrough undiminished on the center
conductor 23 of the transmission line 22; however, it
causes a certain amount of voltage drop on the center
conductor 23 and that voltage drop constitutes power tap-
off which the switching mode regulator circuit 56 con-
verts into local usable power.
The booster subsystem 40 further comprises abooster circuit 60 which senses information traveling
forward on the transmission line 22 and augments the
edges of the traveling digital data signal by adding
energy onto the transmission line 22. The booster cir-
cuit 60 recelves a soft sync signal from the booster con-
troller circuit 52 which alters the response time to the
edges of the digital data signals on the transmission
line 22. The soft sync signal helps the booster circuit
60 to control the timing of the edges which are traveling
along the transmission line 22 to maintain the digital
data signals on the transmission line 22 synchronous.
The booster circuit 60 also has outputs for providing two
received data signals IRXD (i.e., sync pulses and data
from prior sensing stations 20) to the booster controller
circuits 52 and 54.
The two booster con~~roller circùits 52 and 54
are identical; however, in the preferred embodiment, the
ROLE lnput of the booster controller circuit 54 is
grounded while the ROLE input of the booster controller
circuit 52 is connected to a supply voltage. This is
done so that both booster controller circuits 52 and 54
can receive data signals (IRXD) of opposite polarity~
The functions of the input of the received data signals
~ZC~S54~
IRXD to the booster controller circuits 52 and 54 are to
allow the booster controller circuits ~2 and 54 to (1)
become synchronized and maintain synchronization to the
sync pulses, (2) to participate in the organizational
05 process when the system is initialized, (3) to detect
mode information from the sync pulses, and (4) to gener-
ate the correct soft sync signal. These functions are
described in detail below. The booster controller cir-
cuits 52 and 54 are connected to partial phase locked
loop circuits 62 and 64, respectively. The partial
phase locked loop circuits 62 and 64 combine wlth cir-
cuitry within the boDster controller circuits 52 and 54,
respectively, to form a phase locked loop which is locked
onto the sync pulses received at the receive data inputs
to the booster controller circuits 52 and 54. The
booster controller circuits 52 and 54 also detect width
modulation of the sync pulses to determine the proper
mode of operation (idle, data or calibration), to deter-
mine which frame is the contention frame, and to deter-
mine if a calibration function is to be performed.
The time of occurrence of the transmit datasignal TXDl, which is provided by the booster controller
circuit 54, is a function of the slot address stored in a
register ln the booster controller circuit 54 and a func-
tion of the current position in the frame which is deter-
mined by the booster controller circuit 54 in dependence
upon the sync pulses received from the booster circuit
60. The booster controller circuits 52 and 54 each
include a watchdog circuit 66 and 68, respectively, which
monitors the timing of the transmit data s~gnals TXDl and
TXD2. If one of the watchdog circuits 66, 68 senses that
the other booster controller circuit is active outside of
the assigned time slot, it will generate an output dis-
able signal to the in~ector circuit 50, thereby disabling
~LZ~35~
-18-
any transmissions by the in~ector circult 50. Thus, if
there is any failure within the booster subsystem 40, the
failure will result in no transmission onto the
transmission line 22; that is, a failure will not result
05 ln transmission outside of the assigned time slot.
Figure 3 illustrates the booster circuit 60 of
the present invention coupled to the transmission line
22. As noted above, in the preferred embodiment, the
transmission line 22 is a coaxlal cable; however, any
suitable transmission line could be employed (e.g., a
twisted wire pair). As illustrated in Figure 3, the
booster circuit 60 is not connected in series with the
transmission llne 22, as are prior art repeater circuits,
so that even if the booster circuit 60 fails, a digital
data signal can propagate along the transmission line 22,
with the failed booster circuit 60 causing only slight
attenuation of the signal. Figure 4 illustrates an edge
of the digital data signal as it appears on the transmis-
sion line 22, at the input of the booster circuit 60, and
as it appears on the transmission line 22, at the output
of the booster circuit 60, after belng boosted. As
illustrated in Figure 4, the booster circuit 60 has a
threshold level below which no digltal data is detected,
so that all noise below the threshold level ls attenu-
ated. Once a waveform edge, which is above the thresholdlevel, has been detected by the booster circuit 60, the
booster circuit 60 in~ects a constant amplitude signal-on
the transmission llne 22, so that the waveform of the
signal which is output on the transmission line 22 has a
slightly larger amplltude and a sharper edge than the
input signal which is propagating on the transmission
; line 22 at the input of the booster circu~t 60~ Thus,
the booster circuit 60
12~?55~1
1 9
attenuates nolse while sustalning the digital data signal
and compensating for changes in the cable characteristics
which may occur due to temperature, pressure, flexure,
age, etc.
05 The booster circuit 60
is particularly su~table for use in boosting dlgital data
signals which are generated by a sensor array. When used
in this manner, a plurality of booster circuits 60
(either as a part of the sensing stations 20 or as
boosters alone) are coupled to the transmission line 22
to boost the digital data signals which are transmitted
along the transmission line 22. In the preferred embodi-
ment, the in~ected constant amplitude signal includes a
current transient having a fixed amplitude and a voltage
transient having a fixed amplitude. Since this fixed
amplltude signal is added to the digital data signal~ the
effective gain in db varies with signal strength, so that
signals which are weakened by a previously failed booster
are boosted more than normal, thereby asymptotically
; 20 restoring the digital data signal to its normal amplitude
as its propagates past additional booster circuits 60 on
the transmission line 22.
As illustrated in Figure 5, the failure of one
or more of the p]urality of booster circuits 60 will not
cause the digital data signal to be severely attenuated,
nor will it cause the entire sensor array to fail.
Figure -~ is a graph illustrating the amplitude of the
digital data signal as it propagates along the transmis-
sion line 22. In particular, Figure ~ illustrates an
example in which a ~ooster circuit 60, located at a point
80 meters along the transmission line 22, has failed.
Thus, the digital data signal drops from an amplitude of
approximately .7 volt at 60 meters to .45 volt at 100
meters due to attenuation caused by the transmission line
35S4:1
-20-
22 and the relatively sllght attenuation caused by the
failed booster circuit 60 which is located at the
80-meter point. However, the succeeding booster circuits
(located at 1009 120, 140, 160, 180 and 200 meters) boost
05 the digital data signal so that it asymptotically
approaches its normal levelO ~hus, a booster system
which employs the booster circuit 60
overcomes the serial reliability problem of
prior art repeater systems.
The following analysis of the performance of an
infinite string of boosters spaced at uniform intervals
on the data transmission line 22 is provided, with refer-
ence to Figure 6 of the drawings. Figure 6 illustrates
the transmission line 22 and the booster circuit 60. It
is assumed that a single rising edge, hereinafter
referred to as an eigentransient, ls propagating along
the transmission lLne 22 and has evolved into a waveform
shape which propagates with no further change in shape or
amplitude except for a periodlc variation, the period of
which is the booster circuit spaclng. The eigentransient
of the system, as a function of the booster circuit spac-
ing, the transmission line characteristics, and other
system parameters, is considered below.
The ob~ect of a boosted transmission line
design is to obtain an eigentransient which approximates
` a step function. It should have a rapid rise and minimal
distortions such as overshoot, preshoot, ringing, sag, -.
swell, or ghosts (i.e., delayed, attenuated secondary
steps). Any or all of these distortions could occur as a
result of single and multiple reflections from the
booster clrcuits 60 and the dispersion and attenuation
characteristics of the transmission line 22. If a system
can be designed having an eigentransient which ls sult-
ably step-like, then the digital data slgnal logic
~q:~5~i4~
~aveforms wlll propagate since each edge wlll be indepen-
dently boosted. The maximum data rate will be governed
by the rise time of the eigentransient, since accurate
operation requires that the ad~acent edges of the ~ave-
05 forms remain separate. Another ob~ect of a boostedtransmission line design is to achieve an eigentransient
which9 when viewed at a given booster, reaches a thresh-
old (approximately 20X to 30~ of the full step height) at
a point in time which precedes the beginning of that
booster's inJection onto the transmission line. The con-
dition is necessary from the hardware reallzation of the
booster due to causality.
Referring to Figure 6, ZO(~) represents the
characteristic impedance of the transmisslon line 22.
This impedance Z(~) is complex and frequency-dependent.
P(~) represents the propagation loss and delay of a cable
segment having length L, where L is the spacing between
the booster circuits 60. The propagation function P(~)
has the attrlbutes of a transfer function: It is complex
and frequency-dependent, and its magnitude and phase
represent the loss and phase shift, respectively. The
phase of P(~) includes the effect of phase lag due to
propagation delay in the transmlsslon line segment. V(~)
refers to the voltage at a booster circuit 60 denoted
800STER ~0. Il(~) refers to the current signal in the
transmisslon line 22 immediately to the left of the
BOOSTER #0 (as seen in Figure 6~. Any combination of
V(~) and Il(~) immediately to the left of the booster may
be viewed as the superposition of a traveling wave to the
right, A(~ and a traveling wave to the left, B(~. This
is true for any impedance Zo(~) of the transmission line
22. The current and voltage in the transmission line are
related to the travellng waves according to the following
equations:
~2q )5~
) = (A(~) - B(~))/Zo(~) (1)
V(~) = A(~) + B(~) (2)
Similarly9 the current, I2(~), in the transmis-
05 sion line immediately to the right of BOOSTER #O can be
viewed as a traveling wave to the right C(~) and a trav-
eling ~ave to the left D(~), which are related to the
current and voltage in the line according to the follow-
ing equations:
I2(~) = (C(~) - D(~))tZo~) (3)
V(~) = C(~) + D(~) (4)
The propagation function P(~) applies to trav-
eling waves traveling in either direction. Applying P(~)
to Figure 6, the following equations are obtained:
A'(~) = C(~) P(~) (5)
D(~) = B'(~) P(~) (6)
where A'(~) and B'(~) are defined in a manner similar to
A(~) and B(~) except that they represent the traveling
waves which are located immediately to the left of
aOOSTER #1.
Since it has been assumed that the waveform
propagatlng through the system is the eigentransient,
A'(~) and B'(~) are simply delayed replicas of A(~) and
B(~). The delay from one booster to the next is denoted
T. In the frequency demain, time delay is a phase lag
which is proportional to frequency. The eigentransient
.assumption therefore is expressed by the following equa-
tions:
-
5~
-23-
A'(~) = exp(-J~T) A(~) (7)
B'(~) = exp(-J~T) B(~) (8)
G(~) denotes the frequency domain representa-
05 tion (i.e., the Fourier Transform) of the current transi-
ent delivered into a short-clrcuit by the booster circuit
60 when it switches from a "0" to a "1" state at t=0.
Z1(~) denotes the impedance of the booster circuit 60 as
seen by the transmission line 22, when the booster cir-
cuit is at a fixed logic state. The functions G(~) andZ1(~) can be calculated for any booster circuit within a
general class o~ non-directional booster circuits 60
(Figures 8 and 9).
To apply this analysis to a directional booster
circuit 60 (Fig. 7) would require the booster model to be
expanded so that Z1(~) would include not only a shunt
impedance but also a series impedance, and that G(~)
would include not only a current transient but also a
voltage transient.
The functlons defined with respect to Figure 6
have an additional constraint due to the conservation of
current at the point where the booster circuit 60 is
attached to the transmission line 22, so that:
0 = I1(~) - I2(~ - V(~)/Z1(~) + G(~) (9)
Equations 1 through 9 con~itute simultaneous linear
equations in the unknowns A, A', B, B', C, D, I1, I2 and
V. From these equations, us~ng standard algebra, a solu-
tion for V can be obtained:
Y(~) = G (~) (10)
1 ~ 2(exp(~T)P(~ (exp(~T)/P(~
Z1(~) Zo(~) exp(~T) (P(~) - l/P(~))
~X5~5~
-24-
From equation lO the eigentransient ln the fre-
quency domain can be calculated. The voltage eigen-
transient in the time domain can then be calculated by
applying the inverse Fourler transform to the frequency
05 domain result. By varying G(~), Z1(~)~ Zo(~) and P(~)
the effects of various booster designs and various trans-
mission line characteristics and booster spacings can be
determined. This is most suitably performed as a com-
puter analysis to obtain the desired design for the
booster circuit 60 for a given transmission line 22.
To solve equation lO, one must assume a value
for the parameter T which represents the propagation time
of the eigentransient between ad~acent boosters. If the
value of T is varied while G, P, Zo and Z1 are fixed, the
calculated elgentransient changes shape and exhibits a
shift along`the time axis. Since t=O is defined as the
beginning of the current transient generated by the
BOOSTER #0, and letting Td denote the response time of
the booster circuit, the B90STER #O must detect the
eigentransient at -Td. Thus, the eigentransient must
cross the threshold of the booster at -Td, and this
crossing must not be preceded by any earlier crossing~
In use of equation 19, T is varied iteratively until this
condition is met. Through this iterative process, equa-
tion lO yields the correct value of T ln addition to theeigentransient shape based upon an assumed booster thres-
hold, booster delay time, booster impedance 71~ booster
output transient G, booster spacing L, transmission line
attenuation and dispersion P, and transmission line
impedance Zo.
From the above, a booster circuit can be
designed for a specific transmission line 22, taking into
account various choices for the booster clrcult
~.2ns~4~
~mpedance, the transmission line impedance and the trans-
mission line attenuation, dispersion, and propagation
delay.
Figure 7 is a preferred embodiment of the
05 booster circuit 60 illustrated in Figure 2 which ls
designed to couple to the transmission line 22 comprising
a coaxial cable. Alternatively, the booster circuit 60
of Figure 7 could be adapted to operate with a twisted
pair transmission line. The booster circuit 60 of Figure
7 is further designed to be coupled to a transmission
line 22 on which the digital data signal to be boosted
comprises binary signals having constant height edges and
a lower bound bn the time interval between the successive
edges. Referring to Figure 7, a transformer 70 and a
resistor 72 form a coupling network, wherein the voltage
across the resistor 72 is a function of the current in
the center conductor 23 of the transmission line 22.
Since the transformer 70 cannot couple DC levels, there
; is a certain high pass frequency cutoff for the coupling
network formed by the transformer 70 and the resistor
72. In the preferred embodiment this coupling is 3 db
down at 5 MHz. As the edges of the digital data signal
travel on the transmission line 22, the rise and fall
times of the edges are very rapid (approximaely 15 nano-
~5 seconds). The edges show up as a voltage across theresistor 72; however, as the edge falls, the droop will
not be coupled to the transformer 70. Th~-t is, the
coupling network formed by the transformer 70 and the
resistor 72 is edge-sensitive to rapid transitions but is
not level-sens~tive.
A second coupling network is formed by capaci-
tors 74 and 76 and a resistor 78. This coupling network
blocks DC levels but couples through hi~h frequency
levels. It is designed with a high pass frequency cutoff
~æ~
-26-
at 5 MHz as is the coupling network formed by transformer
70 and resistor 72. The coupling network formed by the
capacitors 74 and 76 and the resistor 78 produces a
voltage across the resistor 78 which corresponds to the
05 voltaye on the center conductor 23 of the transmission
line 22~ so that this coupling network senses the voltage
on the transmission line 22 while the coupling net~ork
formed by the transformer 70 and the resis~or senses the
current on the center conductor 23 of the transmission
line 22.
An emitter coupled pair of transistors 80 and
82 form a current switch which receives a supply current
from a constant current diode 84. The supply current
from the constant current diode 84 will normally pass
through one of the transistors 80 and 82, so that one is
conducting and the other is cut .of~. The supply current
from the constant current diode 84 can flow directly to
the emitter of the transistor 80 or it can flow to the
emitter of the transistor 82 through the coupling network
formed by the resistor 72 and the transformer 70. The
booster circuit 60 has two stable states. The state of
the booster circuit 60 is governed by the state of the
switch formed by transistors 80 and 82, which is, in
turn, controlled by a linear combination of the following
three voltages: .
1. the base voltage of the transistor 90;
~'' 2. the base voltage of the transistor 82; and
3. the voltage difference between the emitters
of transistors 80 and 92.
Both the current component and the voltage com-
ponent of the traveling wave on the transmission line 22
influence the state of the booster circuit 60. The cur-
rent component of a traveling wave on the transmission
line 22 is coupled to the voltage d~fference between the
i5~
-27- . .
emitters of transistors 80 and 82 by the coupling network
formed by transformer 70 and resistor 72. ~he voltage
component of a traveling wave on the transmission line 22
is coupled to the base voltage of transistor 82 by the
05 coupling network formed by capacitors 74 and 76, and
resistor 78.
When the forward-directed traveling wave on the
transmisslon line 22 impinges on the booster circuit 60,
the linear combination of voltages which controls the
state of the booster circuit 60 (by controlling the state
of the switch formed by transistors 80 and 82) receives
equal and in-phase contributions from the voltage and
current components of the traveling wave on the transmis-
sion line 22. Conversely, whenever a reverse traveling
wave on the transmission line 22 impinges on the booster
circult 60, the linear combination of voltages which con-
trols the state of the booster circuit 60 receives oppo-
site phase and equal amplitude contributions from the
voltage and current components of the traveling wave on
the transmission line 22. Thus, the booster circuit 60
is selectively responsive to forward traveling signals on
the transmission line 22 due to t.he above-described con-
structive interference between the voltage and current
components of a forward-directed traveling wave, and due
2S to the above-described destructive interference between
the voltage and current components of a reverse-directed
traveling wave. Further, the booster circuit 60 is ---
selectively responsive to only the high frequency portion
of a forward-direct.ed traveling wave on transmlssion line
22 due to the above-described high p2SS filterlng charac-
teristic of the two coùpling networks.
Thus, the transistor pair 80 and 82 alter-
nate.ly switches between first and second states in depen-
dence upon the combined effect of the above three inputs.
~I.Zn~5Si~
-28-
A pair of transistors a6 and 88 form a second
switching element having a constant emitter current sup-
plied by a resistor 90. As in the case of the first
switching element, the current supplied by the resistor
05 90 will normally flow entirely through one or the other
of the transistors 86 and 88 and will s~itch to the o~po-
site trans-istor in response to the base input provided by
the switchlng element formed by transistors 80 and 82.
That is, the second switching element will switch between
first and second st.ates in dependence upon the switching
of the first switching element. Thus, when the first
switching element formed by transistors 80 and 82
- switches, then nanoseconds later, the second switching
element formed by the transistors 86 and 88 switches.
This is because the outputs of the transistors 80 and 82
are coupled to the inputs of the transistors 86 and 88,
respectively. The output of the switching element formed
by transistors 86 and 88 influences the state of the
booster c.ircuits 60 through the coupling from the collec-
. 20 tors of the transistors 86 and 88 to the bases of tran-
sistors 80 and fl2, respectively. The polarity of this
coupling is such that it provides positive feedback
within the booster circuit 60. The high frequency por-
tion of the positive feedback from the switching element
formed by transistors 86 and 88 to the switching element
formed by transistors 80 and 82 is coupled through
capacitor 134 and--resistor 120, and causes the booster
circuit 60 to switch rapidly and completely once switch-
lng has been initiated by a signal edge traveling on the
transmission line 22. The low frequency and DC portion
of the positive feedback of the switching element formed
by transistors 86 and 88 to the switching elemenS formed
by transistors 80 and 82 is coupled by resistor 116, and
causes the booster circuit 60 to remain in either the
.. .
~æ~5~
first or second state lndefinitely in the absence of fur-
ther signal edges traveling on the transmisslon line 22.
As a result of this bistable characteristic of the
booster circuit 609 and because of its insensitivity to
05 droop (i.e. low frequency distortion) of the data signal
on the transmission line 22, the booster circuit 60
reconstructs the DC content of a data signal traveling on
the transmission llne 22 even when that D~ component is
missing or distorted.
When the switching elements within the booster
circuit 60 switch, the current step which occurs in the
emitters of transistors 80 and 82 is conducted through
the coupling network formed by resistor 72 and trans-
former 70. The impedance of this coupling network con-
Yerts the current step into a high pass filtered voltage
step. The high pass filtered voltage step is in~ected
onto the transmission line 22 by the transformer 70 and
appears on the transmission line 22 as if from a floating
voltage source in series with the transmission line 22.
When the second switching element in the booster circuit
60 switches from either a first state to a second state
or second state to first state, the hlgh frequency por-
tion (i.e., 5 MHz and up in the preferred embodiment) of
the current step which occurs in the collector of tran-
sistor 88 is coupled to and in~ected onto the transmis-
sion line 22 by capacitors 74 and 76, and appears on the
transmission line 22 as if from a current source shunted
across the transmission line 22. When switching occurs
in the booster circuit 60~ the voltage which ls in~ected
onto the transmission line 22 by the transformer 70, and
the current which is in~ected onto the transmission line
2Z by capacitors 74 and 76 produce a forward-directed
traveling wave with the shape of a step function ~hich
has been high pass filtered. This in~ected traveling
-30-
wave combines linearly with and travels with and boosts
the original incident signal edge which causes the
booster circuit 60 to switch.
As long as the edges in the traveling waves
05 signal on the transmiss~on line 22 alternate their polar-
ity (which is true for the type of signals which the
booster circuit 60 is designed to transmit - i.e., binary
logic signals), the booster circuit 60 will respond So
each edge by switching its state and will thus boost each
10 edge in the traveling wave.
A transistor 92 generates a constant current on
its collector at all times to establish the DC bias on
the base of the transistor 80, which establishes the
booster threshold for the rising edge, so that the
15 booster circuit 60 operates when this threshold is
exceeded.
The level of current supplied by the transistor
92 is set so that the booster threshold for a rising edge
equals that for a falling edge, the booster threshold for
20 a falling edge being a functlon both of the current
through a collector of transistor 88 when it is conduct-
ing current, and of the current suppl~ed by the collector
of transistor 92. A receive data lnterface circuit 94 is
formed by a pair of transistors 96 and 98 and resistors
25 lOOj 102 and 104. The receive data interface circuit 94
provides the receive data signals IRXD to the booster
controller circuits 52 and 54 in dependence upon the
state of the booster circuit 60. Resistors 106, 108,
110, 112, 122, and 124; capacitors 130 and 132; and diode
30 140 are used for biasing purposes.
Resistors 114, 116, 118 and 120 are used for
suppression of UHF instabilities in the transistors 80,
82, 86 and 88 which could cause oscillatory bursts during
switching transients and lead to erratic behavior of the
~z~ss~
booster circuit 60 with respect to the response thresh-
old.
As described above, the state of the booster
circuit 60 is influenced by:
05 1. internal positive feedback from translstors
86 and 88;
2. the high frequency portion of the forward-
traveling waves on the transmisslon line 22; and
3. biasing supplied by transistor 92.
One additional factor which influences the
state of the booster circuit is the soft sync signal
which is generated by the booster controller circuit 52.
The soft sync signal is coupled to the base voltage of
the transistor 80 by resistors 126 and 128 and capacitor
136. The soft sync signal modulates the response thresh-
old of the booster, making it slightly larger or smaller,
to slightly retard or accelerate each traveling signal
edge on the transmission line 22 as the edge passes the
booster circuit 60, thereby maintaining the edges of the
travellng wave on the transmission line 22 synchroni~ed.
Figure 8 is a first alternate embodiment of the
booster circuit 60 which omlts the directional properties
of the preferred embodiment of Figure 7. Referring to
Figure 8, the booster circuit 60 includes a differential
25 l~ne receiver 142 having an input 144 and an inverted
input 146. The input 144 is coupled to the transmission
- line 22 by a capacitor 148, while the inverted input 146
is coupled to the transmission line 22 by a capacitor
150. The differential llne receiver 142 has an output
30 152 connected to a feedback resistor 154 and an lnverted
output 156 connected to a feedback resistor 158~ In the
preferred embodlment, the dlfferential llne receiver 142
is one third of a model F 10116 trlple differential line
receiver manufactured by Fairchild Semiconductor9 Inc.
..
3L~05S~ `
and the outputs 152 and 156 are differential emitter
coupled logic outputs. Each waveform edge of the digital
data signal on the transmission line 22 is coupled into
the differential line receiver 142 through the capacitors
05 148 and 150, thereby causing the differential line
receiver 142 to change state, following the signal
state. Each time the differential line receiver 142
changes state, a current transient is inJected onto the
transmission line 22 through a capacitor 160. The cur-
10 rent transient boosts each waveform edge, thereby enhanc-
ing its amplitude and rise time as illustrated in Figure
4.
The initial state of the embodiments of the
booster circuit 60 illustrated in Figures 7 and 8 when
15 power is turned on is arbitrary. If the booster circuit
60 is initially at a logic level which is opposite that
on the transmission line 22, the first waveform edge of
the digltal data signal does not cause the booster cir-
cuit 60 to change state. Thereafter, the booster circuit
20 60 functions correctly, i.e., its logic state follows the
logic state of the digital data signal.
The booster circuit 60 of Figure 7 or 8 does 3
not boost noise signals corresponding to waveform edges
which are below the threshold level. Therefore, noise
25 and partial reflections are attenuated by the transmis-
sion line 22 and by the loading effect of the booster
clrcuit 60, while the digital data signals, which are ~
above the threshold, are boosted. The threshold level of
the booster clrcuit 60 of Figure 8 is determined by the
30 amount of positive feedback which is provided through the
resistors 154 and 158 and can be varied with the particu-
lar design. The threshold level of the booster circuit
60 of Figure 7 is fixed at one-fourth the nominal signal
amplitude, but, with addition of resistors to create DC
~D
ss~
-33-
feedback from the collectors of transistors 86 or 88 to
the base of transistor 80, the threshold can be altered.
The booster circuit 60 of Figure 8 is coupled
to the transmission line 22 only through its capacitors
05 (148, 150 and 160~. Likewise, the booster circuit 60 of
Figure 7 is coupled to the transmission line 22 only
through capacîtors 74 and 76 and transformer 70. Thus,
the DC offset between the booster power supply and the
transmission line 22 is arbitrary. In addLtlon, although
the booster clrcuit 60 in the embodiments of Figures 7
and 8 is only AC coupled, it follows the digital data
signal includlng its DC content. This is because the DC
content of a bi-level waveform can be inferred ~rom ies
edges and because the booster can sense the edges via its
AC coupling.
Figure 9 is a second alternate embodiment of
the booster circuit 60 wherein
elements referenced by the same numerals in Figures 8 and
9 represent corresponding elements. In the embodiment of
Flgure 9, the inverted output of the differential line
recelver is not used for feedback purposes~ Capacitor
162 is a DC blocking capacitor. Capacitor 164 and
resistor 166 perform the same coupling function as
capacitor 160 in Figure 8. Capacitor 167 and resistors
168 and 170 are used for biasing purposes in the embodi-
ment of the booster circuit 60 illustrated in Figure 9.
Figure~9 also illustrates the input of a soft sync signal
from the booster controller circuit 52.
In another alternate embodiment, the booster
circuit 60 is implemented by a Schmitt trigger circuit.
The Schmitt trigger circuit is bistable when no pulse is
present, but is set high by positive pulses which exceed
its hysteresis zone and is set low by negative pulses
which exceed its hysteresis zone.
OS5~
-34-
Figure 10 is a block diagram of the switching mode re-
gulator circuit 56 of Figure 2. In the preferred embodiment,
the switching mode regulator circuit 56 acts as a gyrator. A
gyrator is a two-port device where the current in port 1 is pro-
portional to the voltage on port 2 and the current in port 2 is
proportional to the voltage on port 1. Thus, the output voltage
of the switching mode regulator circuit 56 is regulated by the
current supplied by the constant current power supply 30, and
the input voltage to the switching mode regulator circuit 56
which determines its tap-off power is proportional to the load
current drawn by the sensing station 20 from the output of the
switching mode regulator circuit 56.
A voltage limiter circuit 172 provides two backup cur-
rent paths for the supply current. In the preferred embodiment
of the present invention the constant current power supply 30
provides a 600 milliamp DC constant current on the center
conductor 23 of the coaxial cable 22. A capacitor 174 allows
high frequency data edges on the transmission line 22 to pass
through the switching mode regulator circuit 56 without any
attenuation. Further, if the supply current will not flow into
the switching mode regulator circuit 56, the voltage across the
capacitance 174 will begin to rise until it reaches a point
where the regulator circuit 172, comprising the two backup
current paths, starts conducting. A filter circuit 176
receives a supply current and a voltage is developed across a
filter capacitor within the filter circuit. A push-pull switch
circuit 178 is connected to the filter circuit 176 and acts as
a multivibrator that produces an AC waveform on the primary 180
of an isolation transformer 182. Thus, a square wave is pre-
sent on the secondary 184 of the isolation transformer 182. The
secondary 184 of the isolation transformer 182
is connected to a tank circuit
~Z~5~
186 which is a series resonant tank. The tank circuit is
driven by a voltage square wa~le to generate a larger
amplitude sinusoidal waveform. The tank circuit provides
an output voltage which is proportional t4 its input cur-
05 rent (i.e., the current in the secondary 184 of the iso-
lation transformer 182), and an output current which is
proportional to its input voltage. A full wave rectifier
188 rectifies the sinuso;dal output of the tank circuit
186, and a dual filter 190 filters the output of the full
wave rectifier 188 to provide the supply voltage for the
sensing station 20. A damper circuit 173, including a
resistor 175 and a capacitor 177, eliminates a resonant
interaction of the capacitance 1i4 and the capacitors in
the filter circuit 176 with the capacitors in the dual
filter 190, such resonant interaction being mediated by
the gyrator pr~perty o~ the switching mode regulator cir-
cuit 56.
Figure 11 is a circuit dlagram for the switch-
ing mode regulator circuit 56 of Figure 10. As noted
above, the regulator circuit 172 provides two backup cur-
rent paths for the current flowing on the center con-
ductor 23 of the transmission line 22. The first backup
current path comprises a diode 192, a transistor 194 and
a resistor 196. The second backup current path comprises
a diode 198, a transistor 200 and a resistor 202. The
capacitance 174 comprises capacitors 204 and 206. The
filter circuit 176 comprises imluctors 208 and 210 and a
capacitor 212.
The push-pull switch circuit 17B comprises a
30 first pair of transistors 214 and 216 and a second pair
of transistors 218 and 220. The transistors 214 and 216
conduct as a pair, that is, when one is on both are on;
similarly the transistors 218 and 220 conduct as a pair.
3 ~55~L
The tank circuit 186 comprises an inductor 222
having a split wlnding and capacitors 224, 226 and 228.
The full wave rectifier 188 comprises four diodes 230,
232, 234 and 236. The dual filter 190 comprises an
05 inductor 23~ having dual windings and capacltors 240 and
242.
~ he filter circuit 176 together with the
capacitors 204 and 206 form a filter that prevents ripple
generated in the switching mode regulator circuit 5S from
traveling to the transmission line 22. As noted above,
backup current paths are provided through transistors 194
and 200; however, in normal operation, the supply current
flows through the inductor 210 to the active clrcuitry of
the switching mode regulator circuit 56 and back to the
transmission line 22 through the inductor 208. When the
current flows through the inductor 210, thls causes a
vol~age drop across the capacitor 212. The push-pull
switch circuit 178, including the transistors 214, 216,
218 and 220, acts as a multivibrator which produces an AC
waveform on the primary 180 of the isolation transformer
182. Thus, transistors 214 and 216 conduct for half of
the time and transistors 218 and 220 conduct for the
other half of the time, so that there is a square wave at
the output of the transistor 214. As a result, a square
wave is generated on the secondary 184 of the isolation
transformer 18Z and a sinusoidal circulating current is
~~ produced in the tank circuit 186 due to the resonance ln
the inductor 222 and the capacitors 224, 226 and 229.
Although, in the preferred embodiment, three capacitors
224, 226 and 228 are provided, it ls only necessary to
have one capacitor ln the tank circuit 186. A sinusoidal
voltage is produced across the capacitor 224 and a sinu-
soidal current circulates in the tank clrcuit 186. The
sinusoidal circulatlng current circulates through the
~.20~;S~L~
secondary 184 of the lsolation transformer 182, so that a
transformed current flo~s through the prlmary 180 of the
isolation transformer 182. One half of the primary sup-
ports the current on half of the sinusoid and the other
05 half supports the current on the other half of the sinu-
soid, so that the current flowlng lnto the center tap of
the primary 180 of the isolation transformer 182 is
always flowing unidirectionally, ie., it is always flow-
ing into the center tap~ This current is a full wave
rectified sine wave and for one half cycle it flows
through the upper hal~ of the primary 180 of the isola-
tion transformer 182 and is conducted through the tran-
sistors 214 and 216. In the other half cycle the current
flows through the bottom half of the primary 180 of the
isolation transformer 182 and through transistors 218 and
220. Thus, in both instances, both halves of the current
at the primary center tap of the isolation transformer
182 come from the side of the capacitor 212 connected to
the inductor 210 and travel through the transistors 214
and 216 and 218 and 220 through a transformer 244 and
back to the side of the capacitor 212 connected to the
inductor 208.
The push-pull switch circuit 178 further
includes resistors 246 and 248 and capacitors 250 and 252
for absorbing spiky transients on the square ~aves going
into the transformer 182~ Resistors 254 and 256 cause
the transistors 216 and 218, respectively, to conduct
less current than the transistors 214 and 220. The tran-
sistors 216 and 218 are included in the push-pull switch
circuit 178 to lmprove the start-up characteristics
because they have a lower threshold voltage than the
transistors 214 and 22n. Thus, the transistors 216 and
218 enable the switching mode regulator circuit 56 to
become active hith a smaller input voltage. Diodes 258a,
.
i
~2~iS~
-38-
b, c, d, e and f clip the sinusoidal currents at the out-
puts of the secondary of the transformer 24~ to a square
wave for input to the gates of the transistors 214, 216,
218 and 220.
05 Figure 12 ls a circuit diagram of the in~ector
circuit 50 of Figure 2. The ln~ector circuit 50 adds
pulses on the transmission line 22, in the form of a
digital data signal, under the control of the transmit
data signal TXD2 from the booster controller circuit 52.
The transmit data signal TXD2 drives a switching tran-
sistor 259 through a coupling circuit comprising a
capacitor 260 and a resistor 261. An inhibiting tran-
sistor 263 inhibits the switching transistor 259 when
activated by the output disable signal from either of the
booster controller circuits 52 and 54. The in~ector cir-
cuit 50 includes a transformer 262 which in~ects a series
voltage on the center conductor 23 of the transmission
line 22. A current is simultaneously in~ected onto the
center conductor 23 through capacitors 264 and 266. This
in~ection of current and voltage results in a forward-
traveling wave whlch has the same directional properties
as the in~ected voltage and current whlch are in~ected by
the booster circuit 60. That is, the for~ard-traveling
wave components from the current and voltage combine, and
the reverse components cancel out. A pair of transistors
26~ and 270 form a switch which tends to lsolate the
in~ector from the transmission line 22 ~hen the i~-~ector
circuit 50 is inactive.
The in~ector circuit 50 couples a very strong
.~ignal onto the transmisslon line 22 compared to the
booster circult 60. That is, the in~ector circuit 50
must in~ect the full amplitude (approximately 700 milli-
volts) as illustrated in Figure 4. Thus, the in~ector
clrcuit 50 must be strongly coupled to the transmisslon
~ZOS5~
-39-
line 22, and the switch comprising transistors 268 and
270 must allow the coupling to disengage, so that the
inJector circuit 50 does not excessively load the line
when it is inactive. The in~ector circuit 50 further
05 includes capacitors 272 and 274, and resistors 271, 276,
278, 280 and 282.
Figure 13 is a block diagram of the booster
controller circuit 52 of Figure 2, including the part of
the phase locked loop 62 which is not contained in the
integrated circuit which constitutes the booster control-
ler circuit 52.
In the preferred embodiment, the booster con-
troller circuits 52 and 54 are formed by integrated cir-
cuits using CMOS technology and are identical in con-
struction, with only minor variations in the connectionof the input and output. Thus, only the structure of the
booster controller circuit 52 will be described in
detail.
Referring to Figure 13, a receive data decoder
284 receives the receive data signal IRXD from the
booster circuit 60 and selectively inverts the receive
data slgnal IRXD in dependence upon the ROLF input of the
booster controller circuit 52. The receive data signal
IRXD includes the sync pulses shown in Figure 14 and may
also contain data pulses generated by previous sensing
stations 20 (i.e. sensing stations located closer to the
coax termination). The recelve data decoder 284 converts
the receive data signal IRXD to the receive data signal
RXD which is input to various circuits in the booster
controller circuit 52.
A low voltage sensor 286 is connected to the
switching mode regulator circuit 56 and generates a power
on reset signal when the voltage supply to the booster
controller circuit 52 is below a predetermined
~os~
-40-
threshold. The power on reset signal is employed to
reset the logic conditlons in the booster controller cir-
cuit 52 to an lnitial condition.
A booster controller master timlng circult 288
05 is connected to the receive data decoder 284 and receives
the receive data signal RXD therefrom. The booster
controller master timing circuit contains an entire phase
locked loop, and includes the part of phase locked loop
62 (Figure 2). The booster controller master timing
circui-t 288 senses the sync pulses on the receive data
signal RXD and generates a set of timing signals which
are synchronized to the sync pul~ses on the receive data
signal RXD. These timing signals include, in order of
descendlng frequency, bit timing signals, slot timing
signals, subframe timing signals, frame timing signals
and superframe timing signalsO These timing signals fur-
ther include delayed bit timing signals. These timing
signals are transmitted to the various circults in the
booster controller circuit 52.
A mode detector circuit 290 is connected to the
receive data decoder 284 to receive the receive data
signal RXD therefrom, and is connected to the booster
controller master timing circuit 288 to receive delayed
blt timing signals therefrom. The mode detector circuit
290 senses coded information in the sync pulses on the
receive data signal RXD by detecting variations in the
pulse wid~hs of the sync pulses which are sent by the
primary or backup master clock cir~uit 24 or 26. ~ased
on the detected variation in pulse widths, the mode de-
tector circult 290 determines the selected mode and out-
puts mode signals. The various mode signals lnclude idle
vs. data vs. contention frame mode, calibration mode,
signal K, and self test.
~)5~i4~
-41-
A local port interface circuit 292 ls connected
to the signal conditioning circuits 46~and 48 of local
ports l and 2 ~see Fig. l). In addition, the local port
interface circuit 292 is connected to the booster con-
05 troller master timing circuit 288 to receive timingtherefrom and is connected to the mode detector circuit
290 to receive the mode signal. The local port interface
circuit 292 generates clock signals to local ports l and
2 at a frequency which is ~umper selectable (i.e. it may
be set by a programming pad which is external to the in-
tegrated circuit comprising the booster controller cir-
cuit 52) and collects 8-bit data blocks from the local
ports l and 2 at a repetition rate which is also ~umper
selectable. The local port interface circuit 292 pro-
vides a sync pulse on the data I/0 line when it wants toreceive data from the local port. The data I/0 line is a
bidirectional line so that the local data is received by
the local port interface circuit 292 on the data I/0
line. The voltage on the data I/0 line conveys the sync
pulse from the local port interface circuit 292, while
simultaneously the current in the data I/0 line conveys
the data to the local port ~nterface circuit 292. The
local port interface circuit 292 also provides two con-
trol signals to the local ports l and 2 in dependence
upon the mode signal generated by the mode detector cir-
cult 290. The control signals include a CAL signal which
ind~cates that calibration is to take place and a signal
K which may be customized to fit the needs of a particu-
lar system. The control signals CAL and K are conveyed
to the local ports l and 2 by controlling the pulse width
of the sync pulse on the data I/0 line.
A transmission slot controller circuit 294 is
connected to the booster controller master timing circuit
288 to recei~e tlming slgnals~ and to the mode detector
~oss~
-42-
circuit 290 to receive the mode signals. The transmis-
sion slot controller circuit 294 operates during the con-
tention frame mode (indicated by a mode signal) to gener-
ate contention pulses whlch are transmitted through a
05 data handler circuit 296 to the in~ector circuit 50 as a
transmlt data signal TXD2. The transmission slot con-
troller circuit 294 generates contention pulses through-
out the contention frame, while at the same time receiv-
ing the contention pulses from previous sensing stations
20 which are present on the receive data signal RXD. Due
to the directionality of the in~ector circuit ~0, the
receive data signal RXD contains only contention pulses
which are generated by prior sensing stations 20 (i.e.
sensing stations coupled to the transmission line 22 at a
position closer to the coax termination 25~. The trans-
mission slot controller circuit 294 operates on a slot-
by-slot basls throughout the contention frame; that is,
beginning in the first slot of the contention frame, lt
generates a contention pulse and, if no contention pulse
is received on receive data slgnal RXD, then the trans-
mission slot controller clrcuit 294 will claim the first
slot for subse~uent data transmissions. On the other
hand, lf a contention pulse from a previous sçnsing
station 20 ls received on the receive data signal RXD in
the first slot, the transmission slot controller circuit
294 ~111 generate a contentlon pulse in the second slot
in an attempt to claim that~-slot. Thus, the transmission
slot controller circuit 294 generates 1 contention pulse
per slot for each slot in the frame until a slot is
claimed by virtue of generating a contention pulse and
not receiving a contentLon pulse in a particular slot.
Once a slot has been claimed, the tran~mission slot con-
troller circuit 294 will not generate any further conten-
tion pulses.
., .
~c;~
-~3-
As an additional feature? the transmisslon slot
controller clrcuit 294 may be programmed to claim multl-
ple slots ~e.g. 2, 4 or 8) in a frame. If multiple slots
are to be claimed, the slots are uniformly spaced
05 throughout the frame. For example, if the transmission
slot controller circuit 294 i5 programmed to claim two
slots in a frame, it will attempt to claim a first slot
during the first half of the frame, and if it fails to
claim a slot during the first half of the frame, it will
not continue to attempt to claim -its-first -slot during-
the second half of the frame. If the transmission slot
controller circuit 294 is successful in claiming a 510t
in the first half of the frame, it will then remain
silent ~i.e. it will not generate contention pulses)
until the corresponding slot in the second half of the
frame is reached. The transmission slot controller cir-
cuit 294 ~ill emit a single contention pulse in this cor-
responding slot and will claim this slot if no contention
pulse is received on the receive data s~gnal RXD. The
first slot which the transmission slot controller circult
294 attempts to claim is re~erred to as a prime claim and
the transmission slot controller circult 294 repeatedly
transmits contention pulses during the predetermined por-
tion of the frame which ls designated for a prime claim.
The remalning slots which are attempted to be claimed (~f
multiple slots are to be claimed) are referred to as
secondary claims, and only a single contention pulse is
generated in an attempt to claim each secondary claim.
Once the transmission slot controller 294 has
claimed a transmission slot, the transmission slot
address is stored in a register in the transmission slot
controller circuit 294 and a latch is set in the trans-
~ission slot controller circuit 294 to indicate that a
valid transmission slot address has been stored.
-44-
In order to avoid pulse pile-up on the coaxial
cable 22 (i~e., a plurality o~ pulses all being trans-
mitted onto the line at the same time during a slot) the
various sensing stations 20 are pre-wired to vary the
05 location of the contention pulse within a slot for the
particular sensing station. In the preferred embodiment,
there are 9 different types of sensing stations 20 which
are dispersed in the sensor array. The particular type
of sensing station 20 is selected by ~umpers in the sens-
ing station 20, and is indicated by an ID signal gen-
erated by the transmission slot controller circuit 294.
This ID signal controls the location of the contention
pulse within the slot and is further provided to the data
handler circuit 296. Since the sensing stations 20 gen-
erate contention pulses during different times in thetime slot, it is possible for the transmisslon slot con-
troller circuit 294 to receive a contention pulse in the
receive data signal RXD from a prior sensing station 20
before its assigned time for generating a contention
pulse somewhat later in the slot. If a contention pulse
is detected on the receive data signal RXD before the
contention pulse has been generated by the transmission
slot controller circuit 294, the generation of the con-
tention pulse by the transmission slot controller circuit
294 is inhibited9 because the potential for claiming that
time slot has already been negated. This further avoids
any problems due to pulse pile-up on the tr~nsmission
line 22~
The data handler circuit 29~ receives local
port data from the local port interface circuit 292, pro-
cesses the data from the local port interface, adds a
parity b~t, adds an ID bit in dependence upon the ID sig-
nal from the transmission slot controller circuit 294 and
the superframe timing from the booster controller master
~L20SS~
-45-
timing circuit 2B8, and sends out a data burst to the
in~ector circuit 50 as transmit data signal TXD2. The
total data burst ls 18 bits and lncludes 16 data bits,
one parity bit and one ID blt. The ID bit is varied by
05 the data handler circuit 296 on a frame-to-frame basis to
generate a cyclical code, so that if 6 frames in a row
are reviewed, the 6 ID bits can be decoded to determine
the ID of the particular sensing station 20. This ID
information ls used by the controller/receiver 28 to
detect which of the sensing stations 20 remain opera-
tional.
The watchdog circuit 298 detects erroneous
operation by either of the booster controller circuits 52
and 54, and generates an output disable signal in the
case of a malfunction. Thus, the watchdog circuit 298
receives the transmit data signal TXD1 from the booster
controller circuit 54 and checks for corresponding trans-
mission activity during each slot when the transmission
slot controller circuit 294 ls calling for either a con-
tention pulse or data transmiss~on on the transmlt datasignal TXD2. A data transmission slot is indic~ted by
the SNS signal which is generated by the transmission
slot controller circuit 294 and received by the watchdog
circuit 298. A slot in which a contention pulse should
be transmitted is indicated by the CP-GATE signal which
is generated by the transmlssion slot controller circuit
2~4 and received by the watchdog circuit 298. If the
watchdog circuit 298 senses activity from the booster
controller circuit 54 when there is not supposed to be
activity, or if lt does not sense act~vity from the
booster controller circuit 54 when there is supposed to
be activity, the watchdog circuit 298 will generate an
output disable s~ignal.
-46-
Normally, when the transmission slot controller 1,
circuit 294 generates the signal CP-GATE, the booster
controller circuit 54 will generate a contention pulse,
so that the ~7atchdog circuit 298 should be satisfied.
05 However, it should be recalled that the transmission slot
controller circuit 294 can inhibit the generation of a
contention pulse late in a t ime slot if a contention
pulse from a prior sensing station 20 is received early
in the time slot. This could result in the booster con-
10 troller circuit 54 not generating a contention pulse,while the transmission slot controller circuit 294 is
generating the CP-GATE signal. To overcome this dis-
crepancy, the watchdog circuit 298 is also connected to
receive the receive data signal RXD, and during the con-
15 tention frame, the watchdog circuit 298 will acceptactivity on the receive data signal RXD in lieu of
activity on the transmit data signal TXDl. This enables
the r~atchdog circuit 29B to operate properly even though
the booster controller circuits 52 and 54 can inhibit the
20 generation of contention pulses on TXD2 and TXD1, respec-
tively.
A self test circuit 300 ls employed to deter-
mine whether the watchdog circuit 298 is functioning
properly. In general, the self test circuit 300 modifies
25 the inputs to the watchdog circuit 298 from the transmis-
sion slot controller circuit 294. The self test circuit
300 receives the mode signal, the ROLE slgnal, and t iming --
signals. The self test circuit 300 can be actuated to
cause the ~atchdog circuit 298 to look for data transmis-
30 sion in a particular slot or it can mask a slot wheredata should be transmitted to cause the watchdog circuit
to losk for the absence of transmission of data. When
actuated, the self test circuit 300 will cause the watch-
dog clrcult 29~ to detect an error If the watchdog
s~
-~7-
circuit 298 is operating properly, so that the watchdog
circult 298 will generate an output disable signal. The
self test circuit 300 comprises a command decoder which
decodes 4 different self-test commands sent as pulse
05 width modulations on sync pulse No. 4 received in the
receive data signal RXD by the mode detector clrcuit
290. The decoded command signals are sent to the watch-
dog circuit 298 to alter the operation of the watchdog
circuit 298 which will transmit an output disable signal
if it is operating properly.
A soft sync circuit 302 receives the receive
data signal RXD, the timing signals from the booster con-
troller master timing circuit 288 and the mode s~gnal,
and generates a soft sync signal which i5 lnput to the
booster clrcuit 60. The soft sync signal modifies the
threshold for actuating the booster circuit 60, thereby
effectively modulating the booster circuit's response
time to travellng edges on the transmission llne 22.
Th$s modifies the throughput delay of edges in their
transit through the booster circuit 60 and ultimately
tends to keep the edges synchronized on the transmission
line 22. The soft sync circuit 30Z gives the sensing
station 20 the capabLlity of compensating for small time
disturbances in the edges traveling along the transmis-
sion line 22 and maintains the system in a synchronizedconditi~n. The timing signals whlch are recelved by the
soft--sync circuit 302 are employed to alter the booster
circuit's response threshold from a high value to a low
value at the t~me at which a synchronized edge should
arrive. Thus, if an edge arr~ves at the sensing station
20 early9 it encounters a high threshold and the response
of the booster circuit 60 is slow, thereby sllghtly
delaying the edge and pushing the edge toward the ideal
time. Conversely, if the edge arrives late, it
~2i~55~
-48-
encounters a low threshold so that the response of the
booster circult 60 is relatively fast, thereby speeding
- up the edge toward the ideal time.
In the preferred embodiment, the traveling
05 edges are moved by approximately plus or minus one nano-
second at each sensing station 20. The timing signals
which are received by the soft sync circuit 302 indicate
to the soft sync circuit 302 the ideal time at which an
edge should be received. The receive data signal RXD is
input to the soft sync circu-~t 302 because the soft sync
signal must make a low-to-high transition if the booster
circuit 60 is already in the low state, that is, if the
receive data signal RXD is low, whereas the soft sync
signal has to make the opposite transition if the
receive data signal RXD is hlgh. The soft sync signal is
disabled for the passage of the trailing edge o~ each
sync pulse since the sync pulse trailing edges form the
reference timing for the booster controller master timing
clrcuit 288, which is synchronized to these edges. This
allows the sync pulse trailing edges to travel along the
transmission line 22 at what is referred to as native
velocity. Thus, the trailing edges are neither sped up
nor delayed by the soft sync signal. However, the sync
pulses are boosted by the booster circuits 60. Further,
the phase locked loop of the booster controller master
timing circuit 288 is synchronized to this native veloc-
ity and all edges in the system are modified and syn-
chronized to that basic timing through the soft sync sig-
nal.
Figure 15 is a block diagram of the booster
controller master timing circuit 288 of Figure 13 includ-
ing a phase detection and correction circult 304 for tim-
ing acquisition and phase tracking. A charge pump and
filter 306 receives a correctlon signal from the phase
.
-49-
detection and correction circuit 304 and provides a volt-
age to a voltage controlled oscillator 308. The filter
in the charge pump and filter 306 is an active RC filter
having a pole at zero frequency, a zero at a real fre-
05 quency ? and t~o poles at complex con~ugate frequencies.The voltage controlled oscillator is of standard design.
A ~umper selectable prescaler 310 divides the
output frequency of the voltage controlled oscillator 308
by a selected binary number (e.g. 1, 2, 4 or 8) and pro-
10 vides this divided output to a master timing chain 312.The output of the ~umper selectable prescaler 310 is a
clock signal at one and a half times the bit rate~ The
master timing chain 312 includes a divider circuit 314
which generates a clock signal at half the bit rate. At
15 this point ln the booster controller master timing cir-
cuit 288 there are 6 different phases of clock signals on
a timing bus 315. A divider circuit 316 divides the out-
put of the divider circuit 314 by 10 to generate clock
signals at the slot rate; a divider circuit 318 divides
20 the output of the divider circuit 316 by the modulus to
generate clock signals at two times the subframe rate (16
times per frame); and a divider circuit 320 divldes the
output of the divider circuit 318 by 16 to generate clock
signals at the frame rate. All of the timing signals
25 ~i.e.~ the output of the voltage control oscillator 308,
the ~umper selectable prescaler 310, the divider circuit
314, the divider circuit 316,..the divider circuit 318,
and the divider circuit 3~0) are input to the timing bus
315 and can identify any one-third of a bit throughout a
30 frame. Thus, the timing signals can convey timing infor-
mation with a resolution of one-third of a bit. Modulus
computer 31~ provides the divider circuit 318 ~Yith the
appropriate division factor based on the system timing.
~;20ss~ -
-50-
The phase detection and correction circuit 304
includes a frequency correction circuit 328, an acquisi-
tion phase detector circuit 330, a tracking phase detec-
tor circuit 332 and a correction selector circuit 334.
05 The tracking phase detector circuit 332 generates a large
phase error signal (SYM) for input to the tlming acquisi-
tion controller circuit 322, and the acquisition phase
detector circuit 330 generates a very large phase error
signal (PCTL) for input to the timing acquisition con-
troller circuit 3Z2.
The booster controller master timing circuit288 further includes a timing acquisition controller cir-
cuit 322 wh~ch controls the phase detection and correc-
tion circuit 304, the modulus computer 319, and the
divider clrcuits 318 and 320. The timing acquisition
controller circuit 322 is a state sequence machine having
16 states and receives inputs from a coarse frame sync
length resolver 324 (inputs G45, NG38, G38 relating to
bits per frame sync pulse~ and a ~ne frame sync length
resolver 326 (inputs FSN, FSL, FSS relating to fine
resolution of frame sync pulse length). The timing
acquisition controller circuit 322 controls whether the
system is in the INLOCK states or the timing acquisition
states. The timing acquisition process includes a pre-
ceding frequency acqu~sition and a following phase acqui-
sition.
The timing acquisition controller circuit 322,
through its various states, selects which of three sig-
nals will be provided to the charge pump and fllter 306
and hence the voltage controlled oscillator 30~ These
signals are generated by the frequency correction circuit
32~, the acquisition phase detector circuit 330 and the
tracking phase detector circuit 332. The acquisition
phase detector circuit 330 makes timing measurements and
.,
~2~554~
-51-
timing corrections only at a frame rate because it only
measures phase error on the frame sync pulses. In con-
trast, the tracking phase detector circuit 332 measures
phase errors on all of the sync pulses (i.e. 8 times as
05 many as the acquisition phase detector circuit 330). The
tracking phase detector circuit 332 takes over after the
acquisition phase detector clrcuit 330 has reduced the
phase error to a relatively small value. Thus, the
tracking phase detector circuit 332 is able to hold the
phase error to a smaller value because it is making cor-
rections eight times as frequently. During frequency
acquisition, both phase detector circuits 330 and 332 are
turned off while the frequency correction circult 328
generates a frequency correction signal for lnput to the
correction selector circuit 334 which in turn feeds the
correction signal to voltage controlled oscillator 308
via the charge pump and filter 306.
The timing acquisition controller circuit 322,
through its 16 states, also controls the rate of correc-
tion applied by the frequency correction circuit 328,initiallzes and increments and decrements the modulus
computer 319, and presets and clears the dividers 318 and
320 at certain times in the timing acquisition process.
The operation of the timing acquisitlon con-
troller circuit 322 is generally described in Figure
16A. Referrlng to Figure 16A9 the timlng acqu~sition
controller circult 322 initially performs a coa-~se fre-
quency ad~ustment in an attempt to identify the frame
sync pulses (Fig. 14). Since, in the preferred embodi-
ment, a frame sync pulse is 38 bits long, and since noother pulses on the transmission line 22 are longer than
18 bits9 the timing acquisltion controller circuit 322
estimates that any sync pulse above 3~ bits long ~s a
frame sync pulse. During the coarse frequency
~2055~2~
-52-
ad~ustment, the frequency of the voltage controlled
oscillator 308 is ad~usted until the longest pulses are
between 32 and 45 bits long. The timing acquisition con-
troller circuit 322 then sequences to the states for fine
05 frequency ad~ustment. In this process, the frequency of
the voltage controlled oscillator 308 is gradually
ad~usted so that the frame sync pulses converge towards a
38-bit length. At this po~nt, the voltage controlled
oscillator 308 will be running at approximately the cor-
rect frequency;-howeve-r, the modulus (number of slots per
frame divided by 16) will be unknown. Thus, once the
~ine frequency ad~ustment process has taken place, the
timing acquisition controller circuit 322 sequences to
the states for modulus estimation and phase initiali~a-
tion. The phase is inltialized at the beginnlng of aframe, that is, when a frame sync pulse is receiYed, and
the duration of one frame is measured in units of 16
slots. The number of 16-slot increments is counted and
the result is the initial estimate of the modulus. This
estimated modulus is stored and ~he timing acquisition
controller circuit 322 sequences to the states for phase
acquisltion. During the phase acquisitlon process, the
system is operating like a phase locked loop and the
acquisition phase detector circuit 330 is operated until
the phase error in the phase locked loop settles toward
zero~ At this point, the system is capable of measuring
~ths duration of a frame sync pulse with greater precision
and it is determlned whether the modulus estimate is ~n
error. If the modulus estimate is in error, the timing
acquisition controller circuit 322 sequences to the
states for modulus ad~ustment and increments or decre-
ments the modulus estimate by 1, thereby creating a phase
and frequency error in the phase locked loop~ Thus, the
timing acquisition controller circuit 322 is sequenced
~L~055~
-53-
back to the states ~or phase acquisition until the error
is reduced to zero. Once the phase acquisition has been
performed and the modulus determined, the timing acquisi-
tion controller circuit 322 sequences to the INLOCK
05 states, during which the timing acquisition controller
circuit 322 monitors the large phase error signal from
the tracking phase detector circuit 332 for indicat~ons
of loss of phaselock. Normally the system will remain in
the INLOCK state during operation unless there is an
unexpected transient which causes the system to lose
lock. In this case, the timing acquisition controller
circuit 322 will sequence to the appropriate states to,
for example, perform phase acquisition etcO
Figure 16B is a state map for the timing acqui-
sition controller clrcuit 322 illustrating all 16 statesthrough which it can sequence as well as the signals in
the booster controller master timing circuit 288 which
cause state transitions. The double line transitions in
Figure 16B illustrate the normal state transition pat-
tern. From thls map, a set of Boolean equations and alogic circuit can be developed in a straightforward man-
ner.
During the sequencing of the states of the tim-
ing acquisition controller circuit 322, the modulus com-
puter 319 is preset with an initial value and is incre-
mented or decremented until the final modulus value is
deter~ined and the timing acquisition controller circuit ~-
322 goes to the INLOCK condition. At that point, the
modulus computer 319 will contain the correct system
modulus.
Figure 17A is a block diagram of the transmis-
sion slot controller circuit 294 of Figure 13. A
received pulse detector 336 receives the receive data
signal RXD from the receive data decoder 284 (Fig. 13)
-54-
and generates a reGeive pulse signal RXP for each tlme
slot in which a contention pulse is received.
A ~umper selectable multiple slot usage con-
troller circuit 338 indicates the number of slots ~hich
05 the particular sensing station 20 should attempt to claim
during the contention frame by generating a number-of-
slots signal.
A contention frame controller circuit 340 which
is a state sequence machine having 4 states, changes
states on slot boundarles during the contention frame.
Figure 17B is a state map for the contention frame con-
troller clrcuit 340. During the contention frame, the
contention frame controller circuit 340 generates the
CP-GATE signal if the booster subsystem 40 should send a
contention pulse during a slot. If the booster subsystem
40 ls successful in acquiring a required slot or slots
for transmission, the contention frame controller circuit
340 ends up in a predetermined state that indicates that
a transmission slot has been claimed and generates a
valid signal VAL. Thus, the contention frame controller
circuit 340 for~s a speak address status register which
indicates whether the speak address register 354 is
valid.
~ A speak address invalid declarator 34~ resets
the contentlon frame controller circuit 340 under certain
conditions to lts initial state (Figure 17B) whLch is the
starting point for the-eontention frame process. This
initial state indicates that the booster subsystem 40 has
not claimed a transmission slo~ and no valld signal VAL
is generated.
A ~umper selectable ID circuit 344 provides a
four-blt signal ~hich indicates the ID oF the booster
controller circuit 52 and controls the time within the
slot during which the contention pulses are to be gener-
ated.
A contention pulse generator circuit 346 gener-
ates the contention pulses which are transmitted to the
05 inJector circuit 50 through the data handler circuit 296
(Fig. 13). The contentlon pulse generator circuit 346
includes a 9 to 1 multiplexer circuit 348 which receives
timing signals from the booster controller master timing
circuit 288 and receives the ID signal from the ~umper
selectable ID circuit 344. The multiplexer 348 selects
one of nine di~ferently phased clock signals from the
timing bus 315 and generates a selectable phase slot rate
clock signal as an output. An edge detector circuit 350
detects an edge on the output of the multiplexer 348 and
generates a pulse which is used as the contention pulse.
A contention pulse gate 352 passes the pulse from the
edge detector circuit 350 as the contention pulse when
the gate signal CP-GATE is generated by the contention
frame controlIer circuit 340, and when no received pulse
20 is detected by the received pulse detector 336. ~¦
Once a transmission slot has been claimed by
the booster subsystem 40, the address of the transmission
slot is stored in a speak address register 354 which com-
pr~ses a 9 bit register. ~he speak address register 354
ls strobed for each slot in the contentlon frame under
the control o~ the contention frame controller circuit
340 until a transmission slot is claimed.
A speak time indicator circuit 356 is a 9-bit
equality detector which compares two 9-bit words and
generates a speak-next-slot signal SNS when the two 9-bit
words are equal. One of the 9-bit words is a~next slot
number whlch is part of the timing signals generated by
the booster controller master timing circuit 288 and the
other is provided by the address stored in the speak
~l2q:~SS~
-56-
address register 354. The speak time indicator circuit
356 inhibits generating ~ignal SNS when the contention
frame controller circuit 340 is not generating the VAL
signal.
05 Figure 18 is a block diagram of the data han-
dler circuit 296 of Figure 13 and includes a pair of
serial-parallel shift registers 358 and 360 and a pair of
parallel-serial shift registers 362 and 364. The
serial-parallel shift registers 358 and 360 receive
serial data from the two local ports via the local port
interface circuit 292. The parallel-serial shift regis-
ters 362 and 364 periodically strobe data fro~ the
serial-parallel shift registers 358 and 360, respec-
tively, and shift the data out serially to a transmit
data synchronizer circuit 366. A parity generator 368
generates a parity bit by performing an EXCLUSIVE OR
operation on the serial data bit outputs of the
parallel-serlal shift registers 362 and 364. For exam-
ple, the second bit is EXCLUSIVE OR'd with the first bit
to obtain a first result, the thlrd bit is EXCLUSIVE OR'd
with the first result to obtain a second result..., and
so on, until a parity bit is generated and input to the
transmit data synchronizer and buffer circuit 366.
A cyclical code generator 370 receives the ID
signal from the ~umper selectable ID circuit 344 and gen-
erates a coded ID bit which is merged ~ith the output
data by the parallel-serial shift regist~r 364. ~he ID
code bit changes on a frame-to-frame basis, and over a
sequence of 6 frames ~he sequence of blts uniquely iden-
tlfies the ID tl of 9) of the sensing station 20. Thus,the coded sequence of 6 bits is used by the controller/
receiver 28 to determine the IDs of each of the sensing
stations 20 in the array. The cyclical code generator
370 comprises a multiplexer and some combinatorial logic
~.2~5S~L~
-57-
circ~its. The multiplexer selects one of slx comblna-
torial functions of the ID inputs from the ~umper select-
able ID circuit 344 in accordance with the frame number
in the superframe, as conveyed by timing signals from the
05 booster controller master timing circuit 288. There are
six frames per superframe. Thus, there are 64 possible
codes which can be conveyed with the 6-bit sequence.
However, in the present embodiment only 9 of these codes
are used7 and they are designed so that they can be
decoded correctly even if the 6-bit sequence is shifted
cyclically.
The transmit data synchronizer circult 366
merges the local port data, the par~ty bit, the ID code
bit and the contention pulses to generate the transmit
data signal TXD2 which is input to the in~ector circuit
50.
Figure 19 is a block diagram of the watchdog
circuit 298 of Figure 13. The transmlt gate generator
372 generates a transmit gate signal-TX GATE which is
high for an 18-bit period plus a fraction of a bit on
each end. Thus, TX GATE is high for 19 bits and is cen-
tered on the 18-bit region on a slot where activity is
allowed. There are always two bits in a slot that are
termed guard band bits in which there should be no activ-
ity. The tlme period of the transmit gate signal TX GATEshould coincide wlth any activity on the transmit data
signal TXDl si~ce the TX GATE signal is on for one half
bit before and after the 18-bit period. The transmit
gate signal TX GATE is generated as a function of (1) the
speak-ne~t-slot signal SNS generated by the speak time
indicator circult 356 which indicates that data should be
transmitted in the next slot and (2) a contentlon gate
signal CP-GATE which indicates that a contention pulse i5
to be generated. Normally, the TX GATE signal is
~Z055q~
-58-
generated in response to either of the above signals.
The transmlt gate generator 372 is also connected to the
self test circuit 300 which provides an input to cause
the TX GATE signal to go low or high abnormally, and
05 ultimately to cause the watchdog circuit 298 to generate
an output disable signal.
A violation detector 374 receives the TX GATE
signal as well as the transmit data signal TXDl from the
booster controller 52, the mode signal from the mode
detector circuit 290, and the receive data signal RXD
from the receive data decoder 284 (Fig. 13~. During the
data mode, the violation detector 374 compares the TX
GATE signal with the transmit data signal TXDl and if
there is a violation, a violation signal is generated. A
violation occurs when either the transmit data signal
TXDl is inactive for an entire time slot when lt should
be active, or when the transmit data signal TXDl is
active in a slot where it should not be active. During
the contention frame mode, the violation detector also
considers the receive data signal RXD a~ an input to
compensate for the fact that during the contention frame,
the contention pulse is sometimes omitted to avoid pulse
pile-up, thereby resulting in a lack of activity on the
transmit data signal TXDl. Durlng the data mode, there
is no reason to expect that ~Dl should be inactive for
an entire 18 bits during the claimed data transmission
slot. This is because the parity generator 368 (Fig.-18)
imposes odd parity so that the number of active bits is
always odd. Therefore, there must always be at least one
active bit on transmit data signal TXDl in any slot where
data transmission is called for.
A temporary inhibit controller circuit 376
includes a bit counter which counts down from the super~
frame timing signal, so that a single violation results
~L2~;)55~L
59
in a temporary inhibit signal whlch lasts for approxl-
mately 3000 frames. Normally, thls is enough time for
any minor problems in the system to be resolved and for
normal operation to resume. However, if the malfunction
05 ls more serious, a permanent inhibit controller circuit
378 detects repeated violations and when three violations
spread over a substantial time frame have been detected,
a latch is set which generates a permanent inhibit sig-
nal. The permanent inhibit latch is immedlately set by
any violatlon detected in a contention frame. An OR gate
380 ORs the temporary inhibit signal and the permanent
inhibit signal to generate the output disable slgnal.
Figure 20 i5 a block diagram of the soft sync
circuit 302 of Figure 13. The soft sync circuit 302
includes inverters 382~ 384 and 386, and transmisslon
gates 388, 390 and 392. In general, the generation of
the soft sync signal is a function of the receive data
signal RXD and involves inverting and delaying the
receive data signal RXD. The transmission gate 388 is
employed to create a short term memory of RXD as its out-
put, and the transmission gates 390 and 392 are opened
and closed to transmit a true or inverted value of this
signalO That is, at the output of the transmission gate
388 there is some small capacitance to ground which is
inherent in the input of the inverter 384 which it
drives. When the transmission gate 388 opens, the volt-
age at its ~utput remains at its previous logic level for
a brief perio~ of time~ The transmission gate 388 is
regularly closed once per bit and opened once per bit;
thus the storage in the output capacitance is held for a
fraction of one bit. When the transmission gate 388 is
opened~ it is opened near the middle of the bit time so
that the value stored at the output of the transmission
gate 38B represents the data value on the transmission
~205S4~
-60-
line 22 in that bit period. That data value is lnverted
by the inverter 384 and transmitted through inverter 386
and through transmission gate 390 or transmission gate
392. Thus, the transmission gates 390 and 392 select
05 either an inverted or noninverted version of the stored
data bit. ~ust prior to a bit boundary, the transmis-
sion gate 390 is closed, the transmission gate 39? is
simultaneously opened and the soft sync signal changes
state at the bit boundary. When the transmission gate
392 opens and the transmiss~on gate 390 closes, the soft
sync signal changes from the inverted value of the stored
data bit to the true value of the stored data bit.
The transmission gates 388, 390 and 392 are
opened and closed by a timing generator 398 in response
to an enable signal from a soft sync enable circuit 400
and ~n response to the timlng signals provided by the
booster controller master tIming circuit 288~ The timing
signals employed by the timing generators 398 are those
output by the divider circuit 314, have 6 different
phases, and are at half the bit rate. Thus, the soft
sync signal Ls provided to the booster circuit 60 as
elther a rising or a falling loglc transltion which is
synchronlzed to the timing signals generated by the
booster controller master timing circuit 288.
The soft sync enable circuit 400 is used to
disable the soft sync circuit 302 by holding the trans-
mission gates 390 and 392 open to allow a sync pulse
trailing edge to transmit through the system without the
soft sync signal acting upon lt. When a sync pulse is
being passed through the system, the soft sync slgnal is
dlsabled (i.e. transmission gates 390 and 392 are both
opened) and the soft sync signal floats to a halfway
level which is governed by resistors 394 and 396. The
soft sync enabLe circult ~01) also receives the INLOCK
~S543L
-61-
signal from the booster controller master timing circuit
288 and if the system is nGt in phaselock9 the soft sync
enable circuit 400 disables the soft sync circuit 302.
Figure 21 is a block diagram of the primary
05 master clock 24 of Figure l. It should be noted that the
construction of the backup master clock 26 is the same as
the primary master clock 24 except for minor differences
in the external connection of the disable input and out-
put. A switching mode regulator circuit 402, which is
the same as the switching mode regulator circuit 56
lllustrated in Figures lO and ll, couples power off the
center conductor 23 of the transmission llne 22 and con-
verts it to supply voltage for use within the primary
master clock 24. The switching mode regulator circuit
402 also provides the command tones which are transmitted
on the transmission line 22 by the system power and con-
trol subsystem 27 to a mode controller circuit 404. A
crystal oscillator 40~ furnishes ~ frequency related to
the bit rate to a sync pulse generator-circuit 408.
Thus, the crystal oscillator 406 is used to establish the
system bit rate.
The sync pulse generator circuit 408 generates
sync pulses unless it is inhibLted by an inhibit input,
and the pattern of sync pulses generated by the sync
2~ pulse generator circuit 40B is the pattern oF 8 sync
pulses described above with respect to Figure 14 of the
drawings. In the preferred embodi-~ent, the sync pulse
generator circuit 408 is implemented by counters which
count the number of bits in a slot and the number of
slots in a frame. Thus, the sync pulse generator circuit
408 sets up the frame tlming for the booster telemetry
system of the present invention. As further noted above,
the length of some of the sync pulses in the frame can be
modulated ln dependence upon the MODE slgnals frcm the
., i
L3ZO~
-62-
mode controller circuit 404 to indicate to the sensing
stations 20 that the contention frame is approaching or
that calibration is to take place, or to indicate various
other mode functions to the senslng stations 20.
05 The mode controller circuit 404 provides a mode
signal MODE to the sync pulse generator circuit 408 in
dependence upon the command tones provided through the
switching mode regulator circuit 402 and in dependence
upon power-up of the system. In particular, when the-
power is turned on, the system enters the idle mode. The
mode controller circuit 404 generates a calibration mode
signal as a function of the command tones which are
received through the switching mode regulator circuit
402. A fixed time after the power is turned on, the
system enters the data mode and this is the normal oper-
ating state of the system. Thus, the mode controller
circuit 404 controls the sync pulse generator circu~t 408
so that it operates to produce the sync pulses in a nor-
mal manner, and the sync pulses are provided to an in~ec-
tor circuit 410 which in~ects the sync pulses onto thetransmission line 22. The in~ector circu~t 410 may be of
the same construction as the in~ector circuit 50 illus-
trated in Figure 12 of the drawings. Alternatively, a
non-directional in~ector circuit as illustrated in ~igure
23 may be e~ployed as the in~ector circuit 410. The mode
controller clrcult 404 ln the backup master clock 26 also
-~ responds to the long command tone which indicates switch-
ing of the system to the backup master clock 26 by
enabling the sync pulse generator circuit 40~ and the
in~ector circuit 410 in the backup master clock 26 and by
providing a disable input to the primary master clock 24,
thereby switching the system to the backup master clock
26.
~2~554~
-63-
In the preferred embodiment, the sync pulse
- generator circuit 408 and the mode controller circuit 404
are implemented as a single integrated circuit. Figure
22 is a block diagram of the preferred embodiment of the
05 integrated clrcuit including the pulse generator circuit
408 and mode controller circuit 404.
The mode controller circuit 404 includes a
flip-flop 428 which determines whether the system is in
the INIT (idle) mode or the RUN (data) mode. A power on
reset circuit 426 resets the flip-flop 428 to an INIT
state and resets the INIT mode timer/command length timer
416. The INIT mode timer/command length timer ~16 counts
frames during the INIT mode and counts command tone burst
cycles during RUN mode. During the idle mode, a clock
input at the frame rate is received by the INIT mode
timer/command length timer 416 from a frame divider 430
in the sync pulse generator clrcuit 408. The frame rate
signal advances the counter one count per frame until the
terminal count is reached, at which point the flip-flop
428 is set to the RUN state. In the preferred ~mbodi-
ment, this will take 2048 frames. After the RUN state
has been achieved, the operation of a command tone
envelope detector 414 and corresponding circuitry for
detecting the command tones comes into play.
The mode controller circuit 404 further
includes a bandpass filter/comparator 412 which is con-
nected to receive the command tones via the switchin~
mode regulator circuJt 402. The command tone envelope
detector 414 receives the filtered signal from the band-
pass fllter/comparator 412 and generates a high-level
output as long as the command tone persists. The INIT
mode timer/command length timer 416 counts the tone in
terms of cycles until the command tone stops. When a
command tone begins, there is an onset during which the
~ss~
-64-
command tone envelope detector 414 has not yet responded
~ and an onset detector 418 causes the INIT mode timer/
command length timer 416 to be reset. The INIT mode
timer~command length counter 416 is then readv to count
05 once the output of the command tone envelope ~etector 414
goes high. When the command tone ends, the ~alue from
the INIT mode timer/command length timer 416 is sent to a
command decoder 420 which provides a length signal in
dependence upon the command tone length. A command latch
circuit 422 includes latches A and B which change state -
in response to the length signal provided by the command
decoder 420. Thus, if the command tone length is in a
particular window, the length slgnal will cause latch A
to change state, while if the command tone length is in a
different window, the length signal will cause latch B to
change state; if it is outside both of the designated
windows, neither latch will change state. Latch A sup-
plies the signal CAL which is an output to the sync pulse
generator 408 designating ~hat the controller/receiver 28
has called for a calibration operation, while latch B is
connected to an active pulldown 424. In the ¢ase of-the
primary master clock 24, when latch B changes state
nothing happens because the output of the active pulldown
424 is externally wired to ground. However, in the case
of the backup master clock 26, the active pulldown 424 is
wired to the primary master clock 24 and the result is a
short clr~uit on the power supply of the primary master
clock 24, forcefully disabling the primary master clock
24, and disinhibiting the in~ector circuit 410 and the
sync pulse generator 408 ln the backup master clock 26,
enabling the backup master clock 26 to begin operation.
The power on reset circuit 426 resets both of the command
latches in command latch circuit 422 to zero when power
is turned on.
~Z0554~
-65~
The sync pulse generator 408 includes an oscil-
lator 432 ~hich generates a stable frequency. A ~umper
selectable prescaler 434 divides the stable frequency by
a selected power of two to generate a clock signal ~hich
05 is provided to a subframe dv~der circuit 436. The sub-
frame divider circuit 436 divides the output of the
Jumper selectable prescaler 434 by a multiple of the
modulus so that one sync pulse may be generated per sub-
frame, that is every time the subframe divider circuit
436 cycles through its count. In practice, a sync pulse
leading edge is generated at a variable time and always
ends at the terminal count of the subframe divider cir-
cuit 436, so that the end of the sync pulse is regular in
time, from sync pulse to sync pulse. The frame divider
circuit 430 divides the output of the subframe divider
circuit 436 by 8 to obtain a three-bit word that indi-
cates whlch subframe the system is in. This three-bit
word is provided to a pulse length controller circuit 438
comprising a multiplexer which scans across its a inputs
~0 at the rate of one input per subframe under the control
of the frame divider circuit 430. Each of seven inputs
to the multiplexer in the pulse length controller circuit
438 corresponds to an ~ndividual sync pulse in the frame
and controls the length of the corresponding sync pulse
?5 in the frame. The length of the eighth sync pulse is
fixed to provide a fixed length ~rame sync pulse. A
superframe divider circuit 440 advances one count per
frame and is a variable modulus divider. The superframe
divider 440 can be selectively set to cycle through n
frames, where n is an integer from 2 to 8. At its termi-
nal count, the superframe divider 440 generates a signal
which is input to the pulse length controller circuit 438
to be used to generate signal K in the booster subsystem
~20S~
-66-
40. If slgnal K i5 not to be used, the superframe
divider circuit 440 can be disabled.
As noted above, the pulse length controller
circuit 438 has 7 inputs which control the lengths of the
05 7 sync pulses in a ~rame. The correspondence between the
multiplexer inputs/sync pulses, the elements of the sync
pulse generator circuit 408 and the mode controller cir-
cuit 404 and the information conveyed by the pulse, are
set forth below:
Multiplexer Input No./ Connected Element -
Sync_Pulse No. Information
1 Flip-flop 428 - Idle Mode
2 Command Latch Circuit 42Z -
CAL mode
15 3 Superframe divider 440 -
Signal K - Custom mode
4 Input X on Sync Pulse
Generator 408 - Used for
Controlling Self Test
Input Y on Sync Pulse
Generator 408 - Purpose Open
6 Counter input to INIT mode
timer/command length
timer 416 - used for per-
formance monitoring by con-
troller/receiver 28 of band-
pass filter/comparator 412
25 7 ~OLE - distinguishes the
backup vs. the primary mas-
ter clock to the controller/
-................................. receiver 28
A controllable length pulse generator 442
comprises combinatorial logic to generate three sync
pulse leading edge positions, with its inputs connected
to the subframe divider circuit 436~ and the outputs of
the pulse length controller circuit 438. A final
120554~
synchronizer circuit 444 comprises a flip-flop which is
cleared at the terminal count time of the subframe
divider circuit 436 and which is set by the output of
the controllable length pulse generator 442. The final
synchronizer circuit 444 generates the sync pulses
which are injected on the transmission line 22 by the
injector circuit 410.
The operation of the telemetry system will be
described with reference to Figures 1, 2, 7, 13, 17A,
21 and 22. After the sensor array has been arranged in
the desired position, the system power and control sub-
system 27 ~Figure 1) will turn the system power on and
the process of initializing the system begins. When
power is turned on, the power on reset circuit 426
(Figure 22) will reset the INIT mode timer/command
length timer 416, the flip-flop 428 will be reset to
its INIT state and the system will enter idle mode
until the timer 416 reaches..its terminal count. The
sync pulse generator circuit 408, upon power-up, begins
to generate 8 sync pulses per frame, by employiny the
jumper selectable prescaler 434, the subframe divider
circuit 436, the frame divider circuit 430, the pulse
length controller circuit 438, the controllable length
pulse generator 442 and the final synchronizer circuit
444.
When the pulse length controllex circuit 438
receives the INIT signal at one of its inputs, it trans-
mits a signal to the controllable length pulse generator
442 so that sync pulse 1 (Figure 14) ~the first sync pulse
in the frame) is modulated to indicate to all of the
sensing stations 20 (Figure 1) that the system is in the
idle mode. As noted above, the INIT mode timer/command
length timer 416 (Figure 22) is reset to zero by the power
on reset circuit 426 and begins to count upward until it
reaches approximately 2048 frames. When the
~L20S54~
-68-
full count is reached, the INIT mode timer/command length
- timer 416 resets the flip-flop 42~ and sends a signal to
the pulse length controller circuit 438 to indicate that
the system is entering the data mode. The pulse length
05 controller circuit 438 controls the length of sync pulse
No. 1 to indicate to the sensing stations 20 that the
system is in the data mode and that the contention frame
is approaching. Other inputs to the pulse length con-
- troller circuit 438 are directed to the response to com-
mand tones being sent by the system power and control
subsystem 27 (Figure 1). These command tones are
detected in the mode controller circuit 404 ~Figure 21)
which generates the appropriate inputs (e.g. C~L to the
pulse length controller circuit 438) to indicate, for
example, that the system is to enter a calibration mode.
Assuming the primary master clock 24 (Flgure 1) is the
master clock selected for operation, the primary master
; clock 24 will receive a command tone through its switch-
ing mode regulator circuit 402-(Figure 21). The mode
controller circuit 404 receives the command tone from the
switching mode regulator 402 and detects the onset of the
command tone through its onset detector 418 (Figure 22).
When the system enters the data mode, sync
pulse No. 1 is modulated in length, and the next frame
sync pulse (sync pulse No. 8) which is received by the
sensing stations 20 indicates that the contention frame
is beginning, thereby causing the booster c~ntroller cir-
cuits 52 and 54 to attempt to claim a slot or slots for
data transmission (Figure 2). It should be noted that
during the idle mode9 and during all subsequent normal
operation, the sync pulses are received by the booster
subsystem 40 through the booster circuit 60 and are
transmitted to the booster controller circuits 52 and 54
as a receive data signal IR~D. The booster controller
~21~;5~-~
-69-
master timing circuit 288 (Figure 13) generates the tim-
ing signals for operation of the booster controller cir-
cuit 52 on the basis of the decoded IRXD signal which is
the receive data signal RXD. The mode detector circuit
05 290 detects the mode on the basis of the length of the
sync pulses and generates a mode signal indicating the
mode in which the system is operating. When the system
enters the data mode and the contention frame occurs, the
transmission slot controller circuit 294 generates con-
tention pulses by its contention pulse generator circuit346 (Figure 17A) in dependence upon the slot timing
determined by the booster controller master timing cir-
cuit 288 (Figure 13). The transmission slot controller
circuit 294 generates contention pulses until lt gener-
ates a contention pulse in a slot during ~hich no conten-
tion pulse has been received on the receive data signal
RXD. When this occurs, the transmission slot controller
circuit 294 claims this slot and the contention frame
controller circuit 340 causes the -address of this slot to
be stored in the speak address register 354. If the sys-
tem is operating properly, each of the sensing stations
20 will claim a slot for transmisslon during the conten-
tion frame and will store their claimed slot in their
speak address register 354.
During and prior to the contention frameS the
system has been collecting digital data from the local
port-s and discarding it. After the contention frame,
local digital data received by the booster controller
clrcuit 52 ~rom the local ports is transmitted to the
injector circuit 50 in the transmit data signal TXD2 dur-
~ng the claimed.time slot for the particular sensing sta-
tions 20, for in~ection onto the transmission line 22 by
the in~ector circuit 5D (Figure 2). During the operation
of the system in the data mode, the primary master clock
-70-
24 contlnues to generate sync pulses in order to maintain
the system timing. The sync pulses and the digital data
which are in~ected onto the transmission line 22 are both
boosted by the booster circuit 60 located within the boo-
05 ster subsystem 40. The coupling network formed by thetransformer 70 and the resistor 72 senses the current in
the center conductor 23 of the transmission line 22
(Figure 7). A second coupling network, formed by the
capacitors 74 and 76, and the resistor 78, senses the
voltage on the center conductor 23 of the transmission
line 22. First and second s~itching networks are formed
by the transistors 80 and 82 and the transistors 86 and
88. The flow of current through each of the transistor
switching elements is reversed when an edge is detected
on the trans~ission line 22. ~hen the transistors 80 and
82 switch, the switching causes a voltage to be generated
at the upper winding of transformer 70, and when the
transistsrs ~6 and 88 switch, there is a coupling from
the collector output on the transistor 88, through the
capacitors 74 and 76, onto the transmission line 22,
thereby providing the flow of current onto the transmis-
sion line 22. The combined effects of the voltage and
current in~ected onto the transmission line 2~ cause the
digital data signal on the line to be boosted. The soft
sync signal which is generated by the soft sync circuit
302 (Figure 13) in the booster controller circuit 52
tends to move the edges of the signal to be boosted in .
order to maintain proper timing in the system. The soft
sync slgnal is coupled into the base of the translstor 80
without any inversions. Prior to a bit boundary, the
logic level of the soft sync signal is opposite the
receive data signal RXD. This causes the voltage dif-
ference between the bases of transistors 80 and 82 to be
larger than average, so that the threshold for causing
.
~ZOSS4~
-71-
switching of the current flow through these transistors is
larger than normal. At the bit boundary, the soft sync signal
changes logic levels so that it is the same as the receive data
signal RXD, thereby reducing the voltage difference between the
bases of the transistors 80 and 82, and encouraging switching
of the transistors by reducing the threshold. It should be
noted that the soft sync signal is disabled for sync pulses so
that the system timing can be maintained. Thus, while the sync
pulses are boosted by the booster circuit 60, the edges of the
sync pulses are not moved in accordance with the soft sync
signal.
The system described above having the power supply
circuit may be implemented in numerous ways. For example, the
system may be employed in various types of sensing arrays to
transmit and boost digital data signals on a transmission line.
The system may be used in a sea water environment for
detecting other vessels and for purposes of exploring for oil
in the ocean floor. Further, the telemetry system may be
employed on land by dispersing the sensing stations 20 at
various points and by detecting either natural events (e.g.
seismic detection) or looking for oil deposits using sound wave
techniques. Further, the booster circuit may be implemented by
any negative impedance bistable device or circuit and may be
employed with any type of electronic transmission line. The
booster circuit is suitable for any number of applications in
the field of telemetry and~ more generally, for boosting
digital data signals which are transmitted on a transmission
line connecting, for example, two or more computers. The
booster circuit has industrial ~nd commercial remote control
applications and may be used in scientific data gathering
systems.
;
S~
-72-
The many Features and advantages of the lnven-
tion are apparent from the detailed specification and
thus it is intended by the appended claims to cover all
such features and advantages of the system which fall
05 within the true spirit and scope of the invention. Fur-
ther, since numerous modifications and changes will
readily'occur to those skilled in the art, it is not
desired to limit the invention to the exact construction
and operation shown and described and, accordingly, all
10 suitable modifications and equivalents may be resorted
to, falling within the scope of the invention.
