Note : Les descriptions sont présentées dans la langue officielle dans laquelle elles ont été soumises.
~IGITAL CLOCKING AND DETECTION SYSTEM FOR A DIGIThL STORAGE SYSTEM
BACXGROUND OF THE INVENTION
This invention relates to data clocking and detection
for digital da~a storage systems such as tape drives and more par-
~icularly, to an improved digital data clocking and detection system.
When stored digi~al data is played back ~rom a data storag~
system~ such as a magnetic tape or disk system, it is necessary to
de~ermine bo~h the frequency and the phase of the transitions in
the played back signals. In magne~ic tape storage the data is
typically stored in nine tracks which contain ~ransitions representi
ones and zeroes making up digital data words. ~ separate clock
track i5 not normally recorded~ From the played back data itself,
the proper clocking must be determi~ed in order to d*f i ne the
limits of the bit cells in ~ach ~rack.
Since the speed of the magnetic medium upon which he
data is recorded may vary slightly, the $requency of the clock
pulses d~finin~ the edges o the bit cells which are read from the
medium must be varied to match these changes in speed. It is
common practice ~o pr~vide a voltage controlled oscillator ~V.C~O.)
which tracks the detected transitions in order ~o provide clock
pulses having a frequency which varies as the velocity of the
magnetic medium changes. Providing proper clo~king by itself is
no~ sufficiPnt~ the pha~e o~ the dete~ted transitions with respect
to the clock pulses must also be detPcted. The two types of commonl~
used magnetic tape recording systems are ANSI Standard phase en-
coded (P~) and ANSI Standard GCR recording. In PE recording there
is a}ways a transition in the middle of a bit cell and sometimes
there is a transition at the edge o~ a bi~ cell. In GCR recording,
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if a bit cell has a transition ~t is in the middle, not at the edge
of the bi~ cellO Not all GCR bit cells have transitions. In
order to properly determine whether the recorded bit is a one or
zero, ~t is necessary for the data detection circuitry to have
phase in~ormation which defines whether or not a transition occurs
in a given bit cellO
Most prior art PE and GC~ tape subsystems ha~e used
analoy phase locked loops and analog da~a detection circuits for
each track. U.S. Paten~ No. 4,109,236-~esenfelder shows a digi-
tal circuit for clocking and detection. IBM Technical Dislcosure
Bulletln ent~tled ~DIGITAL PHASE ER~O~ DET~CT~U by L. Taber,
Vol. 23, No. 11, April, 1981 shows a digital phase detector.
In the prior art a phase ~ocked loop and associated`
circui~ry are provided for each data track. This is expensive
because it re~uires a controlled oscillator for each track. There
is another problem associated with this approach which is particu-
larly prevalent in high density recording such as is currently
practiced ~ith GCR. In such recording a string of bit cells fre-
~uently occurs with no transitions. Because of the high density,
and the nature of the medium, the transitions at the edge of this
string are often shifted so that the transitions appear as a pha~e
error. This incorrectly ~hifts the frequency of the controlled
oscillator in an attempt to compensa~e or the apparent phase
error in ~his track.
It is an object of ~he present invention to provide
a digital data clocking and detection system in which a common
controlled oscillator ~s used to provide the clock pulses for all
tracks thereby effecting a cost reduction.
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It is also an object o~ this invention to provide a
digital data clocking detection system which reduces the sensi-
tivity to the high density packing problem described ~bove.
It is also an object of the present invention to
provide aigital data and phase detection circuitry which replaces
the analog circuitry normally associ~ted with th~se functions.
It is an object of the present invent1~n to compensate
for large errors in phase by changing the count in the phase
counter associated with that track, whereas smaller phase errors
are compensated by controlling the frequency of th~ controlled
oscillator. In this manner, phase devlatlons, ~uch as
caused by skewO are compensated for in each individual tra~.
It is an object of the pr~sent invention ko provide
data and phase de~ecting circuitry in which dropou~ recovery is
enhanced.
.
SUMMARY OF THE INVE~TION`
,
In accordance with the present invention, a data
clocking and detection system ~or a digital data storage
5~stem includes a common controll~d oscillator producing he
clock pulses applied to the phase detectors for all of the
multipl~ tracks. The phase detector for each track includes
a binary counter which counts multiple, 1~ nominally in the exampl~,
clock pulses for each bit cell. The phase error of the transition
in the played back data is determined with respect to the count in
the counter. If the transition occurs in a range of coun~s just
prior to or just after the center of the bit cell, counts 4-7 and
8-11 in the example, a correction output representing the magnitude
of the phase error is applied to he common controlled oscillator.
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s
If the magnitude is greater, falling in the ranges of
counts 0-3 and 11-15 in the example, a correction is applied to
the oscillator as described abov~ and, in addition, a phase correc
tion is made by changing the count in the digital counter. For
exampl~, when the data transition falls in the count range 0-3, a
~ount is subtracted rom the counter and if it occurs in the range
of 11-15 a count is added to the counter. In this way, the counters
for the various tracks are adjusted differently, one with respect
to ~he other in order to accommodate skew between the ~racks.
In accordance with another ~s~ec~ of the invention,
~he correction output which is appli.~d to ~on~rol the common
controlled oscillator has a pulse wid~h proportional to the
.magnitude of the phase error. Alternatively, the correction
signal may be a fixed width pulse indicating only the polarity
of the phase error. ~n either case, the correction inforn~a~ion
from all tracks àre combined and applied to correct the 05cil-
lator.
In accordance with the invention the controlled
oscillator ~ircuitry provided for each track in the prior art
is replaced ~y a single oscillatorO This effects a cost savings
and it al50 reduoes the problem o~ erroneou~ correction o the
controlled oscillator ~VCOI saused by bit crowding. By separately
correGtin~ the individual counters in each phase dete~tor, and
commonly correc~ing the VCO, the data clocking and detection system
~5 o the present invention provides good tracking of transient varia-
ions in dat~ frequency (media velocity) a~d also provides good
tracking of longer term phase changes, such as caused by tape
and head skew~
s~
The foregoiny and other objects, features and advantag~s
of the invention will be better unaerstood frsm the following more
detailed description and appended claim~.
SHORT DESCRIPTION OF T~E DR~WING5
_ _ _ . _
~ig. 1 depicts the prior ~rt use of a separate
VCO f~r each track of the storage system;
Fig. 2 depicts the data clocking and detec~ion
system of the present inven~ion;
Fig. 3 depicts the phase detector of th~ present
invention~
Fig~ 4 depicts the data de~ector of the present
invention;
Fig. 5A - 5H and SA-6G show wave form~ and more parti-
cularly: .
FigO 5A depicts the GCR data;
Fig. SB is the most significant bit of the phase
counterS
Fig. SC shows the correction up signal,
~ig. SD shows the correction down signal;
Fig. 5E shows the output o the da~a integration
counter;
~ig. 5F shows th~ NRZ data for one track;
Fig. 5G shows the clock which is synchronized with
the data;
~ig. SH ~hows a phase ~rror poin~er;
Fig. 6A shows the clock output of the VCO;
Fig. 6R shows GCR data or one track;
Fig. 6C shows the most significant bit of the phase
counter for that track;
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Fig. 6D depicts the phase count ~or that trac~;
Fig~ 6E depicts GC~ data or ano~her tra~k~
Fig. 6F shows the most ~ignificant bit of the phase
counter for the other track; ~n~ .
Fig. 6G depicts the phase count for the other
track.
DESCRIPTION OF THE PREFERRED EMBODIME~
~ig~ 1 shows the prior art dhta clocking and detection
systems for detec~ing data played from a plurality of tracks, two
lQ tracks being shown in FigD 1. Typically, magnetic tape drive
.systems record data in nine tra~ks ~n a PE or GCR format~ Trans-
it~ons in the played back data are detected by edge detectors 11~
Phase detectors 12 deSect the phase of the transitions with respeot
to clocX pulse~ which define the bit cells in which the transitions
occur. A controlled oscillator ~VCO) 13 produces these clock
pulses. The outputs of the phase detector~ 12 are applied to filte~
14 which produce a voltage which controls oscillators 13. The
clo~k pulses are used in ~he detection of data by data detectors
15 which produce a nonreturn to ~ero output together with a
clock which defines the bit c~lls of the dataO
In accordance with the present invention shown in Fig. 2,
a common con~rolled oscillator 16 produces clock pulses for the
phase detector~ 18 for all nine tracks. The played back tracks of
data are applied to edge detectors 20 which detect the transi~
tions representing data, If these ~ransitions occur, they ~hould
occur in the middle of the bit cells. These transitions and the
clock pulses from the VCO 16 ar~ applied to the phase detector 18
which produces a correction output r~presenting the phase error
s
of the transition with respec~ to the clock pulses defining the
bit cell~ If the transition occurs early, before the center of
the bit cell, ~ CORRECTION UP outpu~ is produced, if the transition
occurs la~e~ after the middle of the bit cell, a CORR~CTION DOWN
output is produced. The sorrection outputs of the phase detectors
are combined in the OR gates 22 a~d 24. All nine of ~he correction
up signals are combined $n OR gate 22 to produce a signal which is
filtered in ~ er 26, and applied to VCO 16 to ~ncrease the frequer,
All nine of the CORRECTION DOW2~ outputs are combined in OR ga~ce
24, the ou~put of which is fil~ered in filter 26 ~o produce a
voltage which is applied to VCO 16 to decrease the frequency of
the clock pulses.
These clock pulses, together with played back data,
are applied to diyital data detect circuits 30 which produce
outputs representing played back data in non-return to zero
form, together with clock pulses synchronized with the played
back data. The digital data detectors of ~he present invention
also produce phase pointers which are bits accompanying ~he
data and which identify suspect data. These phase pointers indicat~
data represented by transitions occurring extremely early ~r late
in the ~it cell. These phase pointers are used in error corr~c ion
circuitry com~only associa~ed with magnetic tape storage systems.
The VCO 16 of the present ~nvention produces a
prescribed number of clock pulses for each bit cell. In the
example there are nominally 16 clock pulses, designated 0-15, for
each bit cell, as is depicted in Fig. 6~.
Fig. 3 shows the phase detector circuit 18 which is
replicated for each of the nine tracks. It includes a digital
phase counter 32 which counts clock pulses from the YC~. Counter
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32 normally rolls over and restarts from zero upon counting
the 16 clock pulses which define a bi-t cell.
The played back data from the associated tract is
applied to the transition detector 34 which produces pulses
at the detected transitions. Decoding logic including
window generator 36 and AND gates 38 - 44 produce COP.RECTION
UP and CORRECTION DO~N signals, and SHORT and LONG signals.
These signals are produced in accordance with the time range
in which the transition occurs with respect to the center of
the bit cel'. Referring again to Fig. 6A, a SHORT pulse is
produced i~ the transition occurs during an extreme low
range corresponding with counts 0-3. A CORRECTION UP signal
is produced if the transi-tion occurs during a range
corresponding with counts 0-7; a CORRECTION DOWN output is
15 produced if the transition occurs during a range
corresponding with counts 8-~5; and a LONG pulse i5 produced
if the transition occurs duriny an extreme high range
corresponding with counts 12~150
Referring back to Fig. 3, the SHORT pulse is
20 produced by AND gate 44 which responds to an output of
window circuit 36 which is up during counts 0-3. The
CORRECTION UP output is produced by AND ga-te 42 which
responds to a window which is up during counts 0-7; AND ga-te
40 produces the CORRECTION DOWN signal in response to the
25 window which is up during counts 8-15; and AND gate 38
produces the LONG signal in response to the window which is
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up during counts 12-15.
In order to produce CORR~CTION UP and CORRECTION
DOWN signals having a width proportional to the phase error,
the outputs of AND gates 40 and 42 are applied to pulse
width logic 46 and 48, respectively. Logic 46 and 48
produce pulses having widths proportional to the -time
between the transition and the center
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_ . _ _ _ .. _ ___ _ _ _ _~.~ _ __ _ .".. __ _.~".. __.. . . _ __.__ _ _
' ~r
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of the bit cell. Logic 48 produces a pulse -that starts at
-the data edge and stops in -the middle of the cell. Counter
45 counts how long after mid-cell a transition occurs. If
this late transition occurs, logic 46 produces a pulse
s proportional to the count in 45.
The CORRECTION UP and the CORRECTION DOWN signals
are applied to the OR gates 22 and 24 (Fig. 2) to be
combined with other CORRECTION UP and CORRECTION DOWN
signals to con-trol the VCO. In this manner, the frequency
of the VCO is controlled by the phase errors.
For larger phase errors, counts are added to or
subtracted from the phase counter 32. When AND gate 44
produces a ~HORT pulse, a count is subtracted from phase
counter 32. When AND gate 38 produces a ~ONG pulse, a coun-t
is added to the phase counter 32. This has the effe~t of
advancing or retarding the ~hase detec-tor o~ one track with
respect to ano-ther track. This is used to compensate for
phase deviations that might be caused by such factors as
head or tape skew.
2~ When the -transition occurs in a high or low
extreme range of the bit cell, an indica-tion is produced
that there is an error in this bit of information. AND gate
50 produces a phase pointer when this occurs.
Fig.4 shows the data detector which is replicated
2s for each of the nine tracks. Data and the output of phase
c~unter 32 (Fig. 3) are applied to the four-bit data
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integra-tion counter 52. Da-ta detect:ion circuit 54 produces
an output indica-ting a high or low condition o~ the counter
at the end of the bit cell. For GCR data, NRZ data circuit
56 compares the condi-tion at the end of the present bit cell
with that of the last bit cell in flip flop 92 to produce an
output representing the NRZ data.
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g~
For PE dat~, the data cycl~ circuit 90 keeps track of the two halves
of the PE data cell. NRZ dat~ circuit 56 then determines if the
integrated data is high or low during the second half of the dat~
cell to produce the NRZ data output~ Clock circuit 58 produces a
clock output synchronous with the N~Z data output for either data
density.
The operation of the data c:locking and detec~ion
system of the present i~vention can be better understood from
Figs. 5A - 5H an~ 6A - 6G which depict examples of operation.
In Fig. SA the first transition 60 in the data u~¢u~s exactly in
the middle of the bit cell as defined by ~he clock in Fig. 5B.
There is a perfect lock. The next transition 62 occurs late,
~fter the middle o the bit cell, but within the ~ime defined by
count~ 8-11 of the phase counter. A ~ORRECTION DOWN signal,
as shown in Fig. 5D, is produced. The next transition 64~ is very
early. It should have occurred at the time 66 in the middle of
the bit cell. A phase error pointer is produced as seen in Fig.
5H. The last tr~nsition S8 occurs early with respect to the middle
of the bit cell 70. A CORREC~ION UP signal is produced as indicated
in Fig. 5C. Fig. SE shows the output of the data integration
counter 52 in detecting this data. N~Z data circuit 56 produces
the output indicated in Fig.5F. Clock 58 produces the wave form
shown in Fig~ 5G which is a clo~k synchronized with the data.
Fig. 5~ shows the error pointer produc2d by the AND gate.S0 to
indicate the larg~ phase error occasioned by the transition 64.
Figs. 6A - 6G depict the condition of th2 phase
detectors for two tracks wherein one track is skewed with
respect to the other~ Fig. 6B shows the played back data
for one track and Fig. 6C shows the most significant bit of the
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phase counter 32 for that track. Fig. 6~ shows played back
GCR data for another track and Fig. ~F ~hows the most signi-
ficant bit of the phase counter 32 for that krack. Figs. 6D
and ~G show the phase counts for the two tracks. Note that
the transition 72 occurred so early that a count was deleted,
or skipped, in the phase count by having the counter ~o from
14 to zero at 76, skipping a count of 15. For the other track,
the transition ~4 occurred so late that a count was added, or
duplic~ted in the phase count at 78 by repeating a count of 12.
The result is that the phase counters for the two tracks obtain
increased phase skew, one with respect ~o the other.
While a particular embodiment of the invention has
been shown and described, various modifications are within the
true spirit and scope of the invention. The appended claims
are J therefore, intended to cover all such modifications.
