Note : Les descriptions sont présentées dans la langue officielle dans laquelle elles ont été soumises.
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Background of the Invention
This application relates to the field of door access
security systems and, particularly, to the field of card
readers for door access security systems.
Door access security systems, utilizing magnetic card
readers at doors to be controlled, are known in the prior
art. Such systems include central controllers coupled to
a plurality of readers, each of which is located at a
specific door to be controlled. Authorized persons
wishing to gain access through a door~ insert magnetic
cards into slots in the reader. Magnetic codings on the
cards are then read and data is sent to the controller
which authorizes or refuses entry and tells the reader
either to keep the door locked or unlock the door.
Such a system can advantageously be used as a time
clock to keep a -record- of the hours -worked by hourly
employees. - ~oweve-r-t~ a problem with- system throughp~t
axises when a large number o employees all try to clock
in or out at the same time. The delays caused by reading
~0 of a card, waiting for a poll signal to come to the reader
from the con~oller, sending the card- data to the
~ontroller and waiting for the controller to process the
information and send back a "Go" or "No Go" signal can
create impatience in the workers at the end of the line.
Such card reader systems can also be used to moni~or
alarm contacts located at strategic locations throughout a
facility. In the prior art, a centrally located alarm
contact monitoring device was located near the controller
with individual wires coupling ~he contact monitoring
device to th~ alarm contacts located throughout the
plant. Such systems were effective but re~uired an
individual polling protocol and the associated hardware
~or the alasm contact monitoring device. Further,
individual wires had to be str~ng between all the contacts
to be monitored and the central monitoring device. This
could result in large expenditures for wire. Further,
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~uch cen~ral contact monitoring devices were yenerally not
well suited to applications where only a ~ingle ~larm
~ontact needed to be mcnitored ~ince the function rarely
~ustified the expense.
The prior art ~ystems al~o had r~om for improvement in
~he area of opera~ion during times when the communication
lines between the reader and the central controller were
down. In such a 6i~uation, if all access was denied,
pe~ple w~uld be inconveni nced ~r, worse, trapped in an
1D undesirable emergency situation. The altern~tive would be
to allow free access thr~ugh ~ll doors. ~owever, with
record-keepin~ functions done at the central controller,
. ~here would be no ~ecord of the individusls who entered
and left specific areas during specific times while the
lines were downO As a result, if the~t occ~rred dùring
the down time, there would be no record t~ use in the
i~vestigation_
5ummary of the Discl~sure
There is disclosed herein a card reader foE use in a
security ~ystem for controlling access through key doors,
~aid security ~y~tem having a central controller. The
card reader -reads magnetic ~ata stored on cards held by
employees, ~tc. The cards have ~ system code and an I.D~
code on them. The card re~ders can do time ~nd attendance
functions to serve as a time clock by reading data stsred
permanently on the card and ~ending it ~o the central
controller for pro~essing~ The central controller then
~rants or denies access based on the ~ard data.
~ptionally the improvrd card re~d~r can also make the
decision whether to gran~ ~r deny access l~lly without
dialogue with the control~er by reading some of the data
on the ~ard and ~toring.the re~t for later tran~misEion t~
the central controller. Typically, thi~ i done by
reading the system ~ode ~nd granting auth~ri~ation i~ the
3~ ~ystem code on the card ~at~hes . . he ~ystem ~ode vn u--er
pr~grammable ~witches~ The I~D~ c~de i~ ~hen stored in
X~
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the buffer with the time of day of the transaction for
later transmission to the central controller. This feature
increases the throughput of the system by eliminating the
need for each employee to wait for authori~ation from a
controller which may be delayed while processing other
messages from other readers.
The improved card reader can also sense when communications
with the central controller are lost and grant or deny access
without consulting the controller, based upon data on the
card. During times when communications with the central
controller are lost, the card reader stores the I.D. data
from the card, for each employee who was granted authorization,
in a buffer for later transmission to the central controller.
The improved card reader can also monitor alarm contacts
for changes in status and signal these changes to the central
controller. The central controller can be programmed to
make a conditioned response to the reader coupled to the
changed contact or to any other reader in the system. The
response message can cause a relay or relays in the reader
to change states, thereby signalling any devices coupled to
the relay or relays that an action in response to the changed
alarm contact is desired.
According to one aspect the invention relates to a
card reader for use in a security system having a central
controller which communicates with said card reader, said
card reader comprising: a memory; means for readiny data
stored permanently on cards; means for evaluating data Erom
the cards independent of the central controller, and for
selectively permitting access to a controlled location in
response to the evaluation of the data from the cards~ with
the card data remaining unchanged on the cards; means for
receiving signals from said central controller; means
coupled to said receiving means for sensing when communication
with said central controller is lost; and means responsive
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to said sensing means for storing said data from said reading
means in said memory during times when communica-tion with
said central controller is lost.
According to another aspect the invention relates to a
method of operating a security system which controls access
to a location and which includes a local card reader and a
central controller which communicate to limit access based
on card data, comprising: reading data stored on a card;
evaluating the data from the card independently from the
central controller; permitting access to a controlled location
in response to the evaluation of the data from the card,
with the card data remaining unchanged on the card; sensing
at said local card reader for inability to communicate with
said central controller; storing card data at said local card
reader during periods of inability to communicate, transmitting
stored card data from said local card reader to said central
controller when communication ~s possible~ and receiving
control signals from the central controller.
According to another aspect the invention relates to a
card reader for use in a security system having a central
controller and a plurality of said card readers, wherein the
central controller and each card reader are electrically
connected so as to each define an electrical communication
system, each said card reader comprising: a memory; me~ns
for readingdata stored permanent~y on a card, wherein said
data is organized on said card so as to define first and
second data segments, means for storing data read from said
cards in said memory; means for sending data from said memory
to ~aid central controller at a time controlled by said
electrical communication system; means for receiving signals
from said central controller; means for selectively permitting
access to a controlled area in response to said signals from
the central controller, means for storing at least one
authorization code; a local buffer; means coupled to said
receiving means Eor sensing that ability to communicate with
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t~
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said central controller is lost; means for comparing a
selected one of said first and second data segments with
said authorization code; means for granting or denying
access to said controlled area independent of signals from
the central controller in response to said comparison of
one of said first and second data segments with said
authorization code, while said ability to communicate with
the central controller is lost; means for storing the other
of said first and second data segments in said local buffer
during periods when said ability to communicate with the
central controller is lost; means coupled to said receiving
means for sensing that said ability to communicate with the
central controller is restored; and means for transmitting
the data stored in said local buffer to said central
controller at a time controlled by ~said electrical communica-
tion system, when said abilit~ to communicate with the
central controller has been restored.
~rief Description of the Drawings
_
Figure 1 is a block diagram of a security system in
which the improved reader of the invention could be used.
Figure 2 is a block diagram of the improved reader.
Figure 3 is a logic diagram of the optical isolator
board.
Figures 4A and B are a logic diagram of the switch
and relay board.
Figures 5A and B are a circuit diagram of the RAM
buffer board and power fail detect circuit.
Figures 6A, 6B and 6C are circuit diagrams of the CPU
reader board.
Figure 7 is a logic diagram of the CCM/COM logic.
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~ igures BA and 8B are ~ l~gic diagram of the circuitry
~f the delayed transmission buffer,
~ igure 9 is a flow diagram of ~he ~eq~ence of ~teps
perfonmed by the ~ard reader in performing ~ ~ime ~nd
attendance function.
~ igure 10 is a flow di~gram of the steps which are
taken to unl~ad the time ~nd attendance data ~r~m the
buffer and transmi~ it to the central controller 20.
~ igure 11 is a flow diagram of the time ofset routine
perf~rmed by the card reader.
~igure 12 is a flow diagram of the steps aken by the
card reader in buffering tran~actions during a degraded
mQde when communic~tion is los~ with *he central
c~ntroller.
1~ ~igure 13 is a flow diagr~m of the ~anner in which the
card reader CPU unloads the delayed transmission ~uff~r
when communications are restored.
Figure 14 is a flow diagram of the manner in which the
card reader CPU senses alarm cont cts.
Figure 1~ is a ~1GW diagram for reporting of the
status ~f alarm contacts by the card reader CP~.
Figure 16 i5 a flow dîagram for the c~n~ral ~ntroller
process for ~n automatic resp~nse t~ a change in an alarm
cont~ct.
Detailed De~cription o~ the Preferred Emb~diment
Referring ~o ~igure 1 there is disclosed a sys~em
diagram o~ a typical magnetic card reading security
system. ~ controller 20 is coupled to a plurality of car~
readers of which readers 22 and 24 are typical~ ~he
contr~ller 20 is coupled to each reader by an enable pair
and ~ data pair by which the controller can communicate
with any card reader in ~he sy~tem.
For example, ~he controller 20 communicates with ~he
reader 22 by an enable pair 26 and a data pair 2B~ The
contr~ller 20 poll~ the reader 22 for messages and ~enas
c~mmands to i~ by the enable pair 260 Data is ~en~ ~o the
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con~roller 20 ~rc>m the reader 22 via the dat~s pair 2B.
Serial format is. used on both lines~,
The reader 22 is typically located ~t a dc~or that
needs to be access-controlled while the ~ontroller 20 can
be located at çome distance ~rom ~he door. ~he ~tr~c~ural
details of the controller 20 are well known in the art,
and it can be purchased under ~che mc>del designatic>n ~AC
530/40 from Rusco Electronic Sy~tems in Glendale,
California. The object ~ode ~ftware for the controller
10 is al so well ~nown ~nd can be purchased from the ~ame
source.
- -In opeFation, the reader 22 receives ~ magne~ic r~rd
in a card slo~-~2~ The det~ of a ~ypical magnetic card
structure will be Eound in ~.S. Patents 3,717,749 or
. ~5 3,811,9770 Other structures could al~o be used; the
details of the structure o~ the magne~ic card ~re not
critical to the invention. Any structure oapable of
holding data enccded in a card and converting it to
electric~l ~ignals c3pa~le of ~eing transmitted over a
line will be sa~isfactory.
When the card is ~ead, the data on the card is stored
in a temporary RAM loca~ion until ~ p~lling signal ~rom
~he controller 20 arrives on ~he enable lines 26. Upon
receipt o~ the polling ~ignal ~n the line 26, the data
from the card is ~rans~erred on the data lines ~8 to the
controller 20 unless certain options are presen~ which
cause ~he reader to independently make the awthorizatiun
dectsion. The c~ntroller 20 processes the data ~nd sends
b~ck a "Go" or ~No Go" ~ommand which ~auses the reader 22
to take the appropriate a~ti9n. If the command is. ~Go",
the re~der 22 unlocks the door lat~h via khe lines 34 and
ligh~ a green LED. If the c~mmand is ~No Go~, the reader
22 lights a red LED ~nd, optionally, energi es ~ No Go
relay.
The reader 22 ~an also incorporate cir~uitry to
m~nit~r a plurality of ~larm conta~ts connected to the
~7~1~i8
lines 30D When ~ne ~f ~he ~ontacts ~hanges ~tate, he
reader 22 ~enses the ~hange ~nd ~ignals ~he contr~ller 20
on the next poll. ~he contr~ller 29 c~n ~hen prin~ out a
pre-programmed message vn a printer 36. More impsrtantly,
the con~roller 20 can automatically ~end back a command to
~ause a ~witch closure by energizing ~ relay in the reader
22 or in any other reader in the systemO This automatic
resp~nse can also be any other command that the reader
receives normally from the con~rol7er. The rel~y can be
~onnected to an emergency de~ice via the lines 38. The
emergency device can be any device ~uch dS ~n ~utomatic
phone diaier, a prinkler system, an àlarm or whatever
other device that is desired~
The reader 24 is ~ different type ~f improved reader
~- 15 which ~an be used to keep time rec~rds for the attendanc~
of hourly employees' ~n their jobs. The reader 24 has a
display 40, a card slot 42, ~nd ~ln~ and aout~ buttons, 44
and 46~ In operation, an employee would place his card in
the card slot 42 and press either the ~in" b~tt~n 44 or
the "out" button 4~. The data on his card plu~ the time
of day displayed in the display 40 would then ~e stored in
a buffer ~n the reader ~4, Based upon the ~ystem code
data on the card, the reader 24 woul~ auth~rize ~r deny
entry to the employee. If ~ntry is authorized by the
~5 reader 24 and.a green LE~ will be lit, the door will be
unlo~ked via the lines 48. If entry is denied, the reader
24 will ~o indicate by lightin~ a red LED ~n the ~ace
plste. All a~thorization or denial d2cisions are made
locally by the reader 24, ~nd the d ta reyarding each
transaction is stored in the loeal ~uffer in the reade~
24.
The controller 20 i5 coupl~d to the reader 24 by an
enable pair SD and a data ~aiY 52~ The controller 20
p~ he reader 24 by sendin~ ~ poll signal ~n the line
SD. Upon receipt of the poll signal, the reader 24
transfer~ the dat~ for one transaction ou~ of its ~u~er
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to the ~ontr~ller 20 via the da~a li~es 52. The
~ontroller ~hen can pro~ess the data in ~ny fashi~n
including printing it ~ut on the printer 36. The details
of the ~tructure and oper~ti~n o~ the controller 20 are
exemplified by U.S. Patents 4,216,375 and 4,218,6gO.
The re~der 24 can ~lss include means ~ offset the
time displayed in the di~play 40 ~rom the time ~ept by ~he
controller 20 in the case that the controller is in a
different time zone from the reader. Nonmally he
10 controller 20 keeps the master time for the sy~tem ~nd the
reader 24 keep its own time. Every 1~ minutes, the reader
24 inquires the time-of the c~ntroll~r 20 and synchronizes
the reader' r l~cai time with the master time kept by the
controller. When the reader 24 is in a di~ferent time
zone from the controller ~, a group of off~et switches in
the reader ~4 are set to indicate the number o~ minu~es of
o~fset between She local reader time and the controller
time.
The reader 22 can als~ include a local bu~fer for
keepin~ a record of all transactions which ~ccur during
times wher~ communications with ~he controller ~0 are lost
due to cutting of the wire pairfi, p~wer Eailure or ~or
o~her reasons. When the reader 2~ has-n~t received a poll
from the c~ntroller for a predetermined time, the reader
will start storing the data ~o~ transactions during the
downtime in its local buf~er. EaEh-magnetic ~ard has a
system code a~d an ID code. The sys~em code is used by
the seader to determine whether or n~t t~ grant
authorization for ent~y to khe individual. ~f the
individual i~ penmitted to enter, ~is ID c~de ~nd ~he
local time will be ~t~r~d in the ~ocal buffer. When
communication~ with the controller 20 are re~t~red, the
d~ta in ~he bu~fer will be sent to the controller vi~ the
data lines for processing there.
3~ Referring to ~igure 2, there is $hown a bl~ck dia~ram
of a card reader f~r use in ~ ~ecurity ~ystem ~uch ~s ~s
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78~3
shown in ~igure 1. Although in reali~y ~wo different
~ypes of readers exist~ ~he core circuits of each type of
reader are ~he s~me with ~ne type ~f re~der havi~g cert~in
~dditional optional circuits which ~he o~her d~es not
have. Figure 2 represents a combined functional bl~ck
diagram o a reader with the ~ommon core ~ircuits and with
all the optional ~ircuit elements ~f both types of readers
al so present .
~he card reader ~f Fiyure 2 communic~tes with the
controller 2D of Figur~ 1 through ~n is~lation board 54.
The isolation board 54 serves ~o isolate he data ~n the
enable . pair 26 -and . data pair 2~ from the logic ~ircuitry
sf ~he rest of the ~ard reader. ~he i~olat~on b~ard 54
passes the ~ignals ~rom ~he en~ble la~e 26 through to the
1~ ~X data lines 56 and passes the data f~om the Tx data
line-c 58 through to the data lines 2R.
The RX data lines ;6 are ~oupled to a multiplexer 60
in a switch ~nd relay board 62~ The purpDse o~ the
mul~iplexer GO is to sele~t various data channels ~or
conne~ti~n to a data lin~ D7 r 63 ~ 9~ a bus 64 . The bus 64
is coupled be~ween the switch . ~nd relay b~ard 62 and the
data, address and contr~l termin~ls of ~ microproce~soF
CPU 66 on a reader CPD b~ard 67~ Address lines ~0-A2 from
the bus 64 are ~lso coupled to the mul'ciplexer 60.
Through these ~d d ress line~, ~he CPU 66 causes the
mul~iplexer 60 to ~elec~ c~ne e:f ~he data channels
connected t~ it for conne~io~ ~o its data ~ltpUt coupled
to the line D7. The microproces~or 66 ~an then read the
dat~ on the se~ ected data ~h~nnel through the .D7 line
63. ~n ~igure 2 the ~nly dat~ channel~ which are ~hc~m
~re th~ ~x data line ~6 throl~gh which commands ~nd ~lling
si~nals are received and the cc~il detect line 57 which
carries data read ~rcm the ~ardO Other da'ca channels are
used f~r other features of the reader not relev~nt to the
3~ pre~ent di~cussic~n.,
~71~
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Data to be transmitted ~rom the ~ard r~ader ~o the
central ~ontrol~er 20 are inpu~ rom the ~ line 68 ~f the
data bus 64 to a driver 70. The driver 7D is ~lso coupled
to the A0-A2 ~ddress lines of the data bus 64 which ~upply
~n addre~s from th microproce~sor 66. ~he driver 70 h~s
several addressable output~, ~ne of which is ~he Tx data
lines 58. The address ~upplied to the driver 70 causes it
~o apply the ~ignal on ~he D~ line 6B to the selected
~utput. To transmit data, the microprocessor 66 places
he data to be ~ent on the D~ bus line and writes the
proper address on the address lines A~-A~ of the bus 64.
~he serial data on the D0 line is hen applieB ~o the.Tx
.
data lines 58.
The central controller 20 seceives ~he data on .he
~5 data line 28 and ~cts upon the ~ata mesxage in some
fashion dependin~ upon what ~he message is end may or may
not send ~ command back to the card re~der ~ia the enable
line 26.
~ go relay 71 is coupled to a door latch device by the
lines 34O The lines 34 can be couple~ to relay contaets
or oth~r switching devices to provide an interruptible
current f~ow path ~o control whether the door ~tch is in
a locked or unlocked ~tate. The go relay is also coupled
to the driver 70 by ~ switching lîne 72. The switching
~5 line. controls the state o~ ~he go relay and thereby
controls the ~tate of the door latch device~ The
switching line is addresssble by the ~icroprocessor 66
through the driver 70 such that the mi6ropr~cessor 6
controls the s~ate of the go rel~y 7D~
q~he microprocessor ~56 is al~o coupled ~o a ~ard read~r
coil circuit 74 by the ~)U5 64. The card reaâer ~ils 74
consis~7 in the preferred embodimeAt:~ of ~ plurality of
coils coupled to the address and da~ca line of the bus 64
~nd physically arranged so as t~ individually magnetieally
in~eract with a plurality ~f magneti2ed ~pot~ on a card
inserted in the ~ard ~lots 112 or 32. ~he 3nicroprocessor
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66 can individually eddres~ and reDd eDch coil in the card
reader ~oil ~ircuit 74 to determine the data in the
magnetic sp~ts on .he card. The details ~f the card
reading coil ~irc~it ~re known to those ~killed in the ~rt
and are not critical to the invention.
The microprocessor 66 is al~o ~oupled to an optional
displ~y 40 by the bus 64. In re3ders which are beiny used
for time ~nd attendance functions, i.e~, ~s time ~loc~s,
it i~ desirable that the time ~f d~y be displayed
externally for the benefit of workers who are lined up and
~aiting to put their cards into the reader 24 to start or
end their work shift . The display 40 can be any
conventional display, ~nd the det~ils of i~s construction
are not eritical -to the invention.
The microprocessor 66 is also coupled to a random
access memory (RAM) board 78~ ~he RAM board 78 contains a
R~M buffer memory-80, a battèry-backup ~ystem comprised of
a battery 82 and a power fail detect ~ircuit 84. The
power ~ail detect circuit 84 m~nitors the 12 volt
unregulated D.C~ voltage derived from the A.C~ power line
and connects the battery 82 to the power termin~ls of the
RAM bu~fer 80 when the ~ n~ p~wer fails 90 ~ to
preserve the data stored in the RAM 80. The ~A~ ~0 is
~elected by the microprocessor ~6 throu~h connecti~n of a
~5 decoder 86 to .the address and con~rol lines of the bus
64~ When the microprocessor 66 wishes to write a wora in
the RAM ~0, the microprocess~r generates ~he proper
~ddress to selec~ the RAM 80 and pla~es ~t on the bus 64
thereby enablin~ the R~M ~0 through the decoder 86. The
d~ta to be written int~ the ~AM 80 is ~hen placed on the
data lines o~ the bus 64.
A delayed transmission buffer 88 is also ~oupled ~
~he micropr~cessor 66 through tbe bus 64. The purp~se ~f
the dela~ed transmissi~n buffer ~B is to st~re d~ta read
from the magnetic cards during times wh~n co~muni~ation
with th~ central ~ontroller 20 are l~st.
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~7868
A CCM/COM board 90 i~ ~lso ~ouple~ to the
microprocessor G6 by the bus 64~ ~he puFpose of the
: CC~/C~M board 90 i6 to monitor the condition ~f ~n alarm
device or deviees external to the ~ard reader and ~o
gener~te data indic~ting ~he conditiDn of the alarm
devices for tgansmission to the central ~ontroller. The
CCM/COM board g0 also can receive d~ta from the central
~ontr~ller which oauses a ~wi~ch closure on ~he CCM/COM
board. This swi~ch is couple~ ~o an emergen~y device by
the line~ 3B. The alarm cont~cts ~re ~oupled to the
CCM/COM board 90 by the lin~s 30.
When the card reader. is being used.for a ~ime ~nd
; attendance ~un~tion, the ~n ~nd Out buttons 44 and 4~ are
used to tell the oard reader whether the cardholder wishes
to enter or leave an area. The ~n an~ Out bu~cns 44 and
46 are coupled to the MUX 60 in the witch and relay board
62 by the llne 92.
~ red ~nd ~ ~reen indicator LED, represented by bl~cX
97 are each coupled to the MUX 60 by the bu~ 96. The
LED'~ are used by the microprocessor 6~ to signal whether
authoriza ion has been granted or denied.
The micr~processor 66 is c~upled to a feature memory
98 and to a program memory l on by the bus 64. The progrs~
memory lG0 stores the instructions for the microprocessor
25 66 and the feature memory 98 ~ores data indi~ating whi~h
options are in effect ~or the mioroprocessor 66.
Referring to Figure 3, ~here ls sh~wn a circuit
diagram $or the iso~ation ~oard ~4 in ~igure ~. The data
lines 28 are coupled to the cGllector and emitter of a
tr~n~i~tor 1~6 in the optical isolator ~02. The light
emitting di~de 108 ~f the optical isolator ~02 is coupled
acros6 the TX data lines 58. When ~he curren~ is~flowing
in the TX data lines 58, the LED 108 i~ energized ~nd
~mit~ light ~ausing the transi~tor ~D6 to a~sume one ~f
it~ two ~wi~hing states. Th OppQSite ~ate is as~umed
when the ~ED 10~ i~ de-energized~
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7~6
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.The en~ble lines 26 ~re ~oupled thr~ugh ~ n~i e
~uppression ~ircuit 110 to the LED 112 of ~n cptical
~ or 116. The transi~t~r 114 of the opti~al ~lator
ha~ its o~lle~tor ~nd emitter ~oupled to the XX data lines
~6. In the preferred cmb~diment, the ~pti~al isolator 116
is ~ MQ~san~o ~MC~2. Tbe ~ptical i~la~or 1D2 is a
~5Dnsanto*4N33 .
The details ~f the cir~uit of ~he swi~h ~nd relay
b~ard 62 are given in Figures 4 A ~nd B whi~h ~re ~ l~gic
~o ~iagram vf that b~ard. The ~X da~a line 56 is ~upled o
~he data input D1 of the mul~iplexer -60~. A resistor 5~
couple~ a ~5 v~lt ~upply t~ the line S6 ~o p~sitively
. cl~mp it ~t ~ logi~ 1 level except where the tr~nsist~r
114 on the i~la~i~n b~ard.cl~mps the line 56 to ground
p~tenti~l. The other dat~ inputs of the.multiplexer 60A
~re coupled to other dat~ channels. ~or ex~mple ~he eard
reader coil circuit 74 is o~upled ~o the D~ input of the
multiplexer 60A by a line 57. ~he coil detect ~ignal line
57 carries She data from eAch ~al in the card reader coil
circui~ 74 ~s it is ~ddressed by the microprocessor S6.
The out switch 46 and the in ~wit~h 44 ~re coupled to the
D2 and D3 inputs respectively ~ the lines ~1~ and 120.
The address inputs 12 of the multipl~xer 60A ~re
co~pled to thè ~0-2 ~d~re~s lines of the bus 64. The
2~ output 63 of the multi~lexe~ 6DA i~ cvupled tQ the D7 d~ a
line of the bus 64. The microprocess~r 6~ contr~ls which
of the data inputs are coupled to th2 data output fi3 by
the ~ddress it ~pplies ~n the addres~ line~ 122.~ The
chip ~e~ect input 126 is coupled t~ the sddres5 lines an
30 . th~ bus ~4 of the ~icroproce~sor 66 through ~ decoder ~n
the reader CPU b~ard to ~e di~ussed m~re fully bel~w.
The micropr~cessor 66 cAn en~ble the ~ultipl~x~r 60A by
wri~ the proper a~dress on the ~ddre~ line~ d~ivinQ
the ~ecoder ~upled tQ the li~e 126 ~not ~h~wn).
multiplexer 60B has ~ts ~ta outpu~ ~suple~ to the
V7 data line 63. The data inputs ~f the ~ultiplexer 6~B
Trademark ~
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are coupled ~o various dat~ ~h~nnels~ The X~ data ~nput
i coupled by the llne 128 ~o a ~t~mper~ ~witch (not
~how~). The tamper swi~ch i5 physically ~itu~ed ~ AS to
ch~nge ~tates when the f~ceplate o~ the ~ard re~der is
removed ca~sing an al~rm message ~o be tran~mi~ed to the
ntroller 20. The Xl data inpu~ is coupled to a ~card
in" ~witch (n~t ~hown). The ~c~rd ina ~witch is ~ituated
~ as to change states when ~ card is inserted in the card
slo~. By periodic~lly ~hecking the condi~ion of these two
swi~ches, ~he micr~processor 66 can tell whether tampering
is ~ccurring or whether there is a card to be read in the
c rd 510t. - . `
~ here are three gro~ps of eight switches ~n the swit~h
and relay board 62. A time 4ffse~ group of switches 136
1~ is c~mprised of 8 ~witches 136~-B which are used ~o set a
binary number representing the number o~ minu~es of ~ime
ofset at the lo~al ~ard read2r. ~n those ~se~ where the
local card reader is in a different time zone than the
central controller 20, th~ ~wit~hes 136 are ~et f~r the
number of minu~es ~y whi~h the lo~al ~ime ~ the ~ar~
reader differs from the time at the central ~ontr~ller.
A second group o~ switches 138 has several ~rposes.
The switches 138A-D are u~ed to set ~he am~un~ of cime
tha~ the unlocX signal on the lines 34 ~o the d~ox la~ch
device cau~es the door latch t~ remai~ unlo~ked. The
switches 138A-D also determine ~he ~ime ~f energizati~n of
a No ~o relay 166 and ~he time ~he red and green LEDs (no~
shown) in the bl~c~ 9? in Fig~re 2 ~re energized during
certain times in the operation. The ~wit~h ~3~E is used
to signal whether a 12 hour or 24 hour time display format
i~ desired. The switch 73BF is used to enable and disable
the bu~fer RAM B0 as an vption. ~he switche~ 138G and
are not used.
The ~wit~hes 140 are used ~y the ~ustomer to 8et the
3~ ystem ~ode. The system code is ~ne of tb~ items ~f data
whi~h is ~agnetically ~tored ~n each cardholder~ eardO
. .
~2~ o ~
When the ca~d r~ader makes the ~uthorization decision
locally with~ut consultiny the central contr~ller 20, it
i the system c~de stored on the ~witches 14DA-~ whi~h is
compared to the system c~de ~n ~he cardh~lder'~ ~ard to
determine i~ ~u~horization will be granted.
The ~witches 136, 138 and 140 ~re individu~lly
addressable by the microprocessor 66 through the
multiplexers 60A and 60B and ~ decoder 1~0~ The dec~der
140 has addres~ inputs 142 ~oupled to ~he address lines in
~he bus 64. The address supplied on ~he lines 142 is
convert2d an the ~CD to decimal decoder 140 to a l~gic
2ero ~ignal.sn on2 ~ the ~utput lines ~-6 which comprise
bus-144, Each o lines in the bus 144 is..coupled t~ one
terminal of a plurality of switches in the ~wit~h groupfi
136, 133 and 140. When the group address appe~rs on the
address lines 142, one ~f the outputs in the bus 144 goes
l~w thereby a~tivating ~hat group. The o~her terminal o
ea~h swit~h is coupled to the cathode of a di~de wbieh has
i~s anode coupled to one of the XD-X3 input~ of the
multiplexer 60B via the lines 132, 134, 130, ~8, 146 or
148. All o~ the XD-X3 input~ are ~l-sc ouple~ to
volt ~upply through the resi6tors 150, 1~2, 154 ~nd 156.
The X0-X3 inputs wil} be held in ~ lo~ic one condi~ion
~xcept if ~he line c~uplin~ ~ha~ input is ~lso ~oupled to
~ ~roup o~ switches o~ which one has been en~bled by a
logic zero ~rom the decoder 140 and the switch is clo~edO
The groups of swi~ches ~oupled t~ the X~-X3 i~puts of
~he multiplexer 60B interse ~ with tbe groups c~nnected
~ he bus 144 ~u~h that for any part icul ar output of the
decoder 1~0 whi~h h~s been enableA, and ~or any ~arti~ular
input of the multiplexer 60B which h s been enabled~ ~nly
one swi~ch is couple~ to b~th en b ed lines. Thus th~
~icroprocessor 66 c~n individually read ea~h swig~h in the
groups 136, 138 and 140 by ~h~nging the ~ddress ~ignal on
3~ the addresc lines of the bus 64,
The multiplexer 60B has its inhibit line grounded by
the line 158 and its disable input held high by connection
through a resistor 160 to a t5 volt supply. The disable
input is pulled low to take the D7 output out of the high
impedance state when the signal CSSW is true on the line
162. The line 162 is coupled to a decoder on the reader
CPU board 67 which is coupled to address and control lines
of the microprocessor 66 in the bus 64.
~ata to be transmitted to the microprocesser 66 is
placed on the Tx data line 58 by a driver 70. The driver
70 also has several other outputs. For example t the
output line 164 can be connected to an optional No Go
relay 166c When the line 164 is grounded by the driver
70, a ~5 volt supply coupled to the other terminal of the
1~ coil of the No Go relay 166 causes current to flow through
the relay coil, thereby energizing it and causing the
electrical conditions on the lines 168 coupled to the
relay contacts to change.
In the preferred embodiment, the decoder 140 is a
74145 type TTL decoder such as made by Signetics, the MUX
60A is a 74LS 251 type multiplexer such as is made by
Texas Instruments, the MUX 60B is a MC14512, (CMOS type
decoder such as is made by Motorola, and the driver 70 is
an NE590 type amp driver such as made by Signetics.
An output line 96 from the driver 70 is coupled to the
GO LED (not shown) to energize it when authorization to
access has been granted~ An output line 72 from the
driver 70 is coupled to a terminal of the coil of a GO
Relay 71. When the driver 70 ~rounds the line 72, a ~5
volt supply coupled to the other terminal of the relay
coil energizes the coil, causing the relay contacts to
change the condition on the lines 34 coupled to the door
locking device.
The driver 70 has a data input, the D0 data bit on the
iine Ç8, and it has address inputs on the lines 172. The
address inputs 172 are coupled to the microprocessor 66 by
.
~2~7~6~
-16-
the bus 64. The address at these inputs determines which
of the outputs of the driver 70 will be coupled to the
data input 68. The microprocessor 66 can thus write a
logic 0 or 1 to any of the outputs of the driver 70 by
controlling the address on the lines 172 and the data on
the data input line 68 which is coupled to data bit zero
of the bus 64. The chip enable and clear inputs are
coupled to decoder 250 of Figure 6C and a gate 282 in
Figure 6B by the signal lines CSOUT and RST.
10Referring to Figure 5, there is shown a ci.rcuit
diagram of the RAM buffer and power fail detect board.
The RAM buffer 80 has address lines 174 which are coupled
to the address lines of the microprocessor 66 in the bus
64. Data inputs and outputs 176 are also coupled to the
microprocessor 66 data lines in the bus 64. A write
enable line 178 is coupled to a control line in the bus 64
from the microprocPssor -66 to control whether the RAM
buffer 80 is reading or writing data through the data
lines 176 to the address specified on the lines 174.
~0A chip select line 180 is coupled to a decoder 86.
The decoder 86 has a VMA signal inp~t line 184 coupling
one input of a NOR gate 182 to a ~MA control line of the
microprocessor 66 in Figure 6B. The VMA signal is true
when there is a valid memory address on the address lines
~5174. Because the other input to the NOR gate 182 is
grounded, the NOR gate 182 serves as an inverter with the
output on the line 186 false when a valid memory address
is present on the address lines 174~ The resistor 188
couples a positive voltage supply to the VMA inp~t of the
gate 182 to hold it at logic one except when VMA is
false. The VMA signal on the line 184 is a control signal
from the CPU 66 which indicat~s when a valid memory
address exists on the address lines of the CPU. A NOR
gate 190 has one input coupled to the output of the NOR
gate 182 and the other input coupled to a
CSRAM~ signal from a decoder 248 in Figure 6C. The CPU 66
786~
can cause CSRAM~ to be true, i.e., logic zero, and can
assert VMA on the line 184. This causes two logic 0's at
the inputs of the NOR gate 190 and a logic l appears on
the line 1~4. This logic 1 is inverted in a NOR gate 196
and appears as a logic 0 on the line 198.
A NOR gate 200 serves to gate a power fail detect
signal on a line ~02 from a power fail detector 84 through
to the chip select input at pin t8 of the RAM buffer 80 if
power fails. When power has not failed, however, the
signal on the line 198 controls whether the RAM 80 is
selected or deselected~ Normally, the signal from the
power fail detector 84 on a line 20 is a logic 0
indicating no power failure. When the signal on the line
1~8 is a logic 0, the RAM 80 is selected because the
signal on the line 204 is a logic 1 which is inverted by a
NOR gate to assert the CS signal on the line 180 at
logic zero thereby enabling the RAM buffer 80 to read and
write data.
A RST signal on a line 208 comes from a reset circuit on
the reader CPU board which will be described below.
The RST signal is a logic 0 at power up but becomes logic
1 1.2 seconds later as will be explained in connection
with Figure 6B. A NOR gate 210 inverts ~his signal such
that its output line 212 which is coupled to one input of
a NOR gate 214 is normally low after power has been on for
1~2 seconds~
The NOR gate 214 has its other inp~t coupled to the
output of a comparator 222 in the power fail detect
circuit 84~ The comparator 222 has its inverting input
224 coupled to a voltage reference of approximately .5.3
volts when the power has not failed. The line 224 is held
at this reference level by the voltage divider effect of
the resistors 228 and 226 which couple a ~12 volt D.C.
supply of line power to ground.
The non-inverting input 230 of the comparator 222 is
coupled to a 3.6 volt reference so~rce derived from
~78~31
ba~tery power. This reference voltage i~ generAted by a
resistor 232 which coup~es ~ battery 82 (not ~hown) to
ground thr~ugh a zener diode 234. ~he zener has a 3.6
v~lt breakdown v~ltage, ~nd has its cathode coupled to the
S line 230. The comparatDr 222 ha-~ ~ resis~or 236 coupled
between the output ~nd its non-inverting input to provide
positive feedback. The ~utput ~n ~he line 216 will be a
logi~ 0 ~s long as the power has not fail2d~ When the
power fails, the battery referen~e ~n the line 230 exceeds
the voltage on the line 224, ~nd the output ~n ~he lane
216 rises t~ a logic 1 level indicating power has failed.
The-logic 1 on the.line 216 with t~e ~ogic z~r~.on the
-line 212 causes the N~ gate 214 to lower ~tS- ~utput on
the line 218 to a logic zero. This 0 ~n the line 21B is
inverted to a 1 on the line ~02 by the N~R g~te 220 wbich
causes the output of the gate 200 to change to ~ 0,
thereby deselecting ~he ~ffer 80 if it was in a selected
conditionO When the RAM ~uffer ~0 is deselected, no data
may be written into ~r read out ~ the bu~er. The power
input 238 o~ the ~AM buffer 80 will be cuupled through any
known switching mechanism ~40 to the battery ~2 (not
shown) via a line 242 upon power failure~
Referring to Fisures SA, 6B, and 6C, there is shown a
circuit diagram of the reader CP~ board. The
microprocessor S6 is coupled ~o ~ feature memory 98 by
~at~ lines 240 and address lines 242. The feature memory
~ontains data regarding whi~h options are incorporated
into the card reader. The ~icroproces~or ~6 is also
~oupled to a program memory 100 by the data lines 240 and
the ~0-~ address lines 2~2, The enable inputs of the
mem~ries 100 and 98 are coupled via the lines 244 and 246
to the microprocessor's address lines 242 thr~gh decoders
248 and 250, respectively~ in ~igure 6C. A cl~ck 252
genera e~ timing ~ignals for he IRQ an~ N~ pu~s on the
lines 254 and 256, respectively. The detail~ of the
construction and operation of the clo~k ~nd of the featurP
`f
J~
-t~-
and program memories will be ~ppreciated by ~hose ~killed
in the art. Any ~echanism which generates signals
periodically vn the lines 254 ~nd 25~ will ~uffice for
purp~ses ~L the inventi~n.
The microprocessor 66 exe~utes the instru~tions which
are ~tored in ~he pro~ram mem~ry 100. Within the pr~gram,
which will be described ~elow, there are certain
~ubroutines which ae~ompli~h various b~usekeeping
routines. The IRQ ~nd NMI inp~ts on the lines 254 and 256
cau~e vectoring to certain of th2~e subroutines. For
~xample, the IRQ line 254, when ~serted ~rue, will cause
the program ~ontrol of the micropro~essor 66 to be
vectored ~ a routine which reads all the Ewitche~
described herein.
When the NMI line 256 is asserted true 9 the
micropr~cessor 66 i~ vectored to ~ tr~nsmit routine which
transmits data to the ~entr~l controller 20 via ~he Tx
data lines 58 and data lines 28.
Th microprocessor 66 must be rese~ to the beginning
of the program upon the initial application of power to
the circuitO A p~wer ~n reset circuit 254 accomplishe~
this purp~se. A comparator 2~6 has its non inverting
input 258 coupled ~o a reference voltage de~ined by a
resi~tive voltage divider compri~ed of the resi~tors 262
2~ and 264 c~upling the power ~upply to ground. The
inverting input 260 .is coupled to one terminal of a
capacitor in an RC ~ircuit comprised o~ ~a re~istor 266 and
a capa~itor 268. When the power is first turned on~ the
capacitor 268 ac~s as ~n initial short ~o ground and the
volt~ge on th~ line i58 will exceed the volt~ge on the
line 260~ and the output of the ~mparator 256 on the li~e
70 will be a l~gic 1. The line 270 is couplea to the
input of a N~ e 272 whi~h acts as ~n inverter. The
resi~t~rs 274 and 276 serve ~s a voltage divider to hold
3~ the li~e 270 in ~ logic 1 condition except when the
comparator 256 asserts the line 270 low.
.X '
~Z~
-20-
The logic 1 at power up on the line 270 i5 inverted
~nce in the NOR gate 272 ~nd ~gain in ~ N~R g~te 278 to
become the PONCLR signal on the line 2B0.
As the voltagP on the capacitor 26R rises, it exceeds
the volt~ge on the line 25a a~ a time determined by the
values of the resis~or 26~ and ~he cDpacitor 268. When
this happens, ~he 1 on the GUtpUt line 270 changes to a 9
and line 280 ~ollows suit. ~he initial 1 on ~he line 280
is communicated ~o the rese~ line ?84 of the CPU 66 as.a a
1~ by passage through a ~R gate 2B2. The other input to the
N~R gate 282 is a line 286 from a deadman reset circuit
288. The:line 286 ~s normally ~ logic 0 except ~hen there
is a problem, as ~ill be described below. With the line
2B6 normally logic 0, the ini ial logic 1 on the line 2R0
~5 is inverted by the N~R g~te 2B2 ~nd resets the
microprocessor 66 to the beginnin~ ~ddress of the
program. Thereafter, the line 2B0 goes to ~ logic 0 and
~ays ~here.
The deadman reset circui~ 2B8 serves to reset the
29 microprocessor 66 in c~se tkere is a so~tware pro~lem.
Normally, the deadman reset circuit 288 will attempt t~
reset the micropr~cessor 66 periodically unlefis tbe
software gives a trigger ~ignal nD/M Srigger" cn the line
~90. Thus if for ~ome reason the siynal Df~ trigger doeg
not ~ccur, prosram contr~l is l~st; and the deadm~n reset
circuit will cause the program counter t~ be reset to the
beginning program location,
The manner in which the deadman reset function is
accompli~h~d is through the u~e o~ two retrigserable
~bnost~ble multi-vibr~tors 292 and 294. The one shot 292
h~s its ~ and ~lear (RD2) inputs coupled to a ~5 v~lt
~urce throu~h a resistor 2g6 and are therefoxe ~lways ~n
a logic 1 ~tate. ~he 0 output on the line 298 is no~mally
low until a nega~ive ~ransition occurs on the D/M trigger
line 290, ~t which time the 0.output line 298 go2s to a
logic 1 s~ate for ~ ti~e determined by the values of the
J~
~C37~6~
-21-
resistor 300 and the c~pacitor 302 coupled to the external
RC ~ircuit terminals. H~wever,the pul~e time e~tablished
by the resist~rs 300 ~nd 302 is l~nger than the peri~d ~f
~he D/M trigger ~ignal. Th~s, the output line 298 will
n~t return to zer~ after the ~ni~ial trigger pulse because
~he D/M trigger signal on the line 90 continues
retrigger the ~ne ~hot 292.
The si~nals on the lines 298 and 2BO are c~upled to
the input~ of a NOR gate 304. The output line 30S of the
N~R gate 3D4 is coupled ~ the clear input o~ ~he one shot
294. The B islput of the ~ne Ehot 294 is held in a l~gic 1
c~ndition by connecti.on to a ~5 volt ~upply thro~gh the
resist~r 296. The A input of the one-Ehot 294 i~ coupled
by a line 30B to the clock 252 and ~arrie~ ~ 600 hertz
cl4ck ~ignal.
After the ini~ial power up period, th~ gate 304
will h~ve a logic O ~t the inp~t c~upled to the line 280
and a logic 1 at the line 298 input unless the D/M trigger
sign~l on the line 290 does n~t occur. The output line
306 will remain in a logic 0 state at all times which
causes the ~ne sho.t 294 tc ign~re ~11 signals Bt the A and
13 inputs. ~3oweYer, if the D/M ~rigger signal on the line
290 fails to occur on ~chedule, indic~ting ~ome problem
with the program execution, the one shot 29~ will time out
2~ and enable the one ~hot 294~ The ~lock signal on the line
308 will then trigger the one sho.t 294 causing a logic O
to 1 transition on the line 2B60 Thi5 causes the line 284
to drop fr~m logic 1 ~o O and reset~ the microprocessor
66.
Referring ~o Figure 6C, there is ~hown a l~gic diagram
of the decoder eircuitry whi~h form~ part of he deco'der
86 in Figure 2. The dec~der ehip 248 has its select
inputs coupled t~ the AI2-AI~ }ines of the addre~s bus 42
of ~he micr~pr~ce~r 66. The G1 enable input 3~0 is
c~upled ~o the ~2 vut~u from the microprocess~r 66 which
i~ the ~lo~k signal for the re~t of the sy5te~. ~he G2A
:X .
. . .
~2~7~36~
-22-
enable input low by virtue ~f being couple~ ~o a logic 1
through ~ resistor 312 and 2n inverter 374. The g2B input
is c~upled to the power on clear sign~l PONCLR ~n the line
280.
The decoder 250 has its ~ and B ~elect inputs coupled
to the address bus 242 ~nd its C ~elect input coupled to
the R/W ~ignal ~rom the ~icropro~essor 66. The Gl enable
input is c~upled to the ~2 clo~k ~ignal from the
micr~processor 66, ~nd the G2A en~ble ~ignal is connected
to the Y0 ~utput fr~m the decoder 248. ~he G2B enable
input is coupled to the A7 line of the ~ddress bus 242
from ~he microprocessor 660
B~th the decoders 24B and 2~0 Dre 74L513B one of eight
decoders ~uch ~s are manufactured by Texas Instruments.
t~ The outputs of the ~w~ decoders 24B and 250 are coupled to
the various chip select input~ in ~he syst~m as labelled
in Figure 6C. By writing the prop~r ~ddresses cn khe
address lines 242, the microprocessor 66 can enable any
chip in the syst2m needed ~or a parti~ular operation.
Turning to Figure 7 ~here is shown a logic di3gram of
the CCM~COM board 90 in ~igure 2. ~ plurality of alarm
~ontacts are c~nnected ~o the b~ard by a plural~y of wire
pairs together comprising ~he ~us 30. ~ach pair in the
bus 30 is ~nergiz~d by connection o~ ~ne of the lines
2g through one of ~he resistors 313-320 to. ~ 50v~1t power
~upplyO The ~ther line from the pair is cQupled through a
par~llel ~C n~ise s~ppression circuit to the anode o~ the
dio~e in one o~ the ~p~ical is~lators 321 32B. The dio~es
~re energi2ed ~s long a$ the external contacts c~upled to
~he wire pairs are ~losed.
The transi~tors in the optical isol~t~rs haYe their
coll~ct~r5 c~upled to a ~5-volt regul~ted power supply
thr~uqh one of the resistors in the re~i~tor block 329.
The c~llector~ are also coupled to the dat~ channel~ of a
3~ multiplexer ~30 which is typically ~ 14512~ type
multipleser such as i5 made b~ ~otorola. The data-input
~7~
3--
of the mul~iplexer i~ coupled ~o the D7 d~ta line 63 ~f
She microprocessor 66. The ~elect inputs 332 ~re ~upled
t~ the A0-A2 address lines sf t:he ~icro~rocessor 66 such
th~t the microprocecsor can individually redd e3ch
5 external contact ~ondition thao~gh ~he D7 da~ line 63.
The microprocessor 66 is programmed to periodically
check 1;he ~ondition of each of the external contacts
coupled ~o the bus 30. After ~he corltact is read, the
~icroprocessor 66 c~perates c~n a flag ~o indicate the
10 status of ~he alarm cc>ntact corresponding to that flag.
The flass are address position~ in a RAr~ memory 334 which
~an be ~ ~116 type CMOS static ~ sue!h RS iS made b~r
Hitachi. The ~ddress inputs o~ the RAM 334 are`couplèd to
~he address lines 242 of th~ mi~roprocessor 66, and the
15 data l/O ports Df the ~A~ 334 are coupled to the
data lines ~40 of the micropr~essor 66. The R ~ input
line 335 of the RAM 334 is couple~ to the R/W csntrol
si~nal from the microprocessor 66 to c~ntrol the direction
of the data flow on the data lines 240.
~he chip ~elec~ input line 3~6 of the RAM 334 is
coupled ~o the ~3 ~utput of a decoder 338 which has its A
and B select inputs coupled to the V~A contrDl ~ignal line
184 and Al 1 address line respectively of the
microprocessor 66~ The en~ble input ~ignal Es~o on the
;25 line 192 for the decoder 338 is ~oupled to a chip select
~output from the decoder 248 in ~igure 6C ~uch that the
:microprocessor 66 ~an enable the RAM 334 by enablin~ the
decoder 338 ~nd writing the prvper bit on ~he ~1 line of
the address bus.
3D Only two outputs from the dec~der 33B are used ~o only
~ne addres5 bit is needed to ~pe~lfy whi~h o~tput is
active. The other ~utput on the line 342 is co~pled t~
~he chip select inpu~ 342 ~f a relay driver 344~ This
X . .
.
~ 7~
24
driver 344 has three address inputs 346 which are co~pled
to the address lines of ~he microprocessor 66~ The rela~
driver ~ls~ has a data line 34B coupled to the buffered D~
d~ta line of the microproces~or 66 throuyh ~ 74L~04 buffer
349 on Fi~ure 6C. The relay driver 344 h~ ~n output 350
which is coupl~d ~o the coil of ~ COM relay 352~ When he
mi~roprocessor 66 ~elects the relay driver 344, and writes
the proper address on the lines 3~6, the line ~43 will
con~rol the state of the line 350, thereby controlling the
~tate of the relay contacts 354~
Turning t~ Figures 8A ~nd 8B there is shown a logic
~iagram of the cir~uitry of ~he dèlayed 'ransmission
~uffer 88 o~ Figure 2. A bat~ery backup circuit 3~6 in
~igure 8Bserves to protect the information in the RAM
1~ chips shown in ~igure 8B~ Each ~f the RAM chips is a
6116LP-4 CMOS static RAM ~uch as i5 manufactured by
~itachi. The ~5-volt line supply voltage on the line 358
nonT ally causes a forward bi~s on the diode 360 and the ~5
volt signal is thus coupled to the output line 362.
20 ~owever, when the power fails, the positive voltage 3n the
line 354 from the hattery 366 exceeds the ~ age ~n the
line 3~ which causes a reverse bias on the diode 360.
The diode 368, h~wever, will be ~rward biased ~uch ~ha~
the battery p~wer will be c~upled to the line 362 to keep
the information in the RAM int~ct.
~ series of dec~der~ ~70-372 ~re ~upled t~ the ~11
line of ~he address ~u~ 242~ These de~ders ~re 74L5139
one of four dec~ders in the pre~err~d emb~iment. Th~
deeoders have outputs 373 37B whi~h ~re ~o~pled. to the
3~ chip ~eleet inputs of the 6 ~AM ~hips of ~igures 8B
through a p~wer fail dete~t ~ir~uit 3R~ E~h deeoder ha~
itfi B en~ble input ~upl~ to the V~A output 184 from the
~icr~pr~oessor 66 to enhble the dec~der t~ ~e~d the All
~it when-the dec~der ba~ be~n en~led. The decod~rs 370-
35 372 ~re enabled by enable ~i~n~l on the ~ne 379-~81
eoupled to the ~ecoder 248 in Figure SC~ A p~wer ~
~3LZ~
-25-
circuit 382 sen5es when the line power represented by the
voltage on ~he line 358 h~s failed by comparing the
volt~ye at node 386 maintained by the line to the volt~ge
~t ~ node 388 maintained by ~he b~ttery 366. ~ comparator
390 ~hanqes the ~tate ~f its ~tput 392 when the battery
vol~age at the node 388 exceeds the line volt~ge ~t the
node 386. The compara~or is a National LM311 in the
preferred embodiment.
The ~hip select ~ignals on the lines 373-378 are
individually ooupled ~hrough ~4L532 ~R ga~es 343-398 to
the chip ~elect inputs of the RAM chips in ~igure BB.
Each chip ~lect input is also coupled-~hro~gh the OR
gate~ 393-398 ts the output 392 ~rom the comparator 390
~uch tha~ when the comparator finds ~ railure of line
powerr ~11 the ~AM chips in ~igure 8B will be deselected
~o as to maintain the integrity of the data~
The connections and funotionin~ of the ~ hips of
~igure 8B wil~ be apparen~ to tho~e skilled in thQ art.
Data from the microprooessor 66 is input ~nd output on the
linPs 24û t~ and ~rom t}2e addresses on the lines 242.
Turning n~w to Figure 9 there is shown a flow diagram
of the steps taken by the card reader in performing a time
~nd attendan~e fun~tion. In this fun~tion, ~he card
reader reads cards and l~cally authorizes entry or
dep~rture based upon the sys~em c~de o~ the card without
c~nsulting the ~entral controller ~nd s~res the data for
each transaction with tbe l~cal time for la~er reporting
to the central c~ntroller.
Xn 2n initiatization step 4 lOr the microprocessor ~PU
66 clears the RAM 80 on powerup. Thereafter, the CPU 66
transfers ~n the path 41~ t~ the exe~utive r~utine 4g4
where ~everal h~usekeeping functions ~re perfvrmed~ One
of these functi~ns is to check f~r the presen~e of a card
in the card sl~t. This fun~tion i~ represented by the
3~ transfer ~n the path 417 to the ~t~te 413 where the card
~wit~h is che~ked via the line 130 and the ~VX 60B in
~7~3~8
26-
Figure 4 ~o determine if there i~ a card in the card
~lot. If n~ eard is in the 61~t~ the CPU returns to the
executive routine 414 by the path 416. In ~he executive
routine, certain basic tasks are performed. For ~xample,
5 the CPT~ checks whether ~ command ~rc~m ~he central
~ontroller 2~ has been received, whether a poll from ~he
central c~ntroller needs to be acknowledged or whether
there is a reques~ fc>r time from the local ~c~ntroller.
Periodically, the CPU return~ to the state 413.
If ~ card was found in the card slot, the CPU
transfers t~ a decision ~tate ~18 along the path 420 to
determine if the s~stem co~e on the card in the slot
matches the system code ~e~ ~n ~he switches 140 in Figure
d, To do this, the CPU 66 individually addresses the
15 reading coils in the card reader 74 in Fi~ure 2 via the
bus 64. The data fr~m each ~oil is transferred to the CPU
66 via the coil detect line 57, MUX 60A, D7 line ~3 and
the bus 64 in ~igure 2.
If there is no match, the CPU 66 transfers to a no
?0 authGrization ~tate 422 via the path 424~ In this state~
~he CPU causes the display 40 in Figure 2 for a preset
time to blink in a manner known to those ~killed in the
art and turns on the red LED in ~he LED block g7 in Pigure
2 f~r a preset time vi~ the line 96, the driver 70, the ~0
line 68 ~nd the bus 64. ~he ~PU S6 then returns the
executive state 414 via the path 4~3.
~ f ~he system c~de matches, the CPU 66 tr~ns~ers to a
bu~fer full decision state 424 vi~ a path 4~6 to determine
i~ there is room in the RAM buffer 8a in ~igure 2 to ~tore
30 the present tr~nsactionO If the buffer à~ full, the CP~
transfers to a state 427 via a path 42~ to ignore the card
~nd display ~ message on the display 40 in ~igure 2
indi~ating that the buffer i~ ~ull. The CP~ then
transfers back to the executive ~tate 414 by the p~th 430O
3S If the buffer i~ not full, the CPU tr~nsfers to ~n
~uthorization sta~e ~32 by ~ path 434~ In ~he
X
~207~8
-27-
authvrization state the CPU performs ~ ~a~ksD Firs~ the
ID c~de from the magnetic card ifi ~tored in the buffer 80
~long with the time of day an ~t~tes 436 and Ç36. Then
~he Gb rel~y 7~ in Fiyure 2 i~ en2rgized PQr a preset time
via the bus ~4, the D0 data bi~ line 68, the ~ddress line
A0-2 and the driver 70. The Go relay is energized for the
time ~et by the swit~hes 13B in ~igure 4 60 they must be
read via the multiplexer 6DB ~nd the D7 dak~ bit line 630
~ inally, ~he ~reen LED in ~he L~D bl~ck 97 in ~igure 2
is turned on for a preset ~ime via the line 96 and the CPU
displays a WGo~ message in ~he display 40 as represented
by the states 44~ ~nd 444~ The CPU 66 ~hen returns to the
executive state 414 via the path 446.
Turning to ~igure 10 ~here is ~hown a flow diagram of
~he ~teps which are ~aken to transmit the da~a in the
buffer 80 to ~he centr~l contrsller 20. The ~teps o~
Fi~ure 10 are ~aken each ~ime a poll signal ~omes in from
the controller 200 The CPU normally opera~es in an
executive m~de symboli2ea by the state 441 in ~igure 10.
The executive jump~ to various ~ubr~utines which per~
housekeeping and command scan ~unctions as mentioned
earlier. These ~ubroutines are symb~lized ~y ~he state
443. One of the functions is to peric~dically check for
the presence o$ ~ poll ~ign~l from the con~roller 2D in
Figure ~. The pc~ll signa~ is sent per~odically to ~ach
card reader in the system Vi8 the enable pair 26 c~upled
th~t card re~des. The check f5r the pre~enc~ of a p~ll
signal is symboli2ed by the ~tate 447 in ~i~ure 1~. If nD
poll has been received, the CPU returns to .its other
housekeeping function~ in the ~tate 443 via the path 449~
If a poll has ~e~n ~eceived~ the CPU will ch~ck ~n
int~rnal eounter which i. incremented esch ti~e a
transaction is st~red in tbe ~uffer ~0. This operation is
~ymbolized by the block 451 an Fi~ure 10. If the count is
non~z~ro, then, the CPU ~nOwB that there i~ data in the
buffer 80 whieh needs tv be tran~mitted t~ the eentral
~( ' .
~7~
-2B-
contoller 20. Transfer is then made to a ~te 448 by a
path 450. If ~he ~ount is 2ero, the CPrJ returns to its
other functions because there i~ n~ data to transmit.
This ~ransfer is symbolized by the path 4~3~
~n the state 448, the CPU ~etermines if the buffer
option data is present in the ~eature memory gR in Figure
2. If the feature is present, he CPD will retrieve the
data for one transaction from the buffer 80 and transmit
it to the central controller 20. Thi~ ~perati~n is
1~ symboli2ed by the state 454 in Figure 10 and is
~ccomplished by .addressing .one of .he.transact~ons in the
. buffer 80 and reading the data there by the ~us 64.. The
data is then c~nverted to serial ~r~at in the CPU 66 and
sent via ~he D~ data bit line 68 ~o the driver 70 in
15 Figure 2O The driver then places the data on the Tx data
lines 58 and it is sent ~hr~u~h the ~pti~l is~l~tor board
54 onto the data line 2~ t~ ~he central ~ntroller 2~.
The CPU then returns to the executive r~utine via the path
456.
I~ the buf~er option is not present, ~he CPV S6 will
transfer to a state 460 by ~ path ~5B where it che~ks for
the presence of a card in the card sl~ . If there is a
c~rd in ~he card reader, the c~rd data will ~e read by the
CPU 66, converted to ser~al fvrmat and transmitted to the
central ~ontroller 20D This ~tep is symb~lized by the
hl~k 462. Con~rol i5 then returned to the executive.
If there is no ~ard in the reader, the CPD will
transfer to the state 464 via ~he path 466 to determine if
there is a time request pending. The card reader. which
30 have the time and ~ttendan~e function keep the local time
but peri~dically reguest the time fr~m the cen~r~l
controller ~o as t~ synchronize the local time ~ith the
eentral e~ntroller timeO If there is a ti~e request
p~ndin~, the card reader will a~k ~he time of the c~ntral
35 controller 20 as symbolized by the s~ate 4~6 and return to
~he execu~ive vi~ the pa h 4680
X
~Z~86~31
-29-
If n~ time request is pending, the CPU will
acknowledge the poll ~s ~ymbolized by ~he ~ate ~70 ~nd
return ~o the executive r~utine by he path 4~2.
~ urning t~ ure 11, ~here i~ ~hown a flow diagra~ ~f
5 ~he time o~fset routine performed by ~he CPU 66 to ~eep
track of the local ~ime ~r~m the central rDn roller time
when the ~entral ~ontroller i~ in ~ dif~eren~ time zone
~rom that of the reader.
The first step in the process is to read ~he offset
10 switches 136 in Figure 4 thrQugh the MUX 60B. The value
of ~h~se swi~ch~s is stored in RA~ at a ~peci~ic
address. ~hi~ is done 600 ~imes per ~e~nd in ~he ~tate
474.
Next, the CPU 66 convert~ th~ data in ~he RAM ~witch
l~ data ~ddress to minutes and h~urs of ~f~et. The data
from the 8~h switch determined whether the ~ffset is
positive or negative while he fir~ 7 ~witches provide
binary number representing up to 127 minutes of offset.
Any number of swit~hes could be used, however. This is
20 -cymbolized by the states 476 ~nd 478.
Finally, the l~cal time is offset in a ~ta~e 480 and
stored in a loca.l buff~r of~se~ time a~dres~. Control is
~hen returned ~o the exe~utive routine~
Referring ~o Fiyure 12 there is shown a flow diagram
25 for the steps taken by the CPV S6 in handling transactions
during a degraded m~de when c~mmuni~ati~n with the ~entral
controller 22 is lost. The blo~ 415 symbolizes the
executive routine. The background blo~k 4~3 ~ymbolizes
al~ the routine houseke-eping che~ks and functi~ns ~hat the
30 card reader does when it i~ no~ doing one of the
fore~round routines to handle ~ertain c~nditions the CPU
dis~overs during the executive rou~ine. ~art of the
normal executive rou~ine i~ to ~he~k ~or the peri~di~
~ppear~nce of a poll signal fEOm the central controllerO
35 This check is symboli~ed by the block ~90. ~hi~ ~unction
i~ implemen~ed by ~he CPU 66 in determining whether a poll
X
signal has arrived in the preceding 30 ~econds. If a poll
signal has arrived during the last 35 secon~, then there
i~ no degraded m~de ~nd the CPU 66 determines what type of
command has been re~eived, if any, ~nd pr~esses the
5 command as symb~lized by the bll~cJc 492. Control i~ then
returned to the executive rc~u~ ine by the path 494.
If a poll signal has not ~rrived durin~ 'che preceding
30 secords; the card reader CPU 56 knows tha~ ~omething is
wrong and enters the degraded m~de. This is ~ymbolized by
the path 496. The f ir5t ~tep iS to determine i~ there is
~ card in the reader slo~. Thi~ tep is ~ymboli~ed by the
blo~k 500. If there ~s no~ ~ card in~the reader, control
is returned to the executive background lo~p 4i3 as
symbolized by the path 498.
~f there is a ~ard in the reader, the CPU 66 addresses
the feature memory 98 in ~igure 2 to determine if the
buf~er option is presentO This is symbolized by the bl~ck
502 in Figure 12.
I~ the buffer option is not present, then no storage
20 of transaetions during he degr~ded m~de will occur.
However, it is ~till possible to ~uthorize or deny access
to a ~ard holder based upon the ~ystem code ~hat is on his
card without storiny the I.D. code ~nd time of day in a
buffer. To determine whether or not ~ do this, ~he CPU
25 66 must again address the festure memory 9B to determine
whether the degraded m~de option is present. This
operation is ~ymboliæed by the bl~ck 504 in Figure 12. If
the degraded mQde opti~n ix n~t in effect, the C~ returns
to the backgroun~ loops ~43 by the path 506.
3~ If the degr~ded mode option is present, the CPU reads
the system ~ode on the magneti~ c~rd in the r~ader ~lot
via the card reader coils 74 ~nd .hen reads the switche~
140 in Figure 4~ The CPU 6~ c~mpare~ the system code sn
th~ card to the system code on the ~witches for a match.
3~ This ~omp~ris~n is symb~li2ed by the block ~08 in Figure
12.
;X
8~6~
If there is n~ match~ the CPU 66 turns ~n the red LED
~or a time ~et by the switches on the ~witch ~nd rel~y
b~ard 62 in ~igure 2~ This indicates n~ auth~rization ~s
~ymb~lized by the ~t~te 510~ The CRU 66 then ~ddre~ses
the feature mem~ry 98 to dete~mine if ~he no 9~ ~ption is
in effect, as ~ymb~lized by ~he ~ta~e 512. If ~t i~ n~t
in effect~ the CPU 66 returns ~o ~he backgr~und l~ps 443
via the path 514. If the ~pti~n i~ in effect, the CPU
addresses the no g~ relay 166 in Figure 4 through the
lO driver 70 by placing the proper address ~n the lines 172
and writing a l~gic 1 on She buffered'D~ dat~ bit line
6R~ The `n~ 9~ ~e~ 166 is ther~y energize~ fQr a. time
set by the switches on the ~wit~h and relay ~oard 62, and
whatever external device th~t ~s coupled to the no
15 relay c~ntac~s through the lines 167 will be signalled
~ch3t an unauth~rized person has at~empted ~n entry. This
operation is symb~lized by the-block 516 in Figure 12.
If ~he system c~de on the switches match tha~ on the
card, the CPU 66 energizes the green LED in the LED block
2D 97 ~f ~igure 2 for a predetermined time. The CP~ 66 als~
energizes the go relay ~1 in ~igure 4 for ~ time ~et by
the ~witches 13B. ~his is done in ~ ilar manner to
that ju~t described for the n~ go rel~y. This operation
is symboli2ed by the ~lock 51B in Figure 12~ Control is
25 then returned to the background loops 442 via ~he path
520.
R~turning ~o the sta e ~02 in ~igur~ 12, if the buffer
op~ion is present, the CPU ~6 check~ its in~ernal counter
~o de~ermine if the buf~er 8B in ~igure 2 i~ .full of
30 transaction dat~. ~his i~ ~ymbolized by the block 528 in
~igure 12. If the buffer is full, the CPU ~6 ignor~s the
card and transfer~ back t~ the bac~ground loops 443 5S
symboli~ed by the path ~31 thro~gh the s~ate 522.
I~ the buffer i~ n~t full/ the CPU 66 will read the
35 system ~ode ~witches in Figure 4 and the ~ystem code da~a
on the card ~nd ~ompare them ~ ~ymboli2ed by tbe block
X
--32--
530. If there i5 no match, the red LED in the LED blc~ck
97 in Fig~:re 2 will be turned on for a time as ~ymbolized
by ~ transfer to the state 510 via the path 532 in ~igure
12. Processing ~rom the ~tate 51D will continue as
previously describe~.
If the ~ystem code does match, the CPU will ~tore the
~ ode from the card along wi h the loc~l time in the
delayed tr~nsmission buf~er ~8 o~ ~igure 2 ~s .ymbolized
by ~he block 533. Th~ green ~ED and Go relay are then
l~ energized for a preset t~me in st~te 5~8.
The bu~fer 88 i5 unlo~ded one transaction at a time
wben communications ire restored. Ref~rring ~o Figure 13,
. . . . .
there is shown a flow diagram o~ the manner in which the
CPU unlc~ads the bt~f~er. During the executive b~ckgr~und
l~ routine, the CPU 66~continually checks for the presence of
a poll signal from the ~entr~l controller. When a poll
finally arrives, the reader knows that communications haYe
been restored. This monitoring function is ~ymboli~ed by
~he bl~ck 540 in ~igure 13. If no poll has arrived, the
CP~ returns to its other ba~kground functisns as
~ymbolized by the path ~42.
If a p~ll has arrived, the CPU 66 will check to ~ee i~
any higher priority messages sre ~aiting t~ be ~ent as
symbolized by t~e block 544. If there is such ~ messager
it is sent, as symbolized by ~h~ block 546, ~nd control is
returned to the backgr~und rou~ine of the executiYeD
I~ n~ higher priority message is w~itin~, ~he CPU 66
will de~ermine if there are any transa~ti~n~ ~t~red in t~e
bufer waiting to be 5ent as symb~lized by the block
30 S48. This i5 don~ by consulting the internal ~ounter in
~he CPU 66 to determine ho~ full ~he b~fe~ ~ is. I no
data, i~ in the buffer ~, the CP~ determines whether
there is a ~ime reque-rt p~ndin~ ~ sym~olized ~y the bl~ck
550O If there i~, the CPU 66 moves to the ~tate 552 to
35 reque~$ the time from the ~entr~l eontroller and then
returns to ghe executive routin~O If there is n~ time
'Y
-33-
request pending, the CPU 66 will ~knowledge ~he poll in a
~tate 554 and return to the execu~ive routine.
Returning to the state 548 ~n Figure 13, if there ~are
transactions in the buf~er 88 to be ~en~, he CPU 66 will
retrieve one transac~ion data group~ ~orma~ it for ~erial
~ransmission and transmit it ~n the Manner previously
discussed, using the D0 data k~it line 68, the driver 70,
the ~ddress lines AO-2, the T:c data lines 58. and ~he
isolation board ~4. The format for the transmission in
10 the preferred embodiment is ~ header identifying the type
of reader wi~h the data, followed by a c~ndition code
-indica~ing the type of transa~tion ~hat has been
retrieved. Following ~he condition code, the I.D. data
from ~he card is sent a~ong with the t~me o~ day whe~ the
lS transaction occurred. These steps are symbolized by the
block 5~6. Any format for transmis~ion will do,
however~ Control i.~ then return~d to the executive
routine.
Turning ~ow to ~igu~e 14; there is ~hown a ~low
2~ diagram of the steps the card reader CPU 66 takes in
monitoring the alarm contacts connected to the lines 30
fro~. the CCM/COM board 93. ~he rout,ine illustrated in
Figure 14 às executed by the ~PU 600 times per second ~nd
is ànte~ded to sense the condition of the flags which
25 symboli~e the.stat~ of the alarm contactsO The ~irs~. ~tep
is to read a CCM flag N to determine the last state of the
flag. This step is symbolized by the block 560 in Figure
14~ To do ~his the CPU 66 pick~ the address ~or the flag
N in the R~M 334 of ~igure 7 ~n~ writes that addr2ss on
30 the lines 242 after ~electing the RAM with the All and VMA
lines coupled to the de~oder 338 to drive the line 336
low. The R~W input of the RAM 334 is driven o the read
~tate by the mi~roprocessor 66 in Fiyure 6~.
There are four possible ~tates for the flag
35 symbolixing the ctate of i s correspondiny alarm
cont~ct. ~he ~lag ~an show ~op~n and rep~rted~, Wclosed
X
~z~
~ 34-
and unreported~, ~open and unreported~ or ~clo~ed and
repor~edW. ~n~ 8 bit byte as used to symbolize ~hese
~tates~
~f the flay ~hows ~clos~d and reported~, the CP~ 66
S ~ust know whether the ~larm cont~c~ N has ~h~nged s~atus
since its last state ~s indicated by the flag N.
Therefore, the CPU 66 ~auses the alarm ~onta~t ~ to be
read. ~his step is represented by the ~ransfer on the
path 561 to the block 566 and ~s physically ac~omplished
lD by selec~ing the contact N ~ddress and writing that
rddress to the multiplexer 330 on the lines 332 in Figure
7. :The CPV 66 also enables the multiplexer ~3~ ln-any
known manner util~ing the CSCCM signal connected to pin
15 of the multiplexer 330. The CSCCM signal can be
lS generated by decoders 60upled to the address bus of the
CPU 66 or in ~ny other known manner. ~th the address on
the lines 332 set, the multiplexer 330 will select the one
~f its outputs X0-X7 for conne~tion to the D7 line coupled
to the CPU 66 da~a bus 64. The CP~ 66 ~an then read the
2Q desired contact ~hrough one of the optical i~olators 321-
328.
If the alarm cont~ct N i~ open, the C~ ~6 knows that
the alarm contac~ has changed its status 6inoe the last
time it was read and that this fa~t must be reported.
25 Therefore the CPU changes the state. of the flag N to an
~open and unreported~ sta us. This operation is
~ymbolized by the transfer on the p~ h 567 to the block
568 in Figure 14. Because the st~tus- of the alann
cc>ntacts has changed, the CPU 6~ must update one bit of
3~ th~ status word that i~ Xept ira RAM to indicate the status
of the alarm contacts~ The ~tatus word has one bit for
each alarm contact t and the bit for contact N is cha;~ged
to indicate tbe most current st~tus. Thi~ operat s:n is
symbolized by .he transfer to the l:loek 570 on ~he pa~h
35 5690
X
~7~8
~35-
After the ~tatus word has been updated 9 the CPU 66 is
ready to move on to read the n~xt flag. TD do this, N
mus~ b~ incremented. This ~tep is represented by the path
571 to ~he blook 572~ Af~er ~ is incremen~ed, the CPU 66
5 ~u~t know whether it has oompleted reading all the flags
and con~acts. To do this, the C~U ~ompares the value of N
after i~ has been incremen~*d to the gotal number of alarm
-c4nta~ts ~or,nected to the lines 30 in ~igure 2. In the
preferred embodimRnt, ~his number is 7, but it ~an be any
lO number depending upon how ~uch hardware is av~ilable.
This comparison oper~tion is represen~ed ~y ~he block 574
in Figure 14. ~ ~. is -less than or egual to 7, the.CPU
returns to the sta~e 560 by the path 576. If, however, N
is greater than 7, ~he flag reading tasX is finished ~nd
l~ ~he CPU 66 returns to the executive routine 8S symbolized
by the blo~k 578.
If the flag ~ had been in ~he ~open ~nd r~ported~
state, the C:PU wol~ld again like to know if there has been
any chanqe of status of the alarm conta~t associated with
20 ~he ~12g N. To determine ~is, ~he CP~ ~6 reads the
contact N. This operati~n is ~ymbolized by the path 582
to the ~tate 5a4.
If the contact N is open, there has been no ~hange
from its last status and the CPU 66 is ready to read ~he
25 next flag. N will be incr~mented and processing ~ontinues
~s previ~usly described. ~his operation i~ sym~olized by
the path 5~6 to the state 572 previously discus~ed~
~ f ~he c~ntact ~ is closed, the CP~ 6S knows there has
been a change in s~atus since the last che~k.
30 A~cordingly, the C~ 66 must ~et the flag N tQ indicate
the ~ontaot ~ is now ~losed and unreported. ~hi~
operation is sym~olized by the transfer on he path 5~ to
the .~ate 90 in ~igure 140
Because there has been a change in the sta~us of one
35 of the alarm conta~t~, the ~tatus word ~u~t be updated,
This operation is symbolized by the trans~er on the path
X
8 6
-3~-
~92 to the sta~e 57D, Pro~essing then continues as
previously described.
Returning to ~he ~tate 566, if ~fter re~di~g flag N
and finding ~ts ~tus ~o be aclosed and reported~ the
SPU ~6 then reads the contact N ~nd ~inds that lt is ~till
~losed, there has been no ~hange in ~he ~larm contact
~ondition since the last re~ding. Thus there is no need
to change the fl~g ~tatus and there is no need to ohange
the s~atus word. Ac~ordingly, the CP~ 66 merely
increme~ts N as symbolized by the transfer on the pa~h 567
to the state 572. Processing then con~inue~ ~s previously
described.- - - . ~ .
If in the state 560, the CPU 66 determines the flag N
is either ~closed and unrepor~ed~ or ~open ~nd
unreportedn, there is no need to read ~he alarm contact
because the central controller has not yet been notified
o~ ~he change in status of the ~larm contact_which caused
the flag to be set in either o~ these two states. Since
notific~tion is the first priority, the CPU ~6 will merely
update .he s~atus word to indicate the new status and
continue reading the other flags~ This operation is
symbolized ~y the transfer on the path 600 to the
previously described ~ta~e 570.
Referring to Figure 15, there is shown a flow diagram
25 o the steps taken by the CPU in reporting the changing
conditlons on the alarm conta~ts coupled to the line~ 30
to the ~entral controller ~0 in ~igure 1. The routine
shown in Figure 15 is pe~iodi~ally executed when program
control o~ the CPU 66 is transferred ~ro~ the ba~kground
30 ~asks of the executive routine represen ed by the block
6~ to the routine of Figure 150
The first step is for the C~U 66 t~ read the flag N to
determine if it has been reported 9r is currently in an
unreported ~t~tus. ~f the ~l~rm contact N change in
35 statu~ h~s n~t yet been reported as indicated by an
unreport~d status ~f the fla9 N, then the CYU 66 ~end-~ a
X
3L2~73!~
.)
-37-.
CCM message to the central controller 20 reporting the
changed condition ~f the alarm contDcts N. ~hese
operations ~re represented by the block 604 where the flag
~ is read and the transfer ~n the path 606 to She ~lock
5 608 where the CCM me~sage is transmi~ted to the cen~ral
con~rollowr. Referrins to Figure 2, the CC~ message is
transmitted by formulation of the serial format mes~age
inside the CPU 66 ~nd placing it on the D~ data bit line
68 tG drive the driver 70. The address bit lines A0 A2
10 ~re held by the CPU 66 at the ~ddress which connec~s the
D0 data bit line to the Tx data lines 58. The serial data
CCM message then pas^ees through the optical isolators on
the isolation b~ard 54 and over the data lines 28 to the
central controller 20 in Figure 1.
The next step after transmitting the CCM message is
for the CPU 66 to determine if the flag i~ open or closed
to determine whether to w~hang2 ~he flag So a ~losed and
reported status" or an "upen and rep~rted status"~ This
step is represented by the t~ansfer ~o ~he state 612 by
2~ the path 610.
If the flag is open, the CP~ 56 transIers to the state
614 by the pa~h 613 to change the flag status to ~open and
reportedn., Control is then trans~ersed to the ~tate 602
by the p~th 616. If the fl~g i~ closed, the CPU 66 must
25 change the ~l~y ~o indicate that the ~ondition h~s now
been reported. The CPU 66 th*n changes the flay status to
0closed and reportedn ~ta~us. This is represented by a
transfer to the state 620 on the path 618. Con rol is
~hen returned to the state 602 ~y a path 622. From the
30 state 60~ pro~essing continues. The CP~ 66 th . n transfers
to the sta~e 604 where fl~g N is again read~ This time~
the flag N will ~how that it has been report~d ~o the P~
fi6 will increment N. This ii represented b~ he transfer
to the ~tate 624 by th~ path 642. The CPU 66 then
3~ compares the value of N to the maximum number of flags to
be read as represented by a tran~fer on a path 626 to a
X
\
-38-
6ta~e 628. ~f N is les th~n the m~ximum number of 1ags
in the ystem, ~ontrol i~ transferred b~k to the
exe~utive via ~ path 630. The next ~ime the executive
jumps to the rou~ine o~ ~igure 15, the CPU 66 will read
5 ~l~g N ~ 1-
-I~ N is equal to the maximum number o~ flags in ~he
system, the C~U 66 i~ finished reading ~ he flags and
need only deter~ine wh*~her the cen~r~l controller 20 has
requested the CC~ status word. This determination is
1~ represented by a trans~er ~o the state 63~ by ~he path
632~ If the ~entral ~ontroller 20 has not requested the
- - CCM sta~us w~rd, control is transferrea back to the
executive via the p~th ~36. If the central co~tr~lier has
requested the CCM status word, the ~tatus word is ~ent as
represented by trans f er to the state 640 on the path
638. Thereafter, control is returned ~o the execu~ive via
the path 642.
Referring to ~igure t6 there is ~hown ~ flow diagram
of ~he ~teps taken by the central controller 20 in Figure
1 ~o process messages ~rom the ~ard readers regarding
changes in the s~atus of the alarm contacts. The blocks
620, 622 and 624 represent individual readers in the
system which are coupled to the central ~ontroller 20~
Each reader has ~ts own data lines, such as data line 28
~or the reader N, upon whi~h data is transmi~t~d ~rom the
reader to the cen~cral controller 20. The controller 20 is
~180 coupled to each readar by enable liness ~uch as the
enable line 26 coupled t4 the reader N, upon whieh
commands are sent ~rom l:he controller 20 to the re~der.
30As represented by the blocks ~20, 622 and 624, each
reader formulates and s~nds a number o~ message~ to the
central controller~
~he messages received by the central controller 20 are
deciphered 'co determine what type of message it is ~nd
35 what is the data in the messageO This operation is
symbolized by the block 626.
X
97~6
-39-
One o~ the qllestions a-~ked by the controller ~s
whe~h~r or not the received message is ~ CC~ message.
This decision is represented by the blsck 628
If 'che mess2ge is ~ ~:CM message, he ~ontroller mus~
5 determine frc~m ~he data in the mes~ye which alarm contact
has ~hanged. ~his determination is represented by the
bloc~ 630. The reason for ~his determina~ion is that the
~on~roller ~nay no~ be programmed by the user tc~ do
any~hin~ in response to changes in cert~in alarm
10 c~ntacts. What the controller does in response to a
~han~e in ~atus of B particular alarm contact is user
programmableO The controller keeps a table of user
progr~mmable entries. The table can hàve an entry for
each alarm contact in the system or ~t may only have
1~ entries for some of the alarm contactsO This table is
called the CRO table, which stands ~or Conditioned
Response Option. ~ typical table entry would include the
alarm contact number, the contact condi i~n, the reader
loc~tion, the condi~ion response loc~tion, ~ CRO override
2~ command and time limitation data.
The controller, after decipheriny the CCM message,
mu-~t consult the CRO table to de~ermine i~ there is ~n
entry for tha~ alaraT cont~ct. If there is, the controller
will examine the cont~ct condition code, the alarm contact
number, and the reader loca~ion data in the CCM message to
determine if-it matches the entry in the CRO table. This
opera~ion is symbol~zed by the ~lock fi32 in ~igure 1 6 D
The time zone data in the CRO table ~an be user-
programmed to only allow the speeified ~onditioned
3Q response if ~he CCM messag~ for the contact ~n guestion
comes in within the time parameter~ Alternatively~ the
time ~one may be unlimited if ~he user pro~r~rns the
~ppropriate code, ~uch ~h~t the conditioned response will
oecur any time a message matehing the CRt) entrSY cc~mes into
35 the c~ntroller. ~his operation is symbolized by ~he block
63~ ~
~7~
.
,, ~o-
If there is a CRO t~ble ~ntry ~nd the CCM message
~o~es iA within ~he ~ime parameters of the CRO ta~le
entry, the ~ontroller will send ~ CRO cD.mmand ~ the
loca~ion ~pecified in ~he CRO ~ble ~ntry. This cou}d be
to ~he reader coupled to the CCM cont~c~ whi~h changed to
cause the C~ message in yuestion~ or it c~uld be to some
other reader location in the ~ystem. Thi~ operation is
~ymbol~zed by the block 636~ The CXO respon~e message is
sent So a buffer which holds ~essages ~o be sent to
particular readers until their turn for ~ransmission over
~he enable lines come up. ~he messag@s are ~ent on a
first come, first . ~erve basis. This mes-~ge buf~èring and-
.
the periodic polling func~ion of the central controllerare represented by the block 638~ The messa~es are sent
on one of tAe enable pairs 640.
The central controller also sear~hes the C~O table for
other entries resarding the same alarm ~ontact. That is,
the central controller may send one or more CRO responses
- to one or more locations in the ~ystem in response to a
2~ change on an alarm ~onta~t. The CRO response ~an be ~ny
of ~he reader commands ~sso~iated with the other reader
functions su~h as ~go o~f line" or ~send CCM status
wordn. In parti~ular, it may k~ a command to ener~ize a
COM relay anywhere ~n the syst~m. This Wenergize COM
relay", command, when received by the CPU 66 in the
re~der, causes it to address the relay 352 in Figure 7
through ~he ~ddress lines 346 after ~electing he driver
344 using the line 342 and the decoder 33Q. The coil of
the relay 352 i~ then c~nnected to the D0 data bit line
3~ 348 ~rom the CPU 66 in Figure ~ sueh that th~ ~PU 66 can
- energize the relay coil by wri ing ~ logic zeEo on the
line 348. This changes the state o the relay ~ont~ct 354
which notifies an external device ~oupled to the relay
contacts 354 ~y the lines 38 that fiome action is needed~
35 The external device can be ~ fire ala~m~ sprinkler system,
telephone dialer or any other device.
`. )'
`` 3~2~
~4 1--
~ fter the CR0 message is ~ent~ the central con~roller
continues on with processing ~11 the incoming messages.
This is 6ymbolized by the ~ransition on the path 642 ~o
the state 644. The same would be ~rue i there were
5 either no CR0 table entry cDrresponding go ~he CCM message
or if the CCM message were o~tside the time zone set by
the CR0 table en~ry~ These two tran~itions are
represented by the paths 646 and ~48~ respe~tively, t~ the
state 644. The central controaller then sends data to be
10 printed regarding any or ~11 of the incoming messages to a
printer as represented by the block 650. The cen~ral
~ontroller may send-a message to ~he printer regarding the
CCM mes~age if desired.
This concludes the description of ~he system of the
15 improved card reader. Below there i~ listed the ma~hine
language in hexadecimal notation9 implemen~ing the
preferred embodiment of the flow diagram~ o~ Figures 9-
16. Appendix A is the machine language for the flow
diagrams of Figures 9-11. Appendix B is the machine
20 language for ~he flow diagrams of ~igures 1~-13. Appendix
C is ~he machine language for the flow diagrams of ~igure~
14-16
- ~
~; ~
"; ~Z~786~
-~2-
Ap~endix A
(c) copyright 1982 Rusco Electronic Systems-- a
division of Figge International, Inc. -- all rights
reser~ed.
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D4O F5 OO ~E 35 60 ~D BD ,O FO 15 BD 7D 8R FE 6a =CO
D5a FF 60 1r FE 60 24 FF 60 22 36 00 82 84 a4 ~5 03
DS~ 7~ 77 a~ CE FF FB 3D 7, ~D 39 FE 6~ 2~ 27 19 0g
D7a FF 60 24 F- 60 1r C6 aa 8C 6~ a6 26 35 CE 6~ 2~
DD~ Z3 01 a8 FF 60 lC OD 39 ac 39 ,D 60 CO 26 29 FE
s~a Oa 2a a3 r, 6a c-a zc 6a 2a~_~ aa O6 FF B7 6a z~
DnO OC 66 05 CD ~5 CE O0 2R Z0 O~ a8 FF Oa 20 BC 60
DBa lr~ ~6 97 86 FF B7 60 C-S 0C 39 9D 39 0e Qel 99 00
Dc~_aa_~a_Q~ _Qo__0_~s___~s_~a_d__~0_a0_0
~a aa ~a o~ aa-~v-~0 ao d0 a0 Q8 ~a a~ aa a~ aa~aa
DEa ao a0 a0 aq.~.s~-aa 0a aa aa-:a0 a0 Oo 0a a0 a0
2Fa ^a ao a0 ~a o0 aa o0 ao a0 3a 00 00 aa aa 08 aa
Eala--0~-0~-~a-~u-a~--ae-~a 0~~00~~0-ola--aa-a0-~0--a~-o~
E1~ a~ a~ 00 ~ O~ ao aa ~a a0 a~ a9 0~:9~ a0 0a 9Q.
C~D a3 aa aa aa aa ~Q ~a a~ ao aa aa Qa aa 0~ ao a~
~c ~ a~~0~00~00-o-a-0~-0-a--aQ-~o--Qs-~0-0~3-~o-a~--d~--3-a
E~a oo o0 aa 0'3 00 aa aa oa 3~ aa oa.a0 ao 3a 00 00
Er~_oa_l~_a0_a0__0_~3a_0~_~a0__a_~a__~,al3_0la-o0 v~a ~
E50 aq a0 aV~ aa a0 v~0 I)0 QO V~ 9~ aa aa 0~ aa aQ-la0~
E,0 oa 0~ 0a 0~ 00~a0 aa ~d ~0 a~ ~0 v0 ~0 ~a ~0 0~
E~a aQ a0 Qa 00 0a a0 oo-ao ~a aa ao a~ aa_a0 ao a0
,~c~a~aa~~va~a0-ao-a0-~v~-v0-^va-ao-a-va-2-a-a~v-a-a o~~aa~s0
E~a 00 V~ ~a 00 00 ~0 a'3 a0 00 aa.aa O0 ~a o0 a0 oe
~-r~ _s_____~_0~__0_00-~a--0-a--sQ-aa--0-0--tl~ aa_
~CO Q0 a~ a0 ~o Q0 Q0 ~Q ~ Q9 00 a0 aQ 00 ~ oa ~
E~a aa ~a aa a0 0a aa a0 a0 aa 3~ a0 a~ ~0 v0 0a ao
^- O QO aa aa a0 aa 00-o0 0Q 3a a0 a0 a~ 30 ~Q oa a8
~r ~~~va~~3~a~~0a~30~~v'~V~~3~0a~~3~~~v0-3o--3~-`3a-~-0-~0-t~3
OFf~ ao a0 faa 0a ao afd ao a0 ao 90 00 a0 0fa va a0 00
'.rf'a~aQ~~ad~f~0~a~~a~~000~~qa~0~~0a~~d~09~q~a~~a~~00~~aa~~
~F~a aa 00 a9 a0 a0 0a a0 a0 aa 0a a0 30 aa a0 ao a~
~ a aa aa aa a0 aa a0 aa aQ aa aa a0 oa a0 d0 da aa
F-.^~af~~v~0~fd~~f~0~f~a~s~~f~~a0~Q0-aa-a0-0~-f~0-f~0-oa--a~
F-~ a~ aa a~ q~ a0 aa ~a ~fd ~f~ ~v0 0~-0q a0 a0 00 af~
F7a ~Q Q0 a0 9a ~a 0Q Q0 a0 a0 a0 Qa d0 00 aQ aa 09
--FD-~-~d-a-aa-a0-~v-vo-v~d--va-~-v-a-a0-ao-~o-a-a-fd~-ov--a0
F~a fd~ a0 oa ao a0 aa aa 0fd a0 aa aa aa 30 ~0 aa o0
_f~Q_~a__Q_~0__e~Q__Q_3a_a~_aa_30 ~,~_a0_^0_0f~_
r^9 aa afd a~d ~d0 a0 aa aa fd0 a0 a~da aa a0 ~d~ afd as
F.a o0 ae QQ 00 fd0 oa a0 Q0 ~ds f~)Q ae Q~d 00 ~0 o0 as
. a aa o0 ae aa fd0 ao aa ~a aa a~ aa aa a0 ~a a0 ~v0
~,-- ~~a~v~0a~af~~f~~aQ~a~d~v~~~v~ao~va~f~a~3av-ldQ-~0-ld~a-0~
Fr3 aa ao aa ^va a0 oo a0 a~3 ,~ SD ,a Of3 ;1 O~ ?a ~df.~
-46-
Appendix B
(c) Copyright 1982 Rusco Electronic Systems -- a di.yision
of Figge International, Inc. -- all rights xeserYed~
00 gE 0~ 7F 7F 00 ~ 26 FF E7 00 ~ FE 40 2E ~ i2
1~ 34 27 ~C CE 0~ ~0 4F ~7 ~0 0~ ~C_~ 64 2~ F3 C
,0~~4~~0~~6F~~0~0~~~C 7~ 00 c~ F CL 41 c0 FF 4~ 3
3~ FF 40 32 FF 4~ 34 FF 4~ 36 CE 12 34 FF 4~ 2~ CE
4~ 0~ GF 00 ~ ~C 4~ 2E 2l~ F~ FE 40 ~ ~C ~ ~c
27 ~3 FF 4~ 32 FE 40 34 ~C 40 3~ 27 03 FF 4~t 3
~ FE 4~ 3~ ~C 4~ 3~ FF ~ 5
~D 7~ 7 ~ FF B7 40 cl ~c ~F ~ 0 9G 27 ~
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
0~_ ~D_~3 3~_2_ F_ c6 Fc_~F ~ ~e~ ~D 71 F~ ~ ?~ 26
1~ wE ~D 73 36 24 F1 ~iD 51 ~D 77 ~2 ~ 0~ c~ E~
7~ F2 ~D 73 36 2I Ed 2~ DE 7E 7el 0~ CE 4d e~l ~6~
3~ 6~ ~7 ~e? t~ e,~ 4~ F~ ~3 et3 ~ t~
~e~ 3~e,~ 3~,~c~~r~FF~~~ ~~F~~~3~cE~a~~~c~~r~
5~ C ~lel ~4 ~ F~ FF C~ ~tt~ t~ , ~ FF
~d Fr Z~ F~ _ ti~4_3~ ,-c_~~ _5_ _ t~t~__7 CE F~ ~ DF
_ _ _ _ _ _ ~ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ._ _ _ _ _ _ ._ .... _ .. .... _ ._ _. _ ._ _ _ _ _ _ _ _ _ .
3F ~ ~t~ 7F ~d ~ ~ 5E ~4 t~4 ~
E ~6 SE ~4 03 D6 3h C4 t~3 11 ~Ç 11l ~t, 5F ~ 0F
3 ~ 15 ~ iZ ~ 4 ~ 4 ~ E~
5 c~ 0~ CE FF EC 7E ~t; E~ ~:` Ft~ -L; f i Ç~ ~-E ~7
40 i5 3~ 7E 7e~ FC ~6 23 2~ ~F 36 30 :'sl ~t4 ~ 6 FZ i~
,r0 ~H FD E~ 7E 4~ 25 0~, F 00 ~ ED 7~_i5 .~E f~
~`0 ~D 7~ 3i ct~ ~3 4F CE Qd de~ r F 4d ~E iÇt ~
, el 71 C4 c4 2C FE ~t3 ZE O ~ ~3 4^j i is ~ 4^~ Ci C
0'0 d~ 0Ç c6 E~ ~F F6 4~ 2f ~D f' 1 C4 F6 4~ 0E E~
1~ 71 C4 FE~d 3~ FF 4d 4 FE 4d 31~ FF 4~1 3;~ ~D 39c~ 7F ~1~ c 33 FE ~1~3 3flCf i3 tJ3 FF 4d 3~ FE 4~; 32
3!~ 5C6F FF 26 05 CE 4l 2~ 2d ~ ;f~r3 FF ~d 32-
4~ 33 dC39 7 ~ 4Ci 3r2~i 29_FE 4d_3h_C1i's FF ~ 3;i
5t~3 FE 4el ;!6E7 dt~ 1~i FFE`7 4d ~E ~C 6F FF L-'r:~ er CE
ht~ 4i 2~ cdt~l ~1 FF 4~ 36 EC 43 3c c6 ~Jf ~ i FF 1~7
f ~ ~ t3 3 C r~ 9 r~ 3 ~ 9 6L ~ L ~ L- cf_ ~ L ~ 3
c r 3 L 4 9 ~ c r c ~ .~. f r 5 r - 4 _ ~ ~ F .~ _ c r~ 2 r~
r;~ i Lt ~ F ~ F .' ~
. C )~ L, '`. -- F F ~i .~ .~ ~ ~ ;~ - _ _ ~ ~ ~ r _
r.- ~ `E ~ll~l -C~ ~ 4 ~ ?_'~ F~
." - I, L i~l f , 5 F l- ~ F ^,i F
"3r j; 13~3 t~ l . rj ~ rl 11 r I -- ~.1 c 1~,1 -t 7 ~ ~;1 4 Lr Cl~
-E4-L--ç-F 7 3 ~ 4 n 2~ r~r ~ 1 I r~ i 7.~ E~ E
, r ~ f, E ~ f ~ - F ~ - f
?
~47--
00 72 B4 D7 I)6 E8 El E0 Dl D0 D4 70 7F 00 2f~ 7h 00
10 0f~2h 2E 86 ~7 97 0h 96 0~ 26 14 96 04 27 22 7F
20 00 04 9~ 0~; 97 0~ 86 09 97 02 7F 00 81 20 12 7Q
30 00 02 27 09 96 0~: 97 81 76 00 08 20 04 86 FF'~7
40 ~1 9~i 01 27 61 96 03 27 32 2~ 41 43 27 15 7~ 0~
50 0B 6 62 86 08 97 0B 96 C6 49 76 00 09 24 56 7C
60 00 03 3B 7~ 00 0B 26 4D 7F 00 03 96 C6 2~ 2F 96
70 05 26 42 73 00 ~5 96 09 97 07 3B 96 C6 2E 36 86
_____ ___ ____________________________________ _____.
0el__03_ _ 0B 8 _01 _7 _3 81~ 0 97 09 3B 95 C6 2~ 0E
7~ 00 0B 26 20 86 FE 97 .03 86 08 97 0B 3B 86 8~-~
97 0B 7F 00 01 3B 96 C6 2Q F4 7f~ 00 0B 26 06 73
30~ 00__1 7F 00 03 3B 0C 96 05 27 15 36 07 7F 00 05
40 0D 39 36 7F 00 80 96 04 26 FC 32 97 06 73 00 04
54 39 96 25 27 15 2fl lD 43' 27 08 8D 37 25 20 7C 00
39 8D 2F 25 14 7F 00 25 39 8D 13 24 ' i0 97 31
7C 0 Zl 25 39 8D lD 24 EE 8D 33 g6 FE 97 25 39 4F
00 CE 04 E0- E6 04- 2~ 0~3 4C - 08 81 14 26 F6-' 0C- 39 97 ' ~
31 0D 39- I~:E~-04 E0 DF'-56- ' 96' 31 9B 57 97 57 ~C 00-- -'
~0 S9 56 97 5~i DE_56 P~6 00 0C 2B D3 0D 39 CE 73 F5
30 DF 56 96 31 9~ 57 97 57-' 8~i~ 00 99 56 97 56 DE 56
40 ~6 0l3 84-0F`-~1-=0~-'27--- 16 .-~1 0B 27 17'D6' 44--~l7 45-.-.;----'-' ` -
50 D6 43 I:7 44 D6 42 -D;i 43 97 42 7C 00 30 39 86 ' FF
97 2E 39 CE 00 03 6F 42 09 8C FF FF 26 F8 7F 00-
30 7F 00 2E 39 ~h 07 04 01 0F 0F 0F 0F 0B ~g 06
, .
a0 03 0~ 08 45 ~Z 86 FF`97- 80 97 B0 7F ~0 B0--`~ 7~
51 7~ 00 4F 26 Z9 BD 75` 60 ED 76 7F B~ 76 ~D BD
7g B6 BD 75 FF BD 78 87 8D 16 ED 74 ~8 8D 31 BD
74 h4 BD` 75 20`BD 75 92``BD 77-56 86 lE 97 4F
1~ 96 80 84 04 27 19 96 20 `27 ~E 2~ 13 43 27 1~:96
E7 2B 0C 86 FF 97 20 39 96 E7 2h 03 7C ~0 20 39
~6 29 27 i6 2~ 20 43 27 09 96 E6 ZB 20 86 FF 97
~0 ~9 39 96 E6 2B 23 7F ~0 _2_ 3 _ 4 97 2~ ~6 E6 2h
00 0_ 8_ 01 97 29 39 _6 E6 2B 04 7F_00 29 _9 86 0i;
37 2~ CE 00 33 DF 54 CE 7Z 6B DF SZ-BD 73 E3 86
FE 97 Z9 39 ~6 82 C4 01 27 12 96 00 27 0F 2h 1~
43 27_1`7-B6_6~ 07 2~ ----`~-FF-~7 00 39 5F D7 28
4~ ~6 68 ~7 2~ ~ C6 ~ 7 ~ 39 ~ ~g 0~ 2~ 0~ 5F
D7 00 39 C6 FE D7 00 39 CE 40 00 C6 07 F7 40 lQ
FF 413 18 7h 40 1~ 2E_33 h6 00 27 16 2h_lF_43- Z7
0:CI EE 01 f~6 ~2~3 ZE 16 FE 40 12 ~:56 FF h~ 00 0~ 56
00 20 10 EE 01 ~6 0el Z~ F6 FE 40 18 6C Q4~ 0C 5li 20
10__01 54_FE_40_1~_08_08 _2_- 7E 74_E0_54____40_15_39
Z~ 91~ 8~3 8~ ~0 27 33 96 21 27 11 2P~ ~3 ~3 27 3~ 6
C2 2B 2C 86 FF 97 21 7F l~0 24 39 96 C2 2~ lE 96
_0 82 84 10 27 07 96 Z4 Z6 03 8D 0F 39 DE i~ 26 0F
CE 00 18 96 60 4C 48 7E 77 36 CE 00 00 DF i8 39
96 80 84 20 27 20 9G 26 27 1;5 2~ 43 27 08 96
Cl Zh 13 7C 00 26 39 9~; _Cl 2~q 10 7F 1~~ 26_39 96
f '
6~3
-48- .
00 _Ci 2E 03 7C 00 26 39 96_ C~ 2B F0 86 FE 97 26-7E
1~ 76 E4 96 82 84 10 27 11 96 2D 27 0E 2~ 0B 43 27
0g D6 CZ ZE 04 86 FF 97 ZD 39 96 C2 2~ FB 9Z 24
26 F7 7C 00 2D 39 CE 00 EC 8D 30 97 61 CE 00 E0:
40 8D 29 97 60 CE-08 E4 $D 2c 97 SE CE 00 E8 8D lB
CE 00 F4 8D 17 97 5F CE 0~ F0 8D 0F CE 00 FC 8D
0E 97 63 CE 00 F$ 8D 03 97 62 3~ 4F E6 03 59_49
E6 Q2 59 49 E6 0i 59 49 E6 00 59 4~ 88 0F 39,CE
0~ 0Q 00 6D 0C 27 23 6C 0D c6 lF 6C 0C 26 lB DF 56
D6 57 CE 76 31 DF 4E DB 4F D7 4F C6 00 D9 4E D7
Z0 4E DE 4E EE 00 ~D 00 DE 5~ ~g 48 8C 00 14 26 D2
39 76 45 76 72 76 B7 76 8C 76 ~5 76 C3 76 EC 76
D9 76 D4 76 DE 86 FF 97 24 96 22 81 01 27 10 $1
FE 27 0C 96 6i 26 0F 96 E6 2~ 17 86 FF 97 2B 7F
6Q 00 86 7F ~0 87 39 7F 0~ 86 7F 00 87 CE 0~ 0E 7E
77 36 96 22 $1 01 27 5B 81 FE 27 57 7E 76 F~ 96
00 2~ Z7 50:96 E6 2B 4C 7F- 00-2B 20 E~ 96 ~1 26 0C
'0 96 E6 Z~ 11 86 FF 97 2C 7F` Q0 85-39-;7F`-`0_ ~5--CE`~
00 14 7E 77 36 86 FF 97 $5 7F 00 2C 39 ~..2C 27
22 9~ E6 2B lE 20 EE 86 FF 97 $4 39 7C ~0 21 7C
00 2D 39 96`80=$4 40 27 .Q~ 86 FF~97 27 ~D 78 71
7F 0~ 2Z.~9 86_FF.97 $3-.39 86 FF--97-$2
64 B7 6g 08 ~9 CE FF FZ DF-- 0C CE 00 Q~DF.0E~ 10~
~Q 96 8~ 84 20 27 03..7F 00 84 39 C-E-~0-00-DF--0c-DF
______________ ..
00 0E DF 1~ 86 FF 97 ~6 ~7 87 4F 97 24 96 60 4C 48
lQ CE 00 10 2Q 21 86 FF`B7 40 2~-96-g~.84~10 2~1 5.~
-20 CE 00 00 DF_12 DF-14.CE-- FF FE- ~F-12-9~-~7.-c7~25
30___E_F_ EC_DF_i2 39 6F 00f 6F 01-4D 27 i8-~F~.5~--CF--
~40 FF _C DF 5G DE 5~-~6--01 D~-SD:E~=~l-E6-Q0._D9.`5
5Q E7 00 4~ 26 Fi 39 7~ 40: ?~ 2~ 46 $6-14 B7 40 ~
B6 40 26_26 3C B6 40 29 ~B 01 19 B7 40 ,9 ~-l 60
f0 26 2F g6 02 B7 f40 29 B6 44 23 ~E 01 i9 ~7 40 28
0~ 16 C4 0F Cl 05 26 03 F7 40--21--81-60 26 13-7F 4
28 E6 40 Z7 $B 0i i9 E7 40 27. 81 24 c6 ~3 JF 40
2~ Z7 39 F6 40 25 26 3~ 44 44 44 44 48 CE 77-Cl DF
50 9E 51 97 5i ~6 ~0-99 50 97 50 DE 50 EE -00 ~E
00 7g E~ 7g-~6 7`g-9~.7g- D9 7~ 96 77 15 76 E4 78
96 7g 2E 7g 42 78 SD 7~ 69 7g 78 7~ 9G-78 BS 7~
C6 F6 40 ^cc 26 lB g4 0F 26 13 ~6 FF B7 40 27 ~7
40 2$ B7 40 26 B7 40 cl 4_ ~7 40 25 39 B7 40 22
00 39 C6 FF F7 40 26 FE 40 23 ~7 00 08 FF 40 23 7~
40 22 26 i9 CE 40 lE ~6 00 ~7 4~ 27 ~6 ~i B7 40
c0 2~ ~6 02 ~7 40 29 4F B7 -4~ 25 E7 40 26 39 B~ -78
E5 96 82 ~4 0C 27 19 C6 01 F7 40 16 ~6 FF B7 40
17 39 BD ~2 ES 96 ~ ~4 ~C Z7 05 86 FE B7 40 1~
- 50 3~ BD 78 E5 96 ~0 84 0~ 27 3C 7E 77 15 B~ 7g ES
96 ~0 ~4 08 27 30 7E 76 E4 8D 7~ 96 80 ~4 08 27
~0 25 86 FF g7 2^c-7E-76 F~ - gD 6B 96 80 ~4`08-27 16
--49--
00 86 01 97 22, E 76 E4 96 80 ~4 01 27 09 96 62 84
01 27 04 7F 00 23 39 86 FE 97 23 39 8D 47 96 82
84_02_2__21_36_01_B7 40 lD 4F B7 _8 0g 96 61 CE
30 00 lE 7E 77 3l~i ~D 2E 96 82 84 02 27 08 4F E~7 68
4008 ~.C B7 *0 lD 39 8D lD 96 82 ;34 0c 27 F7 86 55
50_~7_40_1D 86 FF 1~7 68 08 39 ;~6 FF E_ 40 25 CE 40
lE FF 40 23 39 86 ï0 7E 7~ 2F 01 96 20 c7 3E 2B
08 73 00 20 86 8~l 7E 7~ 0~ 43 26 2E 7F 00 20 2~
00 8l~ 7E i~ 0D l~E 18 'c6 4 i 96 2D 27 3D 2B 0C 73 0~l
2D 86 80 BD 73 42 4F 7E 73 42 43 26 2C 7F 00 2D
2~ 86 80 BD 73 42 86 40 7E 73 42 96 'c'l 27 D6 c~ 0B
73 00 21 73 00 2D 86 2l~ 7E 7f~ 0D 43 2l~ C6 7F 00
2D 7F 00 21 ~6 1'2l 7E 7~ 0D B6 40 16 81 ~1 26 0D
7F 42l 16 86 $4~ 1:D '3 42 86 $1 7E 73 42 81 FE 26
0D 7C 40 16 86 84 BD 73 42 $6 82 7E 73 42 96 82
84 0C 27 69 B6 40 l~i 26 li4 CE 40 00 C6 04 96 82
______~_ ____________________ _____________________.
00 ~:4 08 2;7 02_C6 07_F7 40 lB_5F 7~ 40 1 ~3 2B 2C 5C
i~i 00 27 22 2B 0E ~;3 00 ` 4F l~t 36 86 $0 BD 73 42
32 7E 73 42 43 26 0F 6F 00 86 41Z lB 36 86 g0 ~D
73 42 32 7E 73 42 08 08 08 20 CF B6 40 17 27 lD
7F 40 17 86 80 13D 73 42 ~;6 20 BD 73 42 E6 40 lC
5~1 84 7F D6 82 C4 08 26 57 84 0F 7E 73 42 96 22 27
~0 13 ZB 07 73 00 22 g6` 40 20 23 43 ~ 37 7F ~0 ~2
,0 86 30 ~0 19 B~i 40 lD 81 01 26 07 86 FE B7 40 lD
00 20 11 81 55 26 2C 86 FE B7 40 lD 20 0F 36 8D 19
10 32 20 lC 86 ~0 1~1 73 ~2 ~;6 40 20 13 81; ~0 ~1: 73
20 4c 86 44 20 0f~ 86 FF 2 zl 06 96 81 48 48 48 48 7E
30 73 42 96 28 2~ 51 96 SE 84 04 c7 21 96 5E 84 03
40 D6 3f:~ C4 03_11 Z6 11 96 5F 16 84 0F 91 3~ ;~6 2l8
50 54 S4 54 54 Dl 38 27 05 CE 00 00 I~F 38 96 80 ~4
60 02 26 66 96 80 84 01 Zli 71 8D BE 4F CE 00 00 P~
33 3D_EC 08 h6 33 48 48 48 4;3 08 8C 0Q08 26 EF
7F 0~ 28 39 7E 7h 25 BD 71 h4 24 Zh ~i 03 137 40
1~ 2D 86 70 BD 73 42 17 BD 73 4Z B~l 71 ~4 17 BD 73
42 7h 40 2D 2h F4 7F 40 3C FE 40 32 FF 40 30 FE
3h FF 40 38 39 B6_40 21 27_C!3 86 3~ El: Y3 42
86 01 BD 73 4Z 7F 40 ~1 39 96 2E 27 B7 8D 9h 96
43 48 48 48 48 9h 42 7E 73 42 96 23 21i 813 96 30
81 04 26 h0 86 50 BI) 73 42 8D 12 133 7B 44 Z5 07
70 8D Z0 6 F0 7E 7h 6C 8D 38 4F 7E 7h 6C CE 00 0~;
00 h6 33 hl 3B 27 03 7F 00 2F h7 3B 0g ~C 00 01 2G
EF 39 96 81 84 40 27 18 7C 00 ZF ~6 62 44 84 07
4~ !31 2F 21~ 0~3 7F 00_$2 _7F_00_2F CE FF C4 DF 1~
39 g6 ~1 84 2~ 27 0C 96 2E 27 08 7F 00 33 CE FF
C4 DF iC 39 8I) 20 7F ~0 58 CE 0~ 00 ~6 46 DF 50
97 59 DE 58 h6 33 D~ 50 ~1 42_26 ~$ ~8 8C 00 04
2~ Eh 0D 39 ~C 39 96 63 44 44 44 44 44 97 32 4F
Cl~ el4 CE '30 4h 91 32 c6 01 4C ~7 el0 0~ 4C 5h 26
--5 O-
0el ~F4 :7F 00 5$ 96 ~3 44 44 ..-44 84 03 97 59 DE 58 ~6
10 4~q 97 49 43 h7_4~_96 63 44 $4 03 97 59 DE 58 P~6
2 Zl 4f~ 2~q 01 43 97 48 43 fV 4~ CE 00 49 08 f~6 00 2B
30 FB 97 47 08 ~6 00 2B FB 97 46 36 63 84 01 27 08
40 96 47 D6 46 97 46 D7 47 39 00 00 00 00 00 00 00
50 ~0 0~ 00 ~0 00 ~0 el~ 00 00 00 00 1~0 ~0 ~1~ 0~ e,0
60 00 00 ~ 0~ 00 ~ 00 00 00 00 0~ ~0 00 00 00 00
70 1~0 00 00 0 21 00 el0 00 e~0 00 el0 01~) 00 00 00 00 i.00
_________________________________.___________________
00 130 el0 0el ~0 00 `~0 ~0 00 Q~ 0el Q0 el~ 00
10 0~ 0 00 el0 ~el 0t~ 00 00 00 00 00 00 00 00 00,0
20 ~0 e,0 00 00 00 00 0Z1 ~0 . ~)0 00 00 00 0~ ~0 00`~0
0__0____ _~_0~____~a_~0__0 __~ 0 00__~_00-~
41a 00 ~0 00 00 00 00 00 ~0~1~ 00 00 ~? 00 ~30 00 00
5~ 00 0~ 0~ 00 Q~ 01~ 00 0000 00 ~ 0el1~t0 0el 00
~i~3 00 0e~ 0~ 00 0~? 0~) 0~ 00l~8 00 013 _0 ~
7~ ~0 0~ 00 130 ~0 0000 00 012l 0~ 0 1~0 ~0
0el el0 ~ 0~1 0la 00 ~30 00 00el0 ~ 0 ~4 0el~0 00 00
~ 00 0ZI el~ 00 00 ~0 0~ 0~- ~ 00` 00`-00 00 00 ~10 1~0 0~
20 00 00 0~3 00 00 00 00 00 00 00 00 ~0 l210 la0 ~30 00
130 00 00 012, 00 00 ~1~ 00 ~10 0~1 0~ 00 0~ 00 e~0 0~
4~ 00 00 0el 0~1 0~ 00 00 1~0` ~00 00 - 0~ 00 00 `~ 00
e~0 00 00 01a 00 00 ~ 0e~ 0 00 00 ~a~ 0 00 ~0
l~i0 ~0 130 0~ 00 ~0 el0 0ei 00 0~1 0~ 00 0~ 00 00 el0 00
70 00 '~1 0~ 00 00 00 013 el0 00 00 00 ~0 00 ~0 00-` 0~
_________.___________________________________,______
00 ~_00 00 00 00 00 0~ 0~ ~0 ~ 0~ ~ 0~ ~ 0~. 00
10 00 00 Q~3 00 ` 00 0~1 00 ~0 ~0 ~a 0e~ 0~ 00 0~` 0e~ e"3
0elZ10 0~1 00- ~ 00 01a 120 0e~ 00 e!l~ 00 el0 1~0 1~0 ~
~0 h~?00 00 00 00 00 00- 00= 00 00 00 00_00 _` _~__0
w0 ~0 00 00 00 0el- 00 el~ 00 00 .1~0 00 el0 0~,,,1~0 ~!~
~ 00 00 ~0 00 00 ~ a 00 ~ 0~ 00 ~0--00 0~
~0 00 ~4 00 00 00 ~0 00~0 ~et 04 00 00 ~0 0~1 00
04 4~ 0g 00 00 ~30 0~ 130 00 04 00 0~ 0e~ ~0 0el e10
~0e~~0~~~0~0~~00~0~--00--00-~0-00-00--00-e-0-00--00
30 ~0 e~ 4 00 00 330 00 06 00 00 0~ 00 ~0 1~0 00
21~ 00 ~ 00 00 00 0~ 00 00 ~0 00 00 4~ 00 00 00 00
30 00 ~0 00 00 00 0~ 0~ 0~ 0!3 el0 00 00 0~ 00 00
4~ 0~ 0~-0a ~0-00- ~0 0~- 00 00 00 00 0~ 00 00
50_ _4_~,0____0______0_4~ __00_00--~-~--a~--0-0-~
6~ 00 0g 00 ~0 00 ~ 00 ~ 00 04 ~ 0i~1 00 00 0~ ~0
70 00 00 e~ 00 ~0 00 00 0~ 00 00 00 00 00 0~ e~0 ~0
0~ 0~ 00 0~1 ~0 ~30 ~ ~0 ~ Q 00 0~ 0i~ 00 0~
0!~ ~0 el0 00 0~ 00 ~ 0000 ~_ 0~ 0i3 00 00 00 00
0~ ~0 00 ~e, 00 0~ 00 0g ~ 00 ~ 00 0~ 00 00 012
00 00 00 00 ~ 0~ 0000 ~0 ~0 0~ ~0 00 0t~ 00
4~ 0 1a0 0~ 00 ~ 00 ~0~0 00 ~e~ 0~ 00 00 ~ 00
5~ ~ 00 0~ 00 00 01~ 00 0001a 00 00 00 40 ~.0 00 00
~;0 ~ 0 1~13 00 00 130 013 i~000 0~ 00 00 00 00 ~0 ~0
1~0 ~ 00 ~0 ~0 ~30 00 130Q0 00 ~0 ~ 00 i~0 ~10 00
____________________________________________________.
71~
~0 00 0~-00 00 00 00 00 00 00 00 00 00 0~ 00 00 00
10 ~10 00 0000 00 00 00 00 0000 00 00 00 00 ~10 ~10
20 00 00 0001~t ~10 00 0000 0000 00 ~0 00 ~0 ~0 0~
30 0el 00 0000 00 00 00 ~0 0000 00 00 00 ~0 00 0Q
~0 00 0~ ~000 00 00 ~0 00 0000 ~0 00 ~0 00 ~0 00
50 Ij~ 00 0000 00 00 00 0~ 0400 01~ ~0 e~0 00 00 00
~;00h 00 0000 00 00 00 00 0000 00 00 00 00 00 00
0 e~0 0000 ~ 10 00 0000 0000 00 0~ ~0 ~0 ~0
~0 00 ' 00' '~0 ~0 0~ 00 00 00 00 00 00 0~ 00 0~ 0~ 00
10 00 00 00 01~ 00 00 0a_00 00 00 00 00 00 00 00 00
00 00 00 00 00 ~30 ~.0 0~ 00 ~el 0~ 00 00 00 0~ 00
el0el0 00 e~l3 00 00 0~ ~0 ~0 0~ 00 00 00 00 ~0 00
4~ 00 00 00 00 00 00 ~0 ~0 00 0~ 0e~ 00 00 ~0 ~ 0
~0 00 01~ 00 013 00 00 ~~0 00 ~e~ 00 0~i ~0 1~0 ~0 00
~ 0 01~ 00 00 00 01~ 00 ~t0 ~0 00 00 00 ~0 00 1~0
00 00 00 00 00 00 00 00 0~ 00 ~13 00 ~0 ~0 ~
~0 00 00 00 0~1 ~0 0~ 00 0~ 00 0~ 0 00 03 0Q 00
0~a00 0~ 0~ 00 ~0_00 00 0~ ~0 00 00 00 ~0 0
2~ 00 00 00 00 00` l~e~ 00 00 00 0Z1 0t~1 01Z~ 00 ~ ~0 0~
:~:0 00 ~0 013 00 00 00 0e~ 00 0~ 00 ~ 0 0~ ~0 ~ 0
00 00 01~ 00 0~ 0~ 00 ~0 0el 00 00 00 00 ~ 0 00
0el00 00 00 00 ~0 ~10 ~0 el0 00 0~ 00 ~ 0~ ~0
~i0 00 00 00 00 0~ 00 ~(3 00 ~0 Q0 00 ~ 0 ei~ 2!0 ~0
00 00 00 00 00 00 00 00 74 05 70 00 ~2 ~B 70 00
. . .
``
r~
-52-
Appendix C
(c) Copyright 19~2 Rusco Electronic Systems -- a
divislon of Figge International, Inc.--all rights reserved,
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08 ~3C ~1~ 64 26 F8CE 6~} ~ '. F ~-~ q0 ~$ 8C t~
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~10 1~1000 00 00 00 00 00 00 00 IZ10 0e~ 00 00 0~1 01ZI 0Ç~~20 00 00 ~ 00 00 ~0 00 00 00 00 0~ 00 00 00 00
'~0~00-0~~0~-0~~00-~-0~-00-~-0~-0~-0~-00--0-0-a0-00
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0 ~ 00 0~ ~ 00 00 00 00 ' 00 00 ~0 00 0~ 00 0~ ~0
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~0 ~00~ 0~ ~ 0~ 0 ~000000~ 0~ 0
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QB0 00 00 00 00 00 00 00 00 0 00 00 00 00 00 00
RC0 00 00 00 00 00 00 00 00 00 00 00 0~ 00 00 00 00
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hF0 00 00 00 00-00:00-00 00--00 ~0-00-00-00-00--~0 00
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E10 0__00 00_00_0 Q0__0 Q00_00__0__0_00____00____00
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0 ~ 0 ~ 0 0 ~ 0 ~1 ~ 0 el 0 0 ~ 0 0 1~ 0 e~ 0 0
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B~0_00 00 00 00 0~ 0QJ - 00_00 00 ~0 00_00 00 00 00 00
0 0 ~ 0 1Zt 1~ ~ 0 @! 0 e~ ~5 1 0 - 0 0 0 ~ ~ 0_ .0 0 - ~ &~ 0 0_ 0 0
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c0~ 0~` 00 ~ e ~ Q 01~-0~
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ccei 1~0 0~ 00 00 00 ~0 0~ ~ 00 00 ~0 0~ 00 00 00 00
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r~40 00 00 e~0 00 00 00 00 00 00 00 00 e~0 00 00 ~0 0
D50 00 00 00 00 00 00 00 00 00 00 00 00 0~ 00 00 00
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FF0 00 00 00 ~0 00 00 00 00 73 19 7~ 00 71 9F ?0 00
