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Sommaire du brevet 1209721 

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Disponibilité de l'Abrégé et des Revendications

L'apparition de différences dans le texte et l'image des Revendications et de l'Abrégé dépend du moment auquel le document est publié. Les textes des Revendications et de l'Abrégé sont affichés :

  • lorsque la demande peut être examinée par le public;
  • lorsque le brevet est émis (délivrance).
(12) Brevet: (11) CA 1209721
(21) Numéro de la demande: 1209721
(54) Titre français: DISPOSITIF SEMICONDUCTEUR SOUS CAPSULE PLASTIQUE ET SON PORTE-CONDUCTEURS
(54) Titre anglais: PLASTIC ENCAPSULATED SEMICONDUCTOR DEVICE AND LEAD FRAME THEREFOR
Statut: Durée expirée - après l'octroi
Données bibliographiques
(51) Classification internationale des brevets (CIB):
  • H01L 23/48 (2006.01)
(72) Inventeurs :
  • TATENO, KENICHI (Japon)
  • YOKOZAWA, MASAMI (Japon)
  • FUJII, HIROYUKI (Japon)
  • NISHIKAWA, MIKIO (Japon)
  • KATOH, MICHIO (Japon)
  • WADA, FUJIO (Japon)
(73) Titulaires :
  • MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
(71) Demandeurs :
  • MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. (Japon)
(74) Agent: GOWLING WLG (CANADA) LLP
(74) Co-agent:
(45) Délivré: 1986-08-12
(22) Date de dépôt: 1982-04-27
Licence disponible: S.O.
Cédé au domaine public: S.O.
(25) Langue des documents déposés: Anglais

Traité de coopération en matière de brevets (PCT): Non

(30) Données de priorité de la demande:
Numéro de la demande Pays / territoire Date
64307/1981 (Japon) 1981-04-30
64893/1981 (Japon) 1981-04-28

Abrégés

Abrégé anglais


ABSTRACT OF THE DISCLOSURE
A lead frame having a substrate support which
supports a semoconductor substrate connected to a top
of one of a plurality of external leads extending in the
same direction from a connecting band, wherein a three-
dimensional pattern of a groove shape or a bore shape
is formed on at least part of one surface of the
substrate support the other surface of which supports
the semiconductor substrate.

Revendications

Note : Les revendications sont présentées dans la langue officielle dans laquelle elles ont été soumises.


The embodiments of the invention in which an
exclusive property or privilege is claimed are defined
as follows:
1. A lead frame having a substrate support
which supports a semiconductor substrate connected to a
top of one of a plurality of external leads extending
in the same direction from a connecting band, wherein a
three-dimensional pattern of a groove shape or a bore
shape is formed on at least part of one surface of said
substrate support the other surface of which supports
said semiconductor substrate.
2. A lead frame according to claim 1,
wherein said three-dimensional pattern has grooves
extending perpendicular to a longitudinal direction of
said substrate support.
3. A lead frame according to claim 1,
wherein said three dimensional pattern has grooves in a
lattice form.
4. A lead frame according to claim 1,
wherein said three-dimensional pattern has grooves
extending parallel to a longitudinal direction of said
substrate support.
5. A lead frame according to claim 1,
wherein said three-dimensional pattern has a number of
bores.
-16-

Description

Note : Les descriptions sont présentées dans la langue officielle dans laquelle elles ont été soumises.


~Z~37;~
TITLE OF THE_INVENTION:
A METHOD FOR MANUFACTURING A PLASTIC
ENCAPSULATED SEMICONDUCTOR DEVICE AND A
LEAD FRAME THEREFOR
BACKGROUND OF THE INVENTI_N:
I. Field of the In~ention
The present invention relates to a method for
manufacturing a plastic encapsulated semiconductor
device which can be used with relatively large power
and a lead frame therefor.
II. Description of the Prior Art
Plastic encapsulated semiconductor devices
are superior to metal encapsulated semiconductor
devices in ease in mass production and manufacturing
costs. However, the plastic encapsulated semiconductor
devices are inferior to the metal encapsulated
semiconductor devices in radiation of heat when they
are operated. Plastic encapsulation of semiconductor
devices has recently been developed. A high power
transistor manufactured by plastic encapsulation has
been proposed. In this case, sufficient consideration
is taken to allow the radiation of heat.
In a transistor adhered on a metal substrate
support and encapsulated by plastic, for example, the
lower surface of the substrate support is not covered
with plastic but exposed. The substrate support is
mounted on a radiator to radiate heat~ However, in

2~
this case, the substrate support must be electrically
insulated from the radiator~ The packaging operation
of the semiconductor device on the radiator through an
- insulating plate is complicated and cumbersome.
On the other hand, a plastic encapsulated
power transistor is proposed wherein a thin plastic
layer is formed on the lower surface of the substrate
support during plastic encapsulation and an insulating
plate is not required for mounting the power transistor
on the radiator. However, in this case, at the time of
plastic encapsulation, only the side of the lead frame
from which extend the external lead is clamped by the
upper and lower molds with a transistor assembly which
has the external lead on one side. Plastic is injected
while the substrate support is floating in a cavity
defined by the molds. Thus, the substrate support may
be bent in the cavity due to the injection pressure of
the plastic. As a re~ult, it is very difficult to
encapsulate in plastic while keeping the substrate
support in a proper position, thus, resulting in
non-uniformity in the thic~ness o~ the plastic layer on
the lower surface of the substrate support and
degrading radiation characteristics.
SUMMARY OF THE $NVENTION:
_
It is an object of the present invention to
provide a method for manufacturing a plastic
encapsulated semiconductor device and a lead frame
therefor wherein, in manufacturing a plastic

72~
encapsulated semiconductor device of a structure which
has a thin plastic layer on one surface of a substrate
support which supports a semiconductor substrate and
also serves as a heat sink, to the other surface of
which the semiconductor substrate is adhered, the
thickness of the thin plastic layer is uniformly formed
and with high precision.
In order to achieve the above object of the
present invention, there is provided a lead frame comprisinq
a first connecting band, a plurality of external leads
ex~ending in one direction from ~aid first connecting
band, a substrate support which further serves as a
heat sink connected to a top of one of said external
leads, strips which have portions of ~mall
cross-sactional areas and of a predetermined length,
the cross sections being perpendicular to an extending
direction of said strips, and one ends of which are
connected to one side of said substrate support
opposite to the other side connected to said external
leads, and a second connecting band extending parallel
to said first connecting band with said substrate
support disposed therebetween, wherein said strips have
a smaller thickness than said substrate support so that
said strips are thinner than said substrate support and
rear surfaces of said strips are at a higher level than
a rear surface of said substrate support.

~lZ~7~
In the foregoing lead frame, the number of strips
the ends of which are connected to one end of the substrate
support the other of end of which is connected to the
external lead may be two.
The above and other objects and features of
th~ present invention will become apparent from the
following detailed description of the preferred
embodiments when taken in conjunction with reference to
the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS:
Figs. 1 and 2 are sectional views showing the
structures of conventional plastic encapsulated power
transistors, respectively;
Fig. 3 is a plan view of a conventional lead
frame;
Fig. 4 is a view illustrating the state of
plastic encapsulation for forming the plastic
- encapsulated power transistor of Fig~ 2 using the lead
frame of Fig. 3;

7;~
Figs. 5A and 5B are a plan view and a
sectional view, respectively, of a lead frame according
to one embodiment of the present invention;
Figs. 6, 7 and 8 are views illustrating the
plastic encapsulation process to the completion of
manufacture according to a method for manufacturing the
plastic encapsulated semiconductor device of the
presen~ invention;
Figs. 9 and 10 are views showing examples of
portions of the strips with small cross-sectional
areas, respectively;
Figs. llA and llB are a plan view and a
sectional view, respectively, of the main part of a
lead frame according to another embodiment of the
present invention; and
Figs. 12, 13 and 14 are plan views of the
main part of a lead frame according to still another
embodiment of the present invention, respectively.
DETAILED DESCRIPTION OF THE PRIOR ART:
,
Fig. 1 i5 a sectional view of a conventional
power transistor of the plastic encapsulated structure.
The lower surface of a substrate support 2 on which a
transistor element 1 is adhered and which serves as a
heat sink is not covered with a plastic encapsulating
ZS housing 3 but exposed. A through hole 4 is formed for
mounting the power transistor on the radiator with a
screw. Reference numeral 5 denotes a protective
plastic portion and reference numeral 6 denotes an

external lead. When the plastic encapsulated power
transistor with the above structure is to be mounted on
the radiator (not shown), the exposed lower surface of
the substrate support 2 must be thermally coupled with
the radiator but must be electrically insulated
therefrom. This electrical insulation may be performed
by insertion of an insulating plate such as a mica
plate.
With the above structure, the heat radiation
effect is guaranteed. ~owever, the insulating plate -~
must be inserted between the radiator and the substrate
support when the substrate support is to be mounted on
the radiator, resulting in a complicated packaging
operation. Furthermore, the insulating plate must be
properly inserted between the radiator and the
substrate support. When the insulating plate, the
radiator and the substrate support are to be integrally
adhered, they may be misaligned. Thus, electrical
insulation cannot be guaranteed. Therefore, as shown
in Fig. 2, a plastic encapsulated power transistor is
proposed wherein a thin plastic layer 7 is formed on
the lower surface of the substrate support 2 and the
insulating plate is not required.
Fig. 3 is a plan view of a lead frame which
is conventionally used for packaging the plastic
encapsulated power transistor of Figs. 1 and 2.
External leads 6/ 10 and 11 of the power transistor
extend in one direction from a connecting band 9 on
-- 6 --

7%~L
which apertures 8 for determining the feed pitch dnd
positioning the substrate support 2 at the time of
plastic encapsulation are formed. As shown in Fig. 4,
the substrate support 2 is connected to the end of the
external lead 6. As shown in the leftmost transistor,
the transistor is packaged in such a manner that the
transistor element 1 is adhered, metal wires 12 are
connected between the external leads 10 and 11 and
electrodes of the transistor element 1 corresponding
thereto, and a protective plastic portion 5 is formed.
A transistor assembly is obtained, using the
lead frame as described above. This transistor
assembly is formed into a plastic encapsulated
structure shown in Fig. 2 in the following manner. As
shown in Fig. 4, the substrate support 2 of the `
transistor assembly i5 floated in a cavity formed
~ between an upper mold 13 and a lower mold 14. Plastic
30 is then injected into the cavity. The plastic 30 is
also filled in the cavity immediately under the lower
surface of the substrate support 2. Thus, the plastic ;~
encapsulated semiconductor device of Fig. 2 is
manufactured.
As is apparent from Fig. 4, when the plastic
encapsulated structure of Fig~ 2 is to be obtained by
using the lead frame of Fig. 3, plastic is injected
lnto the cavity while only the side on which the
external leads are formed is clamped between the upper
and lower molds. The substrate support 2 may be bent

~2~
within the c~vity due to the injection pressure of the
plastic. Therefore, it is very difficult to dispose
the substrate suppo~t 2 in a proper position. If the
substrate support 2 is bent, the uniform thickness of
the thin plastic layer 7 is not obtained. Further,
this non-uniformity in thickness directly results in
degradation of radiation characteristics.
DESCRIPTION OF THE PREFERRED EMBODIMENTS:
Figs. 5A and 5B are views illustrating the
structure of a lead frame according to the present
invention in which Fig. 5A is a plan view thereof and
Fig. 5B is a sectional view thereof along -the line U -
U.
Two strips 15 and 16 extend from a side of
the substrate support 2 which is opposite to the side
to which the external lead 6 is connected. The strips
15 and 16 are connected to a second connecting band 17.
Portions 18 and 19 of small cross-sectional areas are
formed at the strips 15 and 16, respectiv~ly.
Apertures 20 formed in the second connecting band 17
fit with parts of a mold for alignment in the plastic
encapsulatlon process. As shown in Fig. 5B, the
thickness of the strips 15 and 16 is smaller than that
of the substrate support 2. A predetermined step is
formed between khe rear surfaces of the strips 15 and
16 and the rear surface of the substrate support 2.
Thus, the portions 18 and 19 are thinner than any other
portions.

Zl
Fig. 6 is a view illustrating the state of
plastic encapsulation of the transistor assembly formed
by using the lead frame according to the present
invention. The plastic 30 is injected into the cavity
formed between the upper and lower molds 13 and 14 in
the same manner as in the conventional plastic
encapsulation. However, when the lead frame according
to the present invention is used, as shown in the
figure, the external lead 6 of the lead frame is
clamped by the upper and lower molds 13 and 14 on one
side. At the same time, the strips 15 and 16 and the
second connecting band 17 are clamped by the upper and
lower molds 13 and 14 on the other side. Projections `Z
(not shown) of the upper mold 13 fit in the apertures 8 `~
formed in the first connecting band 9. Simultaneously,
projections 21 of the upper mold 13 fit in the
apertures 20 of the second connecting band 17. `~;
Reference numeral 22 denotes a projection of the upper
mold 13 which forms a through hole for mounting the
semiconductor device to a radiator with a screw.
According to the present invention, the
substrate support 2 of the lead frame is supported by
the external lead 6 and the strips 15 and 16 which are
clamped by the upper and lower molds 13 and 14, and
thus floats in the cavity of the molds. The first and
second connecting bands 9 and 17 are clamped by the
upper and lower molds 13 and 14, as described above.
Further, since the projections of the upper mold 13 are
_ g _

~g72~ ~
fitted in the apertures formed in the first and second ~,
connecting bands 9 and 17, th~ first and second bands 9
and 17 are not allowed to move horizontally. Thus, the
floating condition of the substrate support 2 is ~.
properly controlled.
As is apparent from Fig. 6, the cavity formed .~.
by the upper and lower molds 13 and 14 terminates at a
small cross-sectional area portion 18 (19) of the strip
15 (16). Therefore, the small cross-sectional area
portion 18 ~19) of the strips 15 (16) extends from the
encapsulating housing to the outside a~ter plastic
encapsulation is completed. In accordance with the .
shape o~ the extending portion of the strips, effects
to be described later will be obtained in the cutting
operation.
Fig. 7 is a perspective view illustrating the ~¦
condition after the plastic encapsulation is completed. :~
As shown in the figure, the plastic encapsulating :~
housing ha~ a thin portion 23 with the through hole 4
for a screw is disposed and a thick portion 24. A step
is formed between the thin portion 23 and the thick
portion 24, the head of the screw mounted in the
through hole 4 does not extend higher than the top of
the thick portion 24.
The external leads 6, 10 and 11 are cut from
the first connect:ing band 9 along the line X - X and
the strips 15 and 16 are cut at the portions 18 and 19
of small cross sectional areas along the line Y - Y so
-- 1 0
'
.,

~2~7Z~
as to produce a plastic encapsulated transistor shown
in Fig. 8. Since the portlons 18 and 19 extending from
the thin portion 23 of the plastic encapsulating
housing have cross-sectional areas smaller than those
of other poxtions, the strips 15 and 16 are easily cut
along the Iine Y - Y when bent in the vertical
direction indicated by an arrow Z - Z. Since the
portions 18 and 19 are partially exposed at the end
face of the thin portion 23 of the plastic
encapsulating housing, the thickness of the strips 15
and 16 is thinner at the end face of the plastic
encapsulating housing. Further, since a step is formed
between the portion 18 and the strip 15 and between the
portion 19 and the strip 16, the substrate support 2 is
brought into contact with the plastic material at a
relatively long length rom the end face of the plastic
encapsulating housing to the transistor element 1.
Therefore, water or the like may not enter through the
cut surface. The strips 15 and 16 may be cut by a
press machine or the like. However, in order to
substantially align the cut surface of the strip with
the end face of the plastic encapsulating housing with
high precision, it is preferable to bend and cut the
strips by brittle fracture under bending stress because
cutting by the press machine may damage the
encapsulating housing, resulting in poor appearance.
In the transistor manufactuxed according to
the method of the present invention, the cut surfaces
-- 11 --

7~
of the strips lS and 16 are exposed at the end face of
the plastic encapsulating housing. However~ since the
step is formed between the rear surface of the
substrate support 2 and the rear surface of the strips
15 and 16, as shown in Fig. 5, a sufficient space is
formed between the cut surfaces and the rear surface of
the plastic encapsulating housing which is mounted to
the radiator. Short-circuiting does not occur at the
cut surfaces of the strips.
In the above embodiment, parts of the strips
15 and 16 are made thin in order to reduce the
cross-sectional areas of the strips at these parts.
However, as shown in Fig. 9, the thickness of the
strips may be kept constant but parts thereof may be
narrowed for this purpose. Alternatively, as shown in ~f
Fig. 10, holes 25 and 26 may be formed in the strips 15
and 16, respectively, to substantially partially reduce ~'
the width of the strips 15 and 16. The plastic for -~
plastic capsulation used according to the method of the
present invention preferably has high thermal
conductivity. The thickness of the plastic layer
immediately under the substrate support is preferably
O.3 to 0.5 mm in consideration of heat radiation and
electrical insulation. With the thickness within this
range, better results are ob~ained.
In the plastic encapsulated semiconductor
device with an insulation structure formed by the
process described above, as is also apparent from

:~L2~9~723~
Fig. 6, a thin layer of plastic 30 is formed on the
rear-surface of the substrate support, to the upper
surface of which the transistor element 1 is adhered.
The layer of plastic 30 has thermal conductivity lower
than that of the substrate support 2 comprising a metal
plate. Therefore, the plastic layer on the rear
surface of the substrate support 2 must be as thin as
possible and must comprise a plastic of very high
thermal conductivity. In consideration of this,
although a very thin plastic layer is formed on the
rear surface of the substrate support 2, the plastic
film may peel off the substrate support 2 due to heat
shrinkage therebetween, thus resulting in changes of
heat dissipation characteristic over time, degradation
of resistance to humidity, degradation of mechanical
strength, and degradation of electrical insulation.
The present invention provides a plastic
encapsulated semiconductor device with an in~ulation
structure which eliminates the above problem. The
characteristic feature of the present invention resides
in that grooves or bores are formed in at least part of
a surface opposing the semiconductor substrate adhered
surface of the substrate support connected to one of
the external leads extending in the same direction from
the connecting band.
- The above feature will be described in detail
with reference to the accompanying drawings. Fig. llA
is a pIan view of the main part of a lead frame for a

7;~:~
plastic encapsulated semiconduc~or device according to
another embodiment of the present invention, and
Fi~. llB is a sectional view thereof along the line W -
W of Fig. llA. A plurality of groo~es 27 are formed
perpendicularly to the direction indicated by an arrow
T. The width, depth and pitch of these grooves are not
limited but may be changed as needed. When a thin
plastic layer is formed on a three-dimensional surface,
~he surface area of the substrate support which is .
brought into contact with the plastic layer is
increased. Therefore, heat dissipation characteristics
are, of course, improved and the plastic layer is
strongly adhered to the substrate suppor~ 2. Thus, the
plastic layer does no~ peel off the substrate support
2, although the layer tends to peel off the flat .
surface of the substrate support 2.
An increase in the surface area is
proportional to the total area of inner walls of the
grooves. Assume that the numher of grooves is defined
as n, the length of each groove is defined as,~, and
the depth of the grooves is defined as d. An `,
increase~ S of the surface area is given by the
relation: a s = 2n~d. For example, assume that fifteen
parallel grooves of 200~ m width and lO0~ m depth are
formed in a substrate support of 15 mm leng.th and 10 mm
width. The surface area is calculated as 150 ~ (2 x
15 x lO x 0.1) - 180 mm2, whereas the surface area of
- 14 -

7;~
the substrate ss~pport without grooves is calculated as
150 mm2. Thus, an increase a S of 20% is obtained.
Figs. 12, 13 and 14 show other examples of
three-dimensionally patterned surface of the substrate
support 2, respectively~ A plurality of grooves 27 are
formed in a lattice shape on the rear surface of the
substrate support 2 in Fig. 12; a plurality of grooves
27 parallel to the direction indicated by th~ arrow T
are formed thereon in Fig. 13; and a plurality of bores
which has predetermined diameter and depth are formed
thereon in Fig. 14. The same effects as described
above are obtained in all modifications of the grooves
27. Further, the plastic is injected in the molds in
the direction indicated by the arrow T. If the
three-dimensional patterning process as shown in
Fig. 13 is performed, the flow of the plastic in the
molds is very smooth, so voids or the like are easily
eliminated, resulting in good appearance and the
improvement of electrical insulation of the device.
As is apparent from the above description, a
plastic encapsulated semiconductor device which has a
thin plastic layer immediately under the substrate
support which also serves as the heat sink is
manufactured with high precision according to the
present invention.
- 15 -

Dessin représentatif

Désolé, le dessin représentatif concernant le document de brevet no 1209721 est introuvable.

États administratifs

2024-08-01 : Dans le cadre de la transition vers les Brevets de nouvelle génération (BNG), la base de données sur les brevets canadiens (BDBC) contient désormais un Historique d'événement plus détaillé, qui reproduit le Journal des événements de notre nouvelle solution interne.

Veuillez noter que les événements débutant par « Inactive : » se réfèrent à des événements qui ne sont plus utilisés dans notre nouvelle solution interne.

Pour une meilleure compréhension de l'état de la demande ou brevet qui figure sur cette page, la rubrique Mise en garde , et les descriptions de Brevet , Historique d'événement , Taxes périodiques et Historique des paiements devraient être consultées.

Historique d'événement

Description Date
Inactive : Périmé (brevet sous l'ancienne loi) date de péremption possible la plus tardive 2003-08-12
Lettre envoyée 2001-07-11
Accordé par délivrance 1986-08-12

Historique d'abandonnement

Il n'y a pas d'historique d'abandonnement

Historique des taxes

Type de taxes Anniversaire Échéance Date payée
Enregistrement d'un document 2001-06-08
Titulaires au dossier

Les titulaires actuels et antérieures au dossier sont affichés en ordre alphabétique.

Titulaires actuels au dossier
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Titulaires antérieures au dossier
FUJIO WADA
HIROYUKI FUJII
KENICHI TATENO
MASAMI YOKOZAWA
MICHIO KATOH
MIKIO NISHIKAWA
Les propriétaires antérieurs qui ne figurent pas dans la liste des « Propriétaires au dossier » apparaîtront dans d'autres documents au dossier.
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Description du
Document 
Date
(aaaa-mm-jj) 
Nombre de pages   Taille de l'image (Ko) 
Revendications 1993-07-06 1 26
Abrégé 1993-07-06 1 12
Page couverture 1993-07-06 1 19
Dessins 1993-07-06 5 88
Description 1993-07-06 15 497