Note : Les descriptions sont présentées dans la langue officielle dans laquelle elles ont été soumises.
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PHN 10.479 1 23-06-1983
Autanatically adjustable equalizing network.
The invention relates to an automatically adjust~b]e equalizing
network c~nprising a numker of regulating networks connected in ca~de,
the regulating ne~rks being controlled by the same control voltage
which is derived from a peak detector.
Automatic equalizing networks are used, for example, in pulse
code m~dulation translrossion systems. In such a transrnission system, the
transmission characteristic of the transmission path, which in many cases
is constituted by a cahle, is a -function of the distance between t~
successive c~nplifiers and of the ambient temperature. In order to obtain
lO as uniform and as sirnple as possible construction of amplifier, the
equalization required fo:r the pulse regeneration in the equalizing
aTr~lifier ls realized as a fixed section which equalizes the transmission
characteristic of a transmission path of nominal length at a nominal
temperature and an adjustahle section for automatically equalizing the
15 variations with respect to ~his n~minal transmission characteristic which
are caused by deviations with respect to the nominal lengthandthe nominal
ternperature which always occur in practice. The adjustnlent signal for the
autcrnatic equalization rnay ~e obtained, for example, by means of a
regulating circuit ~J~Thich comprises a peak detector which is connected to
20 the output of the equalizing arnplifier and whose output signal is
utilized to adjust the equalizing arnplifier so that the pulse signals
at its output have a constant peak value~
Under given conditions, the control range desired can ke so
læge that it c~ not be achieved with a single equalizing net~rk. For
25 exalrq?le, for an 8 M bit 120 channel pulse code ~dulation systern on
symmetrical cables, an autornatic equalizing system ~s required with a
regulat:lng xange of 56 dB at 4.224 ~z. i.e. the 1/2 bit frequency. This
large control range is required kecause the usable section lengths are
strongly dependent on koth geographical conditions and the near cross-
30 talk in symnetrical cables. For the design accuracy, -the phase ]inearity
of the equallzation is oE particular importance kecause the non-linearity
of the phase with change-over b~tween fixed patterns in data transmission
gives rlse to jitter in the clock frequency (change-over jittRr). In
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PHN 10.479 2 23-06-1983
order to keep the phase linear in the whole control range of the
equalization, it is necessary for the cable damping to be equalized
practically up to the bit frequency. This means that, when a regulating
sweep of 56 dB at half the bit frequency is desired, a re~ulating sweep
of 79 dB is required at the whole bit frequency. It is im~ossihle to
realize this very large control range with a single equalizing net~ork.
In such a case, several equalizing networks are connected in series, the
amplification of these networks being adjusted simultaneously with the
aid of a rec3ulating circuit.
The fact that several networks are adjusted simultaneously has
the disadvantage that in the higher part of -the frequency band in which
the equalization takes place the regulating errors of the various
networks will be added to each other, which is undesirable.
The invention has for its object to mitigate the aforementioned
5 problem. The invention provides an equalizing network as set forth in
the opening pharagraph characterized in that each regulating network is
connected to a different reference voltage so that each recJulating
network becomes operative only after the preceding network has reached its
extreme position.
An embcdim_nt of the invention will be described, by way of
example, with reference to the accompanying drawings, in which:
Fic3~re 1 shows in block schematic form an equalizing network
i according to the invention.
Figure 2 is a circuit diagram of a possible emkodim~ent of the
25 equalizing network of Figure 1.
Figure 3 shows a diagram for explanation of the operation of
the equalizing netw~rk according to the invention.
The equalizing network sh~n in Figure 1 comprises the series
arrangment of ~our regulating networks I to IV inclusive. The input
30 signal to be equalized is supplied to an input 1 of the equalizing
network which is connected to the input of the network~IO The output
sic3nal of the netw~rk IV is supplied through a filter 7 to the output 8
of the equalizing network. The output of the filter 7 is connected through
a peak detector 6 to control inputs 2,3,4 and 5 of the respective
35 regulating networks I to IV inclusive. The regulating networks I, II, III
and IV each have a reference voltage input 16,14,12 and 10, respectively,
which are each connected to a different point on a voltage d:ivider
constituted by resistors 17,15,13 ~nd 11. The voltage divider is arranged
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PHN 10.479 3 23-06-1983
bet~een points 18 and 9, to which the supply voltage for the equalizing
netw~rk is applied. Delay v~ltage U1, U2 and U3 are produced across the
resistors 15,13 and 11, respectlvely. These delay vo]taa,es co-operate
with the control signals applied to the inputs 2,3,4 and 5 ln a manner
such that a next rea,ulating network becomes operative only after the
preceding regulating network has reached i-ts extreme regulating position.
As will appear hereinafter, this means that this preceding reguJating
net~ork is in its faultless design position. This can ~e a maximum
position or a minimum position, dependent upon the equalization desired.
mls means that in the equalizing network according to the invention
only the regulating error of the next regulating network is of im~ortance.
All the remaining regulating networks are in the faultless design p~sition
during the regulation of the next regulating netw~rk and consequently do
not contribute to the overall regulating error of the equalizing network.
Since the regulating networks themselves also have D.C. amplification for
the control voltage, the difference between two successive control
v~lt~lges need not be more than 0.2 V. This value is not critical. To
ensure that the regulating net~orks become operative in order of succession,
the said difference is chosen to be comparatively large, for example,
0.3 Volt or more. me high amplification in the control loop guarantees
that, when the extreme position of one of the regulating net~orks is
reached, the next regulating network nevertheless becomes operative
automatically without interruptions.
In the em~odiment of the equalizing net~ork of Figure 2, the
regulating network I comprises six transistors 20 to 25 inclusive, an
amplifier 29, threerresistors 26,27 and 28 and fi~e impedances 40,41,42,
43 and 44. The ~7arious reference voltages are produced by a voltage
divider comprising the series arrangement of three resistors 13,15 and 17,
which v~ltage divider is arranged between the points 12 and 18 of the
30 equalizing network. The input signal Vi to be processed is supplied to the
input terminal 1 of an impedance network comprising the impedances 40 to
49 inclusive~ This impedance netw~rk is coupled to the two regulating
net~rks I and II. The output of the im~edance net~rk is applied tD a
filter having a prescribed transmission characteristic, for example,
35 a Nyquist filter, the output signal keing derived from this output 8,
while further a control signal is produced by means of a peak detector 6
j for controlling the amplification of the t~o regul~ingne~works I and II.
The regulating net~ork I comprises an amplifier 29 having an amplification
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PHN 10.479 4 23-06-1983
~ 1, whose output is connected to -the junction of the impedances 44 and
45 and whose input is connected to the junction of the collectors of the t~o
transistors 20 and 22. The junction of the two transistors 20 and 22 junction
is further cor.u~ected through a resistor 26 to the point 12. r~he emitters of
5 the transistors 20 and 21 are connected together and, through the series
arrangement of the collector-emitter path of the transistor 24 and the resis-
tor 27, to the point 18. The base of the transistor 24 is connected to the
junction of the ~npedances 40 and 41. The emitters of the two transistors
22 and 23 are connected together and, through the series arrangement of the
collector-emitter path of the transistor 25 and the resistor 28, to the point
18. The base of the transistor 25 is connected to the junction of the impe-
dc~nces 43 and 44. The j~mction of the impedances 41 and 43 is connected
through the impedance 42 to the point 18. The bases of the t~o transistors
21 and 22 are connected together and to the junction 16 of the two resistors
515 and 17 of -the voltage divider, which junction constitutes the reference
voltage input of the regulating network Io The bases of the tw~ trc~nsist.ors
20 and 23 are connected to the control input 2 of the regulating network I.
The regulating network II comprises an amplifier 39 having an
amplification`~1, whose o~tput is connected to the jurction of the
~impedance 49 and the input of the filter 7 and whose input is connected
to the junction of the collec~tors of two transistors 30 and 32 and one
end of a resistor 36 whose other end is connected to the point 120 The
emitters of two transistors 30 and 31 are connected together through the
series arrangement of the collector-emitter path of a transistor 34 and
~Sa resistor 37 to the point 18. I~he base of the tranistor 34 is connected
to the junction of the in~edances 45 c~d 46. The emitters of the two
transistors 32 and 33 are connected together and through the series
arrangement of the collector-emitter path of the transistor 35 and a
resistor 38 to the point 18. The base of the transistor 35 is connected
30to the junction of the impedances 48 and 49. The junction of the impedances
46 and 48 is cormected through the impedance 47 to the point 18. The
bases of the two transistors 31 and 32 are connected together and to the
junction 14 of the two resistors 13 and 15 of the voltage divider, which
junction constitutes the reference voltage input of the regulating
35amplifier II. The bases of the two transistors 30 and 33 are connected
to the control input 3 and 2 of the regulating netw~rks I and II,
respectively, and through the peak detector 6 -to the output 8 of the
equalizing ne ~ rk~ The collectors of the trctnsistors 31 and 33 are
P~ 10.479 5 23-06-1983
are connected together and to the point 12.
If it is assumed that the control v~ltage of the peak detector
6 i5 such that the potential at the bases of the transistors 20 and 23 is
neyative with respect to ~he potential at the bases of the transistors 21
and 22, the transistors 20 and 23 are cut off and the transistors 21 and 22
are conducting. The input signal supplied to the input 1 is supplied
through the impedances 40,41,42, and 43 and the transistors 25 and 22 to
the input of the amplifier 29. The junction 50 of the impedances 43 and
44 in this case constitutes the signal input proper of the amplifiying
lD part of the regulating netw~rk I. The overall amplification is the sum of
the amplifications of the transistors 25 and 22 and of the amplifier 29~
me impedance 44 in this case is arranged between the output and the input
of the amplifying part of the regulating network I. The input signal Vi
reaches in attenuated state via the impedances 40,41,42 and 43 the signal
input proper 50 of the amplifying part of the regulating natwork I, while
only the impedance 44 is present in the feedback path of the amplifying
part of the regulating network I. In the embodument shown here, a maxim~n
attenuation will occur with respect to a nominal an~lification; see Eigure 3a.
If it is assumed that the control voltage of the pea~ detector
6 is such that the potential at the bases of the transistors 20 and 23
is positive with respect to the potential at the bases of the transistors
21 and 22, the transistors 20 and 23 are conducting and the transistors
21 and 22 are aut off. The input signal supplied to the input 1 is
supplied through the impeda~ce 40 and the transistors 24 and 20 to the
input of the amplifier 29. The junction 51 of the impedances 40 and 41
in this case constitutes the signal input proper of the-amplifying part
of the regulating netw~rk I. The overall amplification is the sum of the
amplifications of the transistors 24 and 20 and of the amplifier 29. The
impedances 41,42,43 and 44 in this case are arranged between the output
and the input of the amplifying part of the regulating network I. The
input signal Vi reaches substantially without attenuation through the
impedance 40 the signal input proper 51 of the amplifying part of the
regulating net~rk I, while now the impedances 41,42,43 and 44 are
.
present in the feedback path of the amplifying part of ~ regulating
netw~rk I. In the embodiment shown here, a maximum amplification will
occur with respect to a nominal amplification; see Figure 3b~
In all other regulating positions of the eq~lalizing network,
the input of the amplifier 29 is connected to a different point of the
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PHN 10.479 6 23-06-1983
series arrangement of the impedances 41 and 43 located bet~een the
points 50 and 51. The ncminal amplification occurs when all the transistors
20 to 23 inclusive are conducting to the same extent. When the two
impedances 41 and 43 are equally large, this means that the input of the
amplifier 29 is effecti~ely connected to the junction 52 of the impedances
41 and 43~ NOTE~ re~er~n~e numeral 52 is not shown in Fi~ure 2.
For an ideal equalization controlr in general the following
relation applies:
F(w) = F1(w)+F2(w~.F3(~) (1)
In this relation, F1(w) is a nominal constant frequency-dependent
damping, which may be present already in the regulation itself or otherwise
may be obtained b,y arranging separate fixed equalizing net~orks and/or
amplifiers before or after it. In the e~odiment shown in Figure 2,
F1(w) is realized, for example, with -the Nyquist filter 7. F2(w)
15 represents the required regulating characteristic and is realized by
means of the impedances 40 to 49 inclusive. F3(~) is a function which
is proportional to the control vol-tage or current supplied by the peak
detector 6. Figure 3c shows a ~raph illustrating the regulating
characteristic.
The regulating characteristic for ~ = 1 corresponds to the
regulating position sho~ in Figure 3b; the regulating characteristic
for~ = O corresponds to the re~ulating position shcwn in F_gure 3a and
the regulating characteristic for ~ corresponds to -the case in which
the input of the amplifier 29 is connected to the point 52. In all these
25 three cases, it is ensured that the regulating error is equal to 0
(three-point regulation). For all the other values of~, the regulating
errQr ~ will occur, as is indicated, for example, in Figure 3c for ~ = 3/4 and
~ = 1/4. This is due to the fact that, when the transmission for~ula is
expan~ed into a series, there is obtained ~esides the desired term
30 F2(w).F3(~) also a series of odd higher hc~rm~nic terms of the form
F2(w) .F3(`~) +....
In an intermediate position, for example ~- = 3/4~ rtâhæ at higher
amplification will decrease at a dispro~ortionately highe~ fre~uencies
~ue to the higher harmonic terms than at lower frequencies at which the
35 influence of these -terms is considerably sr~aller. When several of these
regulating netw~rks are arranged in cascade without further precautions,
the regulating errors of the separate regulating networks are added to
each other, which gives rise to an overc~ll regulating error which is no
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PHN 10.479 7 23-06-1983
longer acceptable.
In the en~odiment of Figure 2, the reference ~oltage input of
the regul.ating network II is c~nnected to a higher poin-t 14 of the voltage
divi.der constituted by the resistors 13,15 and 17 ~han. the point 16 to
which the reference voltage input of the reg~ating networ.k I is
connected. The desired difference voltage between the two regulating
net~rks I and II is produced across the resistor 15. This difference
is proportioned so that the control space hetween the points 3 and 14
of the re~ulating network II and the control space ketween the points 2
and 16 of the regulating netw~rk T have no con-trol range:.in co~on.
m is means that, w~en one of the regulating amplifiers I or II is
controlled, the other regulating amplifier II or I is adjusted to one of
the faultless extre.me regulating positions for ~ = O ori~ = 1; see Figure
3c. Consequently, always only one regulating net~rk is adjusted at a
timet as a result of which the o~lerall regulating error is a].ways equal.
to the regulating error of this single adjusted netw~rk.
As is known, the noise factor of an equalizing network is
increased by an impedance network at the input by an amount equa]. to the
damping of this in~pedance network With long cable sections, i.e with
a low input level, it is therefore of .umportance that the regulating
network is fixed in its n~ximum position at the input of the equalizing
network; see Figure 3b~ In this case, the impedance network is inc].uded
in the feedback:loop of the regulating network. This netw~rk is allowed
to bec~me operative only after the cable length has hecome sufficiently
small and the succeeding regulating networks have reached their extreme
minimum position (~ = 0). This regulation ~rinciple is therefore of
importance not only for keeping the regulating error small, but also
for keeping the influence of the noise small, the latter ~eing also
determinative of the order of succession in which the regulating networks
arranged in cascade are adjusted.
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