Note : Les descriptions sont présentées dans la langue officielle dans laquelle elles ont été soumises.
Z 2036~-2361
BACKGROUND OF TIE INVENTION
This invention relates to a dynamic semiconductor memory cell wit
random access (DRAM). In particular to a DRAM in which the bit line is diffused
into the semiconductor substrate in the area of the memory cells; adjacent
to the bit line a storage electrode for the creation of the storage capacity
is arranged over the semiconductor substrate; and above the bit line and story
age electrode, insulated therefrom and at least partially overlapping the
storage capacity electrode, the transfer electrode controlled by a word line is
arranged. Methods for the production of the DRY are also disclosed.
To fabricate semiconductor memories using MOW techniques is well
known. These memory cells consist for example of a storage capacitor and a MOW
transistor, the control electrode of which is connected to a word line. The
two controlled electrodes of the MOW transistor are arranged between the storage
capacitor and a bit line. Such memory cells are referred to as single tray-
sister RAM (Random Access Memory) cells.
A disadvantage of such single transistor memory cells is that
space is needed for the diffused areas in the memory component. But because a
maximum of memory cells are to be arranged on a memory component in semi-
conductor memories, the trend is to make the individual memory cell as small
as possible.
One known solution is to arrange tune storage electrode for the
formation of the storage capacitor over the semiconductor substrate and in-
sulfated therefrom. Adjacent to the storage capacitor the bit line is diffused
into the semiconductor substrate. To permit a charge exchange between the
storage capacitor and the bit line, arranged on the semiconductor substrate
and insulated therefrom is a so-called transfer electrode, which overlaps the
storage capacitor and the bit line at least partially.
Other space-saving possibilities are the use of the double-
polysilicon technology in the production of memory cells. A memory cell of the
previously mentioned kind with diffused bit line with "buried contact" in
two-layer polysilicon technology has been described in an article by V. L.
Hideout in IEEE Trans. Electron. Dew. Vol. Ed-26, No. 6 (1979) at pages 839 to
852, specifically at page 846.
SUMMARY OF TIRE INVENTION
It is an object of the present invention to disclose memory
cells for dynamic semiconductor memories with random access (DRAM) with in-
creased packing density.
Furthermore, it is an object of the present invention to state
methods for the simple production of Drills ensuring that process steps require
in complicated masks which require high accuracy of adjustment are avoided.
The foregoing objectives and others are realized by a memory
cell of the previously mentioned kind in which the bit line and the storage
electrode comprise a doped solaced of a metal o-f high melting point and the
length of the transfer gate is defined by the spacing of the solaced on the
bit line and on the solaced of the capacitor electrode.
In a further embodiment of the invention it is provided that the
bit line and the storage capacitor electrode include an arsenic, phosphorus,
or boron doped solaced of the metals tantalum, titanium, tungsten, or Malibu-
denim. More silicon is contained in the compound than corresponds to the
dieselized stoichiometry. Furthermore, the transfer electrode consists of
polysilicon, the system polysilicon/high melting metal, the system polysilicon/
metal solaced, a solaced of the metals tantalum, titanium, tungsten or
molybdenum, or of pure metal.
For the fabrication of the memory cell of the invention a method
-- 2 --
is provided which is characterized in that the drain zone under the bit line
is produced by diffusion of solaced of a metal of high melting point, provide
Ed with a doping substance of a second conductivity type and deposited directly
on the surface of a semiconductor substrate of the first conductivity type
divided by thick oxide Jones on or in its surface. The doping can be effected
after the deposition of the solaced layer by implantation of doping ions of
the second conductivity type into the solaced. Alternatively, a metal
solaced layer may be applied, doped by the use of a tantalum, titanium lung-
stun or molybdenum solaced target mixed with the doping substance, by
lo atomization or by reactive atomization of unhoped solaced in an atmosphere
containing the doping substance. As doping substance of the second conductive
fly type arsenic, phosphorus, or boron are used.
Other features and advantages of the invention will be apparent
from the following description of the preferred embodiments and from the claims.
For a full understanding of the present invention, reference
should now be made to the following detailed description of the preferred
embodiments of the invention.
BRIEF DESCRIPTION OF Tiff DRAWINGS
.. _ _ . . . . . . _
Figures l to 3 show in sectional and partially cut away views
the process steps for the dynamic RAM cell according to the invention.
Figure shows a further preferred embodiment of the invention
in which a self-aligned method is used for generating the gate electrode.
DETAILED DESCRIPTION
... .. .. .. _
Figure l: On a p-doped silicon semiconductor substrate l, Sue
layers 2 structured for the separation of the active zones are produced by the
so-called LOOS or isoplanar method. Then over the whole area an oxidation
process is carried out, and the resulting oxide Lowry no) is structured for
I
the definition of the storage capacitors and of the bit line. Then follows the
deposition of an arsenic-doped tantalum solaced layer 4 of a layer thickness
of 200 no. This may be accomplished, for example, by atomizing with the use
of an arsenic-doped tantalum solaced target, more silicon being present than
corresponds to the stoichiometry of tantalum solaced, to permit subsequent
reoxidation. On this layer (4) an insulation layer 5 consisting of Sue is
applied over the whole area in a layer thickness of about 300 no, to reduce the
overlap capacities and to avoid the out-diffusion of doping substance. The Sue
layer 5 with the underlying tantalum solaced layer 4 is structured in the bit
line zone 10 and in the storage capacity zone 11 by a reactive dry etching
process. The distance of the thin oxide edge 14 from the bit line zone 10 and
from the storage capacitor 11 must correspond at least to the adjustment toter-
ante yin the embodiment the distance is in the range of 500 to 1000 no).
Thereby it is ensured that the solaced layer 4, 11 has no contact with the sift-
con substrate and that the solaced layer 4, 10 rests on the whole area of the
substrate.
Figure 2: Figure 2 shows an oxide etching over the whole area
which follows the previous steps. By this etching the oxide zone 14 is removed.
Simultaneously with the thermal treatment for producillg the gate oxide 6 at
900C, the drain zone 8 lying under the solaced structure 4 in the bit line
area 10 is produced by out-diffusion of arsenic (n ) and the solaced edges
are provided with an oxide 7.
Figure 3: Following the production of the channel zone 9 in the
transfer gate area 12 by implantation of boron ions, the polysilicon layer 13
forming the transfer gate 12 is deposited on the whole area. It is structured
so that the gate electrode overlaps the edge of the drain zone 8 toward the
channel zone 9 and the edge of the storage capacitor electrode 11 toward the
channel zone 9.
Lastly, an intermediate layer serving as insulation oxide is pro-
duped (this is not shown). The contact holes for the conductor tracks are
etched and the metallization is carried out.
Figure 4: This figure shows another advantageous embodiment of the
invention, in which, in contrast to Figure 3 and in order to produce minimum
overlap capacities, the transfer gate 12 is designed to be not overlapping,
but rather, using the so-called lift-off technique, to be introduced self-
adjustingly (self-alignment) between the solaced structures I. This is done
as follows: Instead of the insulation layer 5 consisting of Sue (according
to Figure 1) an insulation layer 15 consisting of silicone nitride is applied,
and instead of the polysilicon layer 13 forming the transfer gate (according to
Figure 3), a metal solaced layer 23 is used. During vapor deposition of this
metal solaced layer 23, the connection at the silicon nitride edges in the
transfer gate region 12 necessarily breaks off. Figure 4 shows the arrangement
after the structurization of the gate electrode. The partial structures aye
and 23b present on the nitride layer 15 are removed upon removal of the nitride
layer 15 using an isotropic etching method. Then, in a manner not shown, the
insulation oxide is produced the contact holes for the conductor tracks are
etched and the metallization is carried out.
These processes are similarly applicable with p-channel transistors,
as is described for example in the article by Shimohigashi in IEEE Trans.
Electron, Dew. Vol. ED-29, No. 4 (1982) pages 714 to 718.
For the memory cell according to the invention with the so-called
solaced field plate (4, 11), the bit line of solaced (4, 10) and the n zone
8 diffused out of the solaced, the following advantages over the known arrange-
mint (for example Hideout) are achieved:
1. The solaced acts as a self-aligning contact for the transfer
transistor. Because of the self-aligning contact a higher packing density is
possible.
2. The gate length is not dependent on the adjusting accuracy, as
it is defined by the distance between solaced bit line and between solaced
field plate created in the same lithography step.
3. By the use of the solaced one obtains a very low-resistance
bit line.
There has thus been shown and described a novel DRY and a fabric
cation method therefore which fulfills all the objects and advantageous sought
therefore inn changes, modifications, variations and other uses and applique-
lions of the subject invention will, however, become apparent to those skilled
in the art after considering the specification and the accompanying drawings
which disclose preferred embodiments thereof. All such changes, modifications,
variations and other uses and applications which do not depart from the spirit
and scope of the invention are deemed to be covered by the invention which is
limited only by the claims which follow.
