Note : Les descriptions sont présentées dans la langue officielle dans laquelle elles ont été soumises.
Background of the Invention
The present invention relates to a video
controller preferably for use in a microcomputer system.
The video controller controls the video display and is
capable of both character generation control and cell
generation control.
It is an object of the present invention to
provide an improved video controller circuit, prefer-
ably for use in a microcomputer system and which enables
character inversion.
Another object of the present invention is to
provide an improved video controller as in accordance
with the preceding object and which permits video
inversion under such control to provide inversion on
a character-by-character basis.
Still a further object of the present inven-
tion is to provide an improved video controller which
employs as the heart of -the controller, a cathode ray
tube controller for coupling signals to a video RAM
of the video controller.
A further object of the present invention is
to provide an improved video controller in accordance
with the preceding objects and which has means for
controlling the output video signal to provide graphic
overlay.
Another object of the present invention is
to provide an improved video controller in accordance
with the preceding objects and which has control for
enabling, in addition to character generation and cell
generation, alternate set control preferably by way of
the system character generator ROM.
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Summary of the Invention
In accordance with the invention there is
provided a video controller. The controller includes
means for providing serial dot data signals represent-
ative of a character line. It also includes circuit
means coupled from the serial means and control signal
means having video inverting and video non-inverting
states. Means are provided for coupling the control
signal means to the circuit means to provide one of
inversion and non~inversion of the signal that is
coupled from the serial means.
The invention also relates to video control
apparatus for controlling a serial video signal which
includes means for receiving the serial video signal
on a character line by character line basis and com-
posed of 1 and 0 code bits. Output means provide an
output video signal and control means are adapted to
be controlled by a control signal having video invert-
ing and video non-inverting states. Means are pro-
vided for coupling the control means to the output
means whereby in the video non-inverting state the
output video has a first predetermined composition,
and in the video inverting state has the inverted
composition.
In accordance with a particular embodiment
there is provided a video controller for a micro-
computer system which includes a video memory means
or storing video character codes. The controller
also includes character generator means and means
coupling the output of the video memory means to the
character generator means. The character generator
means provides dot data signals. The controller
also includes a shift register means and means for
loading the dot data signals into the shift register
`gl~'~
means and for shifting the signals therefrom. The
controller also includes output gating means and
means coupling the output of the shift register means
to the output gating means. The con-troller also
includes control signal means having video inverting
and video non--inverting states and means coupling the
control signal means to the output gating means to
provide one of inversion and non-inversion of the
signal to the output gating means from the shift
register means.
In accordance with a more particular embodi-
ment of the invention there is provided a video con-
troller, preferably for use in a microcomputer system.
This video controller basically receives data from a
system memory such as a random access memory. Address
data is presented to a video memory means which is
adapted to store video character codes. The video con-
troller also comprises character generator means and
means coupling the output of the video memory means to
-the character generator means. The character generator
means is adapted to provide data signals for display
of characters. For example, the input data to the
character generator may be in ASCII form and the
outputs from the character generator are in the form of
of a set of parallel signals indicative of a line of
a character at a time. A shift register couples from
the output of the character generator and means are
provided for loading the data signals into the shift
register in parallel and for shifting the signals
therefrom in serial. In accordance with the invention,
output gating means are provided and means are also
provided for coupling the output of the shift register
to the output gating means. In order to provide signal
inversion, there is provided signal control means having
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video inverting and video non-inverting states.
Means couple the control signal means to the output
gating means to provide one of inversion or non-
inversion of the signal to the ou.put gating means,
which signal has been coupled from the shift register.
The aforementioned control signal means preferably
includes circuit means having one state indicating
inversion and another state indicating non-inversion
of the character. This control is provided select-
ively on at least a character-by-character oasis.
The aforementioned output gating means preferably
includes a logic gate having a signal input for
receiving the serial shift register signal and also
having a control input for receiving the control
signal from the control signal circuit means. The
logic gate that is provided herein is disclosed as
an exclusive OR gate that enables the character
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inversion. The means thaw couple the output of the shift
register to this output gate preferably comprises an AND gate
means having vne input for receiving the shift register serial
output. With regard to this AND gate, there is also provided
associated therewith a blanking signal which is coupled to the
vther input of the AN gate. Tnis blanking signal enables
blanking of the screen between character rows.
The video XAM couples to the character generator,
preferably by way of an output data latch. The data lines
between the data latch and the character generator do not all
connect directly, but instead there is also provided logic
control referred to herein as alternate set logic means for
controlling data flow content from the data latch to the
character genrator. The alternate set logic means includes
gate means response to an alternate set enabling signal and at
least one data bit from the data latch means. This gate means
preferably includes an OR gate responsive to the alternate 5et
enabling signal or a first data bit. The gate means also
includes preferably an AND gate means having one input
connected to the Ox gate means, a second input from a second
data bit, and the output coupling to the character generator at
a position corresponding to the second data bit.
In accordance with the invention there is also provided in
the disclosed em~oaiment, a cell generator means and means
coupling this cell generator means in parallel with the
character generator meansO Thy cell generator couples in
common at its output with the character generator and both
devices are coupled to the parallel inputs of the shift
register The cell generator preferably comprises a
multiplexer and a video data output buffer. Now, associated
with the character generator and cell generator is logic means
including a first logic gate responsive to a first data bit
signal from the video memory means for providing a signal, the
state of which is representative of either graphic generation
or character generation. To provide this control, where is
provided a flip-flop coupled from this first logic gate and
having alternate states including one state enabling only the
character generator means and another state for enabling only
S the cell generator means. This first logic gate preferably
comprises an AND gate. The aforementioned control signal means
responsible for character inversion may be considered as
comprising a second logic gate having one input for receiving
an inverse video enable signal and a second input for receiving
a data bit.
In the disclosed embodiment, as the heart of the system,
there is proYided a cathode ray tube controller which receives
data inputs from a system databus. The output of the cathode
ray tube controller couples to the video memory. The cathode
ray tube controller is coupled to the video memory by means of
multiplexers which have two sets of different inputs. In the
disclosed embodiment, there are three quad input multiplexers.
These multiplexers each have a first set of inputsl coupled
from a cathode ray tube controller, and a second set of inputs
coupled Erom the central processing unit address bus.
Brief Description of the Drawings
Numerous other objects, features and advantages of the
invention should now become apparent upon a reading of the
following detailed description taken in conjunction with the
accompanying drawing, in which:
FIG. 1 shows one portion vf the microcomputer system
including the basic Z80 processor; and
FIG. 2 shows a portion of the microcomputer system
including programmable array logic (PAL circuits and decoders
used in generating timing signals used in the system; and
FIG 3 shows video circuitry along with the system random
access memory and cathode ray tube controller; and
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FIG. 4 shows additional timing for the system including
keyboard circuitry; and
FIG. S shows a portion of the microcomputer system
including cassette porting;
FIG 6 shows a portion o the microcomputer system
including video RUM and random access memory timing circuitry;
and
FIGS 7-9 show timing diagrams associated with the
microcomputer system shown in FIGS. 1-6.
Detailed Description
The video controller of the present invention is preferably
adapted for use in a microcomputer which may be of the
self-contained desk-top microcomputer type. The microcomputer
system includes a microprocessor such as the conventional Z-80
microprocessor shown in FIG. 1 which in the microcomputer
system of the present invention is capable of running at either
of two different clock rates. It also included preferably two
programmable array logic (PAL) circuits used for frequency
division and routing of appropriate timing signals.
The computer system is provided with main CPU timing from a
20-MHz. clock. Of the aforementioned PALS, a first PAL U3
divides the main clock signal by five to provide 4 MHz. CPU
operation. The main clock is also divided by ten to provide a
2 MHz. rate. The logic also waits the CPU at 4 MHz. clsck rate
for the Ml cycle. Thls first PAL U3 also divides the master
clock by four to obtain a S MHz~ clock to be sent Jo the RS-232
option connector as a reference for the band rate generator.
The second PAL U4 selects an appropriate 10 MHz. or 12 MHz.
clock video shift clock, and by means of a divider U5, provides
additional timing signals tG the video display circuitry to be
described in further detail hereinafter.
Low level signals from and to the CPU need to be buffered
or current amplified in order to drive many other circuits.
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The 16 address lines are buffered by devices U55 and U66 shown
in FIG. 1, which are uni directional buffers that are
permanently enabled. The tight data lines are buffered by
device U71. Since data must flow both to and prom the CPU, the
device U71 is a bi-directional buffer which can go to a three
state condition when not in use. Both direction and enable
controls come from the address decoding section.
In FIGo l the clock signal to the CPU is buffered by the
active pull-up circuit Q3. The RESET and WAIT inputs to the
CPU are buffered by gates U17 and U46. Control outputs from
the Z80 processor include the signals Ml-, RD-, WR-, MREQ- and
IORQ-o These signals are sent Jo the PAL U58 shown in FIG. 2
which combine these into other appropriate control signals.
Other than the signal MREQ- which is buffered by device U38,
the raw control signals go to no other components and hence
require no additional buffering.
The address decoding section is divided into two
sub-sectlons, namely port address decoding and memory address
decoding. In port address decoding, lower order address lines
are sent to the address and enable inputs of decoders U48, U49
and U50. Tne decoder U48 is also enabled by the signal IN-,
which means that it decodes port input signals, while decoder
U49 decodes port output signals. Memory mapping is
accomplished by the PAL U59 shown in FIG. 2 in the basic 16K or
64X system. In a 120 K system, the PAL U72 along with the
select and memory bit of the option register, also enter into
the memory mapping function.
Another component of the microcomputer system is the
read only memory lROM) shown in FIG. 1. In the microcomputer
system, the ROM is preferably of 14K capacity divided into an
8K ROM, a 4K ROM and a 2K ROW. The ROMS what are used
preferably have three-state outputs which are disabled if the
ROMS are deselected. ROM data outputs are connected directly
to the CPU da~abus. Toe ROMP contain a basic operating system,
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:~22~L3
as well as a floppy disk boot routine.
In the overall microcomputer system, the random access
memories are available as options in three different capacitieS
including 16K, 64K or 128K of RAM. The 16K option uses memory
type 4116. The 54K and 128K options which are described in
detail herein use memory type 666~. This type is of 64K by 1
capacity requiring only a single supply voltage.
Now, with regard to the drawing, there is shown in FIG. 3
random access memory 10 which is comprises of eight memory
units 10-0, 10-1, 10-2~ 10-3, 10-4, 10-5, 10-6 and 10-7. Each
of these memory units as mentioned previously is of type 6665
having associated therewith input control lines such as lines
12, address lines 14 and output data lines 160 The data
outputs from the RAM 10 couple to the databus 18~ The databus
is identified by the signals D0-D7.
A dynamic RAM as used herein requires multiplexed incoming
address lines. This is accomplished by means of circuits 20
and 22. These circuits are each of type 74157 referred to as
quad-multiplexers. The four output lines from the multiplexers
20 and 22 connect by way of a resistor array 24 to the address
inputs of the RAM. The inputs to the multiplexers 20 and 22
are taken from the address bus 24. The address bus 24 is
designated by address lines A0-A15 as noted.
The ransom access memory 10 is of conventional design in a
readily available circuit chip and has signals coupled thereto
such as memory read-write signals and memory request signals.
Reference has been made hereinbefore to control lines 12.
Tnese include a memory read-write signal (MWR~ and a row
address strobe signal (WAS). There is also provided as shown
at the bottom of the RAM 10 a column address select (CAS).
The data lines 16 from the JAM 10 are coupled to the RAM
data buffer 26, This suffer may ye of type 74LS244 referred to
typically as a octal buffer. The output of the RAM data buffer
26 couples to the databus and cathode ray tube controller 30.
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For the 12~K JAM option, there are two rows ox the 64K by 1 JAM
circuits type 6665, The proper row is selected by the signal
CAS- shown in the drawing and generated from a programmable
array logic (PAL) circuit U72. The output data lines 27 from
the RAM data buffer 26 couple as data slgnals D0-D7 to the
cathode ray tube controller (CRTC) 30~ The controller 30 is in
a sense the hear of the video display circuitry. This
controller is of type MC6835. The controller 30 allows two
screen formats; 64 by 16 and 80 by 24. Since the 80 by 24
screen requires 1,920 screen memory locations, a 2K by 8 static
RAM is used for the video RAM. The 64 by 16 mode has a
two-page screen display and a byte in the options register for
determining which page is active for the CPU. One offsets the
start address of the controller 30 to gain access to the second
page 64 by 16 mode. In this connection, note the input control
signal on line 32 which is a mode control signal controlling
either 64 by 16 or 80 by 24 operation.
The controller 30 as mentioned previously is a conventional
circuit thaw generates all of the necessary timing and control
signals associated with video control including addresses for
the video RAM 34~ The video RAM 34 is of type 4016 and is a
200 nanoseconds JAM of capacity 2K by 8. This is a static
RAY. It is noted that the address lines from the controller 30
are coupled in groups to three address multiplexers 36, 38 and
40. These multiplexers are controlled by the CRT clock signal
~CRTCLK). Thus, addresses to the video RAM 34 are provided
from the controller 30 when the screen is being refreshed and
are provided directly from the CPU by way of the address bus ~4
when updating the screen data. This alternate control is
controlled by the signal CRTCLK which is a bi-level signal that
controls the operation. This signal CRTCLK is coupled to pin 1
of each of these multiplexers. Each of the multiplexers 36, 33
and 40 is referred to as a quad multiplexer of type 74LS157.
The data lines of the video XAM 34 may be referred to as a
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... . .
video databus 42~ This video databus intercouples the video
RAM with a video data read latch 44, a video data write buffer
46, and a video output latch 48. The video data read latch 44
is an octal latch of type 74LS373. The video data write buffer
46 is a octal buffer of type 74LS244. The video output latch
4~ is an octal flip-flop circuit of type 74LS273. The data
transfer between the CPU and the video RAM 34 is latched by the
video data read latch 44 whose output connects to the databus
l Input data passes to the video data write buffer 46 from
the databus l to the video RAM.
During a screen refresh, the data outputs of the video RAM
34 are latched by tne video output latch 48. The outputs from
tAe video RAM 34 are A~CII character codes. These data outputs
become the addresses for the character generator E~OM 50. The
character generator TOM 50 may be of type MCM68A316E. In
accordance with the system described herein, there is also
provided an alternate display in the form of low resolution
graphics. Accordingly, there is provided a data selector 52
and associated video data output buffer 54. The selector 52
may be in the form of a dual multiplexer of type 74LS153. The
video data OLItpUt buffer 54 may be A octal buffer of type
74LS244. The multiplexer or selector 52 receives the data
signals from the video output latch and provides two control
signals which are coupled in common separately to the video
data output buffer 54.
The output of the character generator ROM 50 and the video
data output buffer 54 couple in common to the shift register 56
which may be of type 74LS166. There are control inputs
associated wlth the shift register 56 for loading data into the
shift reglster, and shifting data on a clocked basis out of the
shift register. The line 58 is the basic video output from the
shift register 56.
The inputs to the shift register 56 are the latched data
outputs from either the character generator ROM 50 or the cell
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generator at the video data output buffer 54~ The shift clock
input on line 57 is a timing signal generated from PAL U4 and
is at a frequency of 10.1376 MHz. for the 64 by 16 mode and at
a frequency of 12.672 MHz. for the 80 by ~4 mode of operation.
The serial output from the shift register on line 58 after
signal processing to be describe hereinafter, becomes the
actual video dot information shown at the video output line
59.
Special timing considerations in the video circuitry are
handled by means of the latch 60. The latch 60 may be a quad
flip-flop of type 74LS175. In this regard, it is noted that
there are four input data lines and four pairs of output lines
including assertion and negation outputs. This timing or
synchronization provided by the latch 60 includes a blanking
control originating from the controller 30 and shift register
clocking originating from a PAL of the microcomputer system.
In accordance with the present invention, additional video
control and timing functions, such as sync buffering, inversion
selection, dot clock chopping, and graphics disable of a normal
video, are handled by logic gating shown on the drawing and to
be soon describedO
In the drawing, there are two sets of logic including set
62 and set 64. Logic set 62 controls, inter alia, the
forementioned video inversion. In this regard, note the signal
IN W ID (inverse video) on line 66 which couples to NAND gate
68 and also inverter 70. The output of the inverter 70 coupled
to an AN gate 72. The output of the AND gate 72 in turn
coupled to a NAND gate 74. The logic set 62 also includes NAND
gate 75 and AND gate 76.
When the mode of operation is not in inverse video, then
the line 66 is low and an enabling signal is coupled by way of
the inverter 70 to the AND gate 72. The other input to the
gate 72 is the dataline D7 It is noted that this also couples
to one input of the NAND gate 68. The logic set 62 also
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receives the dataline signal D6 which it is noted is coupled by
way of inverter 75 to one input of the NAND gate 74. The
output of the gate 74 by way of line 71 couples to a control
flip-flop 78. The flip-flop 78 has its assertion output
coupled by way of line 79 to the bufer 54 and has its negation
output coupled by way of line 80 to the character generator ROM
50. These outputs of the flip~flop couple to enable inputs of
the buffer and ROM. A load timing signal is coupled to the
clock input of the flip-flop 78. This signal is coupled on
line 81. When the signal on line 71 is high, the flip-flop 78
lS set and the low output on line 80 enables the character
generator. Alternatively, when the signal on line 71 is low,
this causes a resetting of the flip-flop 78 upon occurrence of
the clocking thereon and this causes a low signal on the line
79 for enabling the cell generator section by directly enabling
the video data output buffer 54.
In accordance with the present invention, there is provided
for an inversion of the video (black-to-white and
white-to-black). In this connection, refer to the inverse
video signal on line 66. When the system is not in the inverse
mode of operation, the signal on line 66 i5 low. This signal
is inverted by inverter 70 and couples to the AND gate 72 to
enable the gate 72. Assuming that the dataline D7 is also at
its high state, then the output of the AND gate 72 is also
high. The output from the gate 72 couples to two different
locations. This signal couples directly to the video output
latch 48 so as to provide, in normal, non-inverted operation,
all eight data bytes from the video output latch 48 to the
character generator S0. The signal from the gate 72 also
couples to the NAND gate 74. Now, the data line D6 which
couples to the inverter 75 has its state establish whether one
is generating graphics or characters. ion graphics the data
bit D6 is low and for characters the data bit ~6 is high.
Assuming that the data bit D6 is low for graphics, then the
.. . . . . .. . . . ..
inverter 75 causes two high inputs to occur at the gate 74 thus
causing a low output therefrom. The output from the gate 74
couples to two different places. The output of this gate
couples by way of the aforementioned line 71 to the flip-flop
78 and this output from gate 74 also couples to NAND gate 75~
Tnis low level signal at the output of gate 74 provides a high
signal at the output of gate 75 and also a high at the output
of gate 76. The output of gate 76 at line 73 lS shown coupling
to the latch 60~ The latch 60 forms a synchronizer providing
predetermined delays so that all operations on the character
are synchronized at the output video. The signal on line 73
entering the latch 60 is delayed at the output line 82. This
signal couples to the AND gate 83. The AND gate ~3 also
receives on its line 58 the direct character code bits from the
shift register 56.
Now, as mentioned previously, the output of gate 76 is high
and this high level signal, delayed by the latch 60 is coupled
to the gate 83~ This forms an enabling signal so that the
character code bits on line 58 pass directly through the gate
83 to the exclusive OR gate 84. The character code bits are
capable of passing by way of the gate 84, by way of NAND gate
85 and inverter 86 to the uutput video line 59. The gate 85
has inverted sensing inputs. The gate 86 is shown as an
exclusive 0~ gate but is logically an inverter having one of
its inputs permanently connected to a voltage high. The output
on the video line 59 lS the dot pattern for generating graphics
and characters on a line-by-line basis on the screen at a
typical raster scan rate.
The low output from the gate 74 also couples by way of line
71 to the flip-flop 78 and upon clocking of the flip-flop, it
is reset so that the output on the line 79 goes low thus
enabling the video data output buffer 54 for enabling data
transfer from the cell generator rather than the character
generator. The high signal on line 80 from the flip-flop 78
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causes a disabling of the character generator ROM 50.
Now, assuming that the data bit D6 is high which is to
indicate character generation rather than graphics or cell
generation, this signal is inverted by the inverter 75
providing a low input to the gate 74 which in turn is inverted
by the gate 74 to provide a high output. This high output
signal from gate 74 couples by way of line 71 to the flip-flop
78 so that upon occurrence of the next clock pulse at line 81,
the flip-flop 78 is set, assuming that it had been previously
reset. The setting of the flip-flop 71 causes a low signal on
line 80 for enabling the character generator ROM 50~ The
signal on line 79 prom the flip-flop 78 is high and disables
tne cell generation portion of the circuit or in particular it
disables tne video data output buffer 54.
The high output from the gate 74 also couples to the gate
75. The otner input to gate 75 is tne signal RA3 which is a
row select signal from the cathode ray tube controller 30.
This gate 75 is used for blanking to provide a blanking signal
between character rows. Thus, when blanking is to occur, the
signal RA3 is high and the output of gate 7.5 low. Tnis low
level signal is passed by way of line 73 to the latch 60. The
delayed signal is coupled by way of line 82 to the gate 83.
This low level signal inhibits the gate 83. Thus, the
character code bits on line 58 coupled to gate 83 are blanked
by virtue of this inhibit signal delayed so as to be properly
synchronized by means of the synchroniæing latch 60. In this
connection, with regard to the latch 60, it is noted that a
line intercouples the output of the first flip-flop at output
Ql to the data input 2D of the second flip-flop. It is the
output Q2 from the second flip-flop of the latch that couples
by way of the line 82 to the AND ga e 83.
When the signal ~A3 is not high, which is during a
character space and not between characters, then the output of
gate 75 is low and there is a low level signal coupled on line
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73 by way of the first two stages of the latch 60 so that the
signal on line 82, properly synchronized, is a high level
signal which enables the gate 83 and permit passage of the
character code bits from line 58 by way of gate 83 to the
exclusive OR gate 840
In this mode of operation just discussed, it has been
assumed that the signal on line 66 is low because there is not
video lnversion. It is noted that this low level signal
coupled to the gate 68 maintains the output of the gate 68 at
its high state. This signal couples by way of line 69 to one
input of the OR gate 86. The inputs to the OR gate are
inversion inputs. Associated with the gate 86 is also an
inverter 87 and a NAND gate R8~ It is noted that the output of
the NAND gate B8 couples by way of line 89 to the two latter
stages of the latch 60. Line 89 couples to the 3D input of the
latch. It is noted that the Q3- output from the latch couples
back into the fourth date input 4D and the output at Q4 couples
by way of line 90 to gate 92.
The inputs to gate 8~, look for low level signals. Thus,
when the signal on line 69 is at its high level and when one is
not enabling external graphics, then the output of the yate 86
is low. This low level signal ls inverted by the gate 88 to a
high level signal on line 89. A further inversion occurs in
the latch 60 and thus the signal on line 90 is low, thus
disabling both sections of the combination AND and NOR gate 92.
Thus, when the output of gate 68 i5 high because we are not
in inverse video, the signal on the line 69 is essentially an
inhibiting signal. However, for video inversion, the signal on
llne 66 goes to its high state. First, this signal couples by
way of gate 70 to AND gate 72 to inhibit the gate 72 so that it
has a low output. This low output is coupled to the video
output latch 48 so that the data bit D7 is always at a low
state. This low level signal also couples to gate 74 so as to
provide a high output from gate 74. This high output signal
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from gate 74 couples on line 71 to cause a setting of the
flip-flop 78. In this state, the line 80 is low and thus the
character generator is enabled. The high level signal from
NAND gate 74 also couples to the NAND gate 75 and provides
S operation as previously mentioned for providing blanking
between character rows As indicated previously, this is under
control of the signal RA3 from the cathode ray tube controller
30.
The inverse video signal on line 66, when at its high
state, also couples to gate 68 and assuming that the other
input to the gate 68 is also high, then the output from 68 goes
low. This low going signal on line 69 is indicative of
character inversion. This signal is coupled to gate 86 for
causing a high output therefrom which is inverted by gate 88 as
long as the display enable signal is present at the other input
of the gate. This provides a low output signal from the gate
88 which couples to the 3D input of the latch 60. It is noted
that the interconnection from the third to the fourth stage is
taken at the negation output Q3- and thus the output at line 90
is a high level signal coupling to the gate 92. for causing
enabling thereof However, it is only the lower gate 92A that
is enabled because the inverse video signal is present and also
the graphics is not enabled and thus the output from gate 87 is
high. The enabling of gate 72 provides a low output therefrom
which couples to one input of the exclusive OR gate 847 Thus,
in the video inversion mode of operation, the signal on line 93
is low whereas for non-inversion, this signal is high. This
has the effect of inverting the character code bits at the
output of gate 83. Under non-inversion conditions, the line 93
is high and for inversion the line 93 goes low.
The latch 60, as mentioned previously, is used primarily
for synchronization and it is noted that there is a delay
provided between the output of the gate 88 and the signal on
line 90 coupled to the gate 92. This allows for the proper
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. .. .. . _ . . . . .. .. . .. .. .
, ~2~39~3
synchronization between the data presented to the shift
register and the occurrence of the inversion signal.
In the drawing there is also shown the signal ENGRAF on
line 94~ This signal couples directly to the gate 92B and also
by way of the nverter 87 Jo the gate 32A. When external
graphics is being enabled the character code bit from gate 83
are essentially overlayed by means of an input graphic control
signal referred to as the signal ENGRAF. When this is present,
the gate 92~ is enabled instead of the gate 92A and as long as
the signal GRAEVI~ is present, then there may be a low signal
on line 93 or providing inversion. This type of control is
possible on a character-by-character basis or bit-by-bit
(cell-by-cell) basis.
There are also provided, two other gates identified as OR
gate 96 having inverted inputs and AND gate 98. Vne input to
the gate 96 is the data line D7. The other input to the gate
96 is the signal ENALTSET on line 99. When this signal on line
99 is present, this signals the generation of an alternate
character set from the character generator ROM. The alternate
character set provides additional characters above the normal
haracters that are used. In this connection, when the inverse
video signal is high, bits 0-127 represent normal characters,
and bits 128-255 represent inverse video characters If the
inverse video signal is low and the alternate set signal is
low, then bits 0-127 are normal characters, bits 128-191 are
graphics and bits 192-255 represent a kana character set. If
the inverse video signal is low and the alternate character set
signal is high, then blts 0-127 are normal characters, bits
128-191 are graphics and bits 192-255 are alternate set
characters.
When the signal on line 99 is absent, because an alternate
set is not being enabled, then the output of gate 96 is high
and this enables the gate 98 The gate 98 is enabled
regardless of the state of the signal on the line 97 which is
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39~3
the date line D7. Thus, for normal character generation, the
data bit D6 simply passes without inversion through the gate 98
to the corresponding ~6 input of the character generator ROM 50.
When the signal on line 99 goes high to indicate an
alternate set, then the control of the gate 96 is primarily
from the line 97. If the date line D7 is high, then the output
of gate 98 is low and thus the data bit D6 to the character
generator is low. Vn the other hand, if the date bit D7 is
low, then the data bit D6 from the output video latch simply
goes directly by way of the gate 98 to the D6 input of the
character generator ROM 50. Thus, for alternate set operation,
the outcome is that the higher order data bits are presented to
the character generator ROM 50 for display of what may be
termed special characters.
Reference is now made to FIG. 6 which shows the generation
of timing signals in connection with timing for memory access
in connection wlth the microcomputer system. The timing
control snown in FIG. 16 includes the generation of timing
signals for the random access memory of FIG. 3 as well as
timing signals for the video RAM. In this connection,
reference is made to FIG. 3 which shows the main memory 10 and
the video ram 34.
In FIG. 6 the siynals that have to do with the timing for
the random access memory include the signals SMUX-, RAS-, and
ICAS-. The timing signals that relate to the video RAM include
the signals PWAIT-, OE-, WID-, VBON-, and LATCH DAT-.
FIG. 6 also shows the number of input signals, many of
which originate from the central processing unit, which in the
preferred embodiment, is a type Z80 processor. Also shown in
FIG. 6 is part of the circuitry of FIG. 3 shown in block form.
This part includes the multiplexer 36 and the video RAM 34. It
is the signal identified in FIG. 6 as the signal WID- that is
coupled to pin 11 of the multiplexer 36. This is a window
signal for providing a window for writing to the the video RAM.
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39~3
Read and write signals are coupled directly from the Z80
processor and are identified in FIG. 6 as signals ZWR- and
ZRD-. These two signals couple to the gate 110. The output of
the gate 110 couples to the data input of the flip-flop 114.
The clocking of the flip-flop 114 is from the signal XADR7-.
This signal is basically an inversion of the signal CRT CLK
shown and discussed in connection with FIG. 3. The clearing of
flip-flop 114 is from the signal VIDEO- by way of the inverter
gate 116. The signal VIDEO- also couples to one input of the
gate 118 tO assert RWAIT-. The assertion output of the
flip-flop 114 couples to the other input of tne gate 1180 The
setting of the flip-flop 114 indicates video access in
progress. wince it is known that the video access is now in
progress, the signal PWAIT- is released. The output of
flip~flop 114 also enables gate 124 and by way of gate 122
starts the timing of the delay line 120. The setting of
flip-flop 114 occurs upon either a read or write signal from
the central processing unit passing by way of the gate 110 with
a high level signal at the output thereof for presentation to
the flip-flop 114.
The output signal from gate llB is the signal PWAIT- which
couples back to the central processing unit. This signal
unctions as a wait line for the Z80 processor. This action is
utilized by the Z80 processor to synchronize to asynchronous
signals.
FIG. 6 also shows a delay line 120 which has an input from
the NOR gate 122. One input to the gate 122 is the output of
flip-flop 114 and the others to the gate 122 is the signal
MCYCEN which is a memory cycle enable signal. This is
generated througn logic from the central processing unit and is
for enabling the memory cycle. The delay line 120 has a series
of taps that provide for different timing functions with
different predetermined delays used to carry out controls of
the signals particularly for control of the random access
.
-lB-
memory 10 and the video RAM 34 shown in FIG. 3.
The gate 118 which generates the signal PWAIT- is connected
so that the signal is present when the signal VIDEO- occurs but
terminates upon the setting of the flip-flop 114. It is noted
that the output of the flip-flop 114 also connects to the gate
124. The gate 124 is instrumental in control of the video
window. While the output of gate 124 is high, the output at
inverter 126 is low and this provides one input enable to the
gate 128. The other input to the gate 128 is the signal MWR-.
If the system is in a write cycle, then the gate 128 is enabled
and has a low output. This in turn enables gate 130. This is
the signal that is coupled to the multiplexer 36.
The access in progress signal on line 115, as mentioned
previously, has a line that couples to the NOR gate 122. The
output of the NOR gate 122 couples to the delay line 120. This
access in progress signal on line 115 essentially starts the
delay line 120 and upon receipt of a low going signal at the
pin 12 of the delay 120, the gate 130 is enabled. The
dispersed output of the delay line 120 is a 30 nanosecond tap.
Thus, tne first tap of the delay line essentially starts the
video window at the gate 13~. This signal identified as the
signal SMUX- also couples to gate 136 and provides the video
buffer on signal identified as signal VBON-. This is for
enabling the video buffer 46, as nod in FIG. 3. This occurs
when the signal We- is low.
The second signal from the delay line at tap 60 is a signal
ICAS-. The delayed pulse travels down the delay line to the
third tap which is tap 150 which couples to a second input of
the AND gate 124. When the signal at pin 10 goes low this
essentially ends the video window. This low signal provides a
high output to pin 4 of gate 130, thus terminating the window
signal with the signal WID- going high. This brings the signal
WE- high and concludes the right cycle to the video ram. This
also disables the signal VBON- which in turn turns off the
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video buffer 46.
With ~onclusi~n of the write cycle there is still a pulse
progressing down the delay line 120. One can now assume that
there is a read sequence. At the commencement thereof the
signal OE- is still low and thus the video RAM 34 is not
enabled. At the 24~ tap at pin 6 of the delay line there is
then provided the signal LATCH DAT-. This low signal as
indicated in FIG 3 couples to the line 45 thereby latching
data from the video data bus 42 to the data bus 18~ This is
for reading data from the video data RAM to the CPU. The data
is held in the latch 44 until the signal VIDEO- terminates. It
is noted that this action by way of the inverter 116 clears the
flip-flop 114 and in turn resets the circuit for further
operation.
In FIG. 6 the signal MWR- as mentioned previously is
instrumental in not only control of the gate 128 but also in
generating of the signal OE- which is the output enable signal
for the video RAM 34. In this connection the gate set 134 also
receives the signal CUT CLK and the output therefrom is the
aforementioned signal OE-. The signal CRT CLK is an
alternating signal and depending upon the state thereof, there
is essentially an interlacing between control from the cathode
ray tube controller (C~TC) 30 or the address lines from the
central processlng unit (CPU~. When the signal CRT CLK is
high, then the multiplexers 36, 38, and 40 provide control from
the C~TC 30. The address lines are presented from the cathode
ray tube controller 30 and the write enable input to the video
RAM is held enabled. The signal OE- is also at a state that
provides an output enabling of the video RAM In fact, the
output of the gate set 134 has only one condition that brings
its output high and that is when the signal CXT CLK is low and
duriny a write cycle as controlled by the signal MWR-. Thus,
during a CPU write cycle, a window is established by the signal
WID- and data is written by way of the video data write buffer
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' ~LZ;2~3~343
46 into the video RAM 34.
FOG. 6 also shows additional logic control such as the gate
136 which is used for generating the signal VBON-. As
indicated previously, this signal is used in the control of the
video data write buffer 46. There is also provided a second
gate set 13~ that generates at its output the signal RAS-.
This signal is used in connection with control of the random
access memory shown in FIG. 1. The inputs to the gate set 138
are from the tap 300 delay line 120 and also frown the signal
PRECHG coupled by way of the inverter 139. The other input
signal to this gate set is the Z80 signal for a memory request,
namely signal MR~Q. It is noted that the delay line 120 also
generates on a properly timed basis, the signal ICAS- and the
signal SMUX- for the dynamic RAM timing.
FIG. 6 also shows the generation of the signal WAIT- from
the flip-flop 140. This signal is coupled to the central
processing unit and is another one of the WAIT functions for
the control of the Z80 processor.
With regard to the control in accordance with the present
invention, reference is rnade to FIG 3 and the video RAM 34 and
also to the cathode ray tube controller 30. The central
processing unit address lines couple to the three multiplexers
36, 38, and 40. l'he control input to each of these
multiplexers is at the input pin 1. This control is the signal
CRT CLK. This is an alternating signal which, it is noted, is
also coupled to the cathode ray tube controller 30. This is
the basic clock for the controller 30 for screen refresh but
also functions to permit reading from and writing into the
video RAM under CPU control.
Thus, when the signal CRT CLK is hign, this conditions the
multiplexers 36, 38, and 40 to bring addresses directly prom
the cathode ray tube controller 30. These are shown in FIG. 3
as the Bl-B4 addresses which couple to the output line Yl-Y4.
This control is for refreshing of the display. Thus, during
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c:
~22~g~3
this state of the signal CRT CLK, the video RAM data is read
out into the video output latch 48 and to the character
generator ROM 50. The latch 48 latches this data on its
portion of the CRT CLK signal or in other words when this
signal is high. This provides for a refreshing of the screen
and yet, as described hereinafter, data transfer is capable of
occurring between the CPU and the video RAM in an interlaced
manner on the alterate cycle of the CRT CLK signal so as to
enable updating.
Now, when the signal CRT CLK goes to its low state, it is
during this low condition that data can be read from the video
RAM to the CPU and data can also be written into the video RAM
from the CPU. In this regard, the video data read latch 44 and
the video data write buffer 46 are used in this control. When
the signal CRT CLK goes low then the control of the
multiplexers 36, 38, and 40 changes so that the addresses Al-A4
couple to the outputs Yl-Y4. These addresses couple directly
from the CPU address bus with the exception of one of the
inputs which is the signal WID- which connects by way of the
multiplexer 36 to the input We- of the video RAM. During this
phase of operation this is where the signals VBON- and LATCH
DAT- previously referred to in connection with FIG. 6 are
instrumental in providing data transfer either on a READ
sequence or a WRITE sequence.
If one first assumes that the control is such that it is a
write cycle, then the signal VBON- enables the video data write
buffer and data is written into the video RAM. Under this
condition, the signal OE- is high and thus the output of the
video RAM is disabled because it is being written into. This
control is provided by way of the gate set 134 of FIG. 6.
In the sequence of operation, one can then assume that the
signal CRT CLK then reverts to its high level and the addresses
to the video RAM then switch again to the cathode ray tube
controller 30. Tnere is thus a continuous refreshing of the
c"
~L2~28943
video RAM data under control of the CRY CLK. When the signal
then reveLts again to its low stave, during a subsequent read
cycle, the video data write buffer 46 is disabled and the video
data read latch 44 is enabled. Data may then be read from the
video data bus 42 by way of the video read watch 44 to the CPU
data bus.
Thus, there is provided for a read and write sequence with
regard to the video JAM, not durlng any blanking sequence, but
actually interleaved with the video All refreshing cycle.
There is also described herein tables showing the design
for a number of PAL's used in the micro computer system along
with mapping equations.
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