Note : Les descriptions sont présentées dans la langue officielle dans laquelle elles ont été soumises.
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A FIELD ~FFECT TRANSISTOR
CURRENT SO~RCE
~ ion
1. Pield of the Invention
The present invention relates to a technique
for implementing a current source in field effect
transistor technology.
2. Description of the Prior Art
Most linear circuits are biased by means of a
current source. It is usually thought desirable that this
source provide a current that is independent of
temperature, power supply, and process variations. One
current source in common use takes advantage of the
logarithmic insensitivity of a bipolar transistor's forward
base-emitter voltage, VBE, to power supply and process
variations. A resistor placed across the emitter-base
junction of an active transistor will give a reference
current equal to VBE/R~ CMOS (Complementary Metal-Oxide-
Semiconductor) integrated circuits have also used thistechniaue by taking advantage of the intrinsic bipolar
transistor in the CMOS structure. unfortunateIy, this
current source has a large temperature dependence, since
VBE has an intrinsic negative temperature coefficient of
approximately -2 mv/degree C, and the resist~r has a
positive temperature coefficient. ~lence, the current from
this source has a large negative temperature coefficient.
A great deal of work has been done on circuits
that provide a constant reference voltage, but relatively
less on the apparently similar job of producing a constant
reference current. In the case of ield effect transistor
(FET) current sources, steps are frequently taken to
mitigate the effects of large lot-to-lot variations in
device parameters, for which field effect transistors are
notorious. In particular, circuits are usually designed to
minimize the effects of threshold and gain variations that
occur for field efect transistors on different wafers.
.
~6~
~æ~ 3
For example, a resistor is typically included in the
source path of a FET to provide degenerative feedback,
which reduces these variations.
Summary of the Invention
In accordance with an aspect of the invention
there is provided an integrated circuit comprisiny a
current source adapted to provide a controlled current to
at least one device, characterized in that said current
source comprises a reference field effect transistor
having a gate electrode connected to a source electrode
thereof by means of a reference resistor, means for causing
a reference current to flow through said reference resistor
in the direction that tends to promote the ~low of channel
current in said reference transistor, means for causing
said channel current and said reference current to be
proportional, and means for causing said controlled
current to be proportional to said reference current.
~ e have invented a technique for implementing a
constant current source using a field effect transistor.
In this technique, a reference field effect transistor
has a resistor connected between the gate and source
electrodes. Means are included to cause a reference
current to flow in the reference resistor, and be
proportional with the channel current of the reference
transistorO The reference current can be made to have a
positive, negative~ or zero temperature coeficient. When
utilized with analog or digital field ef~ect transistor
circuitry implemented on the same semiconductor su~strate,
the reference circuit also compensates for processing
variations. In a preferred embodiment, the field effect
transistor is an enhancement mode type.
Brief Descri~ion of the Drawings
FIG. 1 illustrates a field effect transistor
current source reference circuit according to the present
invention.
.~
~ 2
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FIG. 2 illustrates a first circuit for
implementing the present invention.
FIG. 3 illustrates a second circuit for
implementing the present invention.
FIGS. 4 and 5 show controlled transistors for
implementing current sources relative to positive and
negative voltage terminals, respectively.
FIGS. 6 and 7 illustrate a prior art current
source reference resistor.
FIGS. 8, 9 and 10 illustrate an inventive current
source reference resistor.
FIG. 11 illustrates the effect of process
variations on current source output for reference resistors
of differing widths for the resistor type shown in
~ e `',~. ~
:
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FIGS. 8-10.
1~ t~ D~ n
The following description relates to a circuit
which can provide a temperature and power supply
independent currrent, and in a pre~erred embodiment
actively compensates for inherent process variations. This
results in a smaller spread of linear circuit parameters,
such as operational amplifier slew rate, gain, and gain-
bandwidth, than can be obtained with an "ideal" current
source. The present technique results in part from a
recognition that positive and negative temperature
coefficient terms can be balanced to a desired degree in a
FET, to obtain a desired temperature coefficient. The
present invention also provides that the current source FET
1S may be fabricated by the same fabrication process (e.g~, on
the same semiconductor substrate) as the circuits utilizing
the controlled current. Then, process variations produce
changes in the current source FET that offset changes in
performance parameters (e.g., gain, slew rate, etc.) in
the controlled circuit. By this technique, a FET is
utilized to good advantage as a current source.
The basic ~ore of the source is shown in FIG. 1,
wherein a field effect transistor has a reference resistor
(R) connected between the gate and the source. The field
2S effect transistor is typically an insulated gate type
(i.e., an IGFET), which may be a metal-oxide-silicon fiel~
effect transistor (MOSFET) type. In the saturation region,
the current through the channel of the IGFET is:
I = l/2 ~ (VGS-Vt)2 (1)
where ~ is the gain, and Vt is the threshold voltage, of
the IGFET. For a MOSFET, the gain (~) may be approximated
as ~ = (Z/L) ~ Cox, wherein æ is the width of ~he channel,
L is the length of the channel, ~ is the mobility of
majority carriers in the channel, and Cox is the gate
capacitance per unit area. The value of Cox can be
calculated as: The permittivity of free space times the
dielectric constant of the gate insulator (about 3.85 for
an oxide) divided by the thickness of the gate insulator.
Equation (1) may be solved Eor VG5:
VGS = (2I/~ Vt. (2)
For a constant channel current I, the temperature
coefficient of VGS is the sum of two terms. The first
involves ~, whose temperature dependence arises from that
of the mobility of the majority carriers flowing in the
channel between the source and the drain. The mobility
(~) is limited by lattice scattering, which has a
temperature dependence of:
~ = ~ (T/TO) 3/2 (3)
where ~O is the mobility at temperature To. Typical
20 values of ~O range from 520 to 775 cm2/volt-sec for n-
channel FET's, and from 185-240 cm2/volt-sec for p-
channel FET's, at To = 20C. In practice, surface
scattering changes the exponent somewhat from its
theoretical value of 3/2.
The threshold voltage (Vt) has an intrinsic
negative temperature coefficient that depends only weakly
on process parameters. For a typical Complementary MOS
(CMOS) technology based upon 3-5 micrometer design rules,
this value is -2.3 mv/degree C. Equation (2) can now be
written as:
VGS = Vt ~ (2I/~o)1/2(T/To)3/4. (4)
.
'5
Note that ~0 is the gain at temperature To. It is no~
apparent that VGS is the sum o~ t~70 terms with opposing
temperature coefficients; that o~ ~o being positive, and ~t
being negative. In addition, the magnitude of the second
term in Equation (4) depends on the channel current, so
that the total temperature coefficient of VGS can easily be
adjusted. (A complete analytical treatment is included in
the Appendix.) Since the reference current IR = VGS/R,
it is apparent that the desired te~perature coefficient of
the reference current can be obtained by choosing one or
more of: the threshold voltage (Vt), the channel current
(I), and the gain (~). The gain in turn can be set
according to considerations known in the art, inçluding,
for example, the approximation given above.
The ability of this source to compensate for
process variations is also shown in Equation 4. A "fast"
(e.g., relatively thin gate oxide and short channel length)
process will have a large ~, and thus a small value of VGS.
The reference current (IR) is equal to VGS/R, so it will
decrease. A "slow" (e.g., relatively thick gate oxide and
long channel length) process with a small ~ will have a
larger VGS, and thus a larger reference current. In terms
of the physical process, a fast process usually results
from relatively more etching of the gate material, which
reduces its length relatively more than its width. Hence,
when the channel is formed, the ratio Z/L is increased.
The opposite is true for a slow process. Other factors may
also be involved, such as semiconductor junction depths,
gate insulator thicknesses, doping levels, etc.
A simple circuit that uses the VGS/R concept to
generate a constant current is shown in FIG. 2. To obtain
a desired temperature coefEicient (TC)~ the channel current
through the re~erence transistor ~M3) should be held
proportional to the reference current (IR). For this
purpose, transistor M1 mirrors the channel current in M5,
which is connected as a diode. ~ote that ~S also causes
~;i 2
-- 6 --
the reference current IR to flo~7 through R1. ~lence, IR
is identical to the channel current flowiny through ~5. If
a current I is flowing in ~1 and M5, then current 2I is
mirrored in M4, which is twice the size of M2. The channel
current in reference transistor M3 is equal to that in ~4
minus that delivered by M5. The ~inal result is that a
current I flows through all the transistors except M4,
which has a current of 2I. Since the channel current
through M3 is forced to be equal to the reference current
in R1, a stable feedback loop is formed. Thus the current
mirrors are means for causing the channel current (I) in
the reference transistor (M3) and the reference current
(IR) through the reference resistor (R1) to be
proportional. In general, these currents need not be
e~ual, but merely proportional. Thus, I > IR, I = IR,
and I < IR are all possible design variations.
Two output bias voltages are available from this
circuit. The bias-out positive (BOP) provides a voltage to
the gate of one or more P-channel current output
transistors M50; see FIGo 4~ The output current,
IoUt is proportional to the reference current, IR.
The proportionality constant depends upon the size of M50
as compared to M5 of FIG~ 2 (or as cornpared to M48 of
FIG~ 3 ~ ) A corresponding bias-out negative (BON) can be
supplied to one or more N-channel current output
transistors M60; see FIG. 5. However, the circuit of
FIG. 2 has two stable current states, one of them I = 0.
Hence it is desirable to include means to prevent the
circuit from reaching the I = 0 state.
A more typical circuit employing the inventive
concept is shown in FIG~ 3. The widths and lengths of the
transistor channels, in micrometers, is given as W/L ~or
each associated transistor. Transistor M410 and its bias
resistors are included to provide proper start-up
conditions; i.e., prevent I = 0. For this purpose, M410 is
sized to draw a small current, typically less than 0.1% of
the current through re~erence resistor R1, which is set at
..
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a nominal value of 100~a. M410 and its bias resistors can
be replaced by a depletion transistor. The other
additional transistors are optionally included to impro~e
power supply rejection by cascadiny all of the mirrors, and
to mirror the current to ~413, which actually drives the
negative bias output (BON). A positive bias output (BOP)
is provided from the drain of ~48.
The reference resistor R1 can be of any type that
gives a positive temperature coefficient of resistance. It
is advantageously made with a P~ diffusion, which has a
much lower TCR (temperature coeficient of resistivity) and
VCR (voltage coefficient of resistivity) than the P-tu~.
The absolute control of the P~ sheet resistance is also
very good, typically within plus or minus 15% o~ the
nominal value. R1 can alternately be made of polysilicon
or other materialO The sizes of ~1 and reference
transistor M45 are typically set to give a zero TCC
(temperature coefficient of current) in M~13 and M48 at
nominal conditions. The resistance of the reference
resistor (~1) is typically greater than 100 ohms, and
typically less than 10 megaohms, although a wider range is
possible3 The size of the reference transistor (M45) is
desirably chosen so that the channel length (L) is large
enough to minimize processing variations. A length of
about 8 to 10 micrometers is suitable for typical
processing conditions. Then, the gain may be set by
choosing the width, Z, to give the desired temperature
coefficient. One methodology or obtaining the desired
temperature coefficient of the current from the source is
as follows:
1. Determine the temperature coefficient of the
reference resistor (e.g., by measurement or estimates based
on material type).
2. Choose a desired reference current (e.g.,
IR Y 100 microamps) and a desired proportionality between
channel current in the reference transistor to the
reference current (e~g., I/I~ = 1).
~ 3~
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3. Estimate the approximate size of the reference
transistor (e.g., W = 50 Inicrometers, L 3 10 micrometers)~
4. Determine Vt and ~ for the reference
transistor thus selected.
5. Determine VGS for the re~erence transistor, as
from equation (2) (e.g., VGS = 1.7 volts).
6. Set reference resistor R = VGS/IR (e-g- r
1.7/100x10 6 = 17K).
7. Calculate the temperature coefficient of the
reference current: (i.e., IR = VGS/R) from 1 above and
equation (2).
8. If the IR temperature coefficient is not
within desired limits, change a variable reflected in
equation (2), and repeat steps 3-7 until desired value
obtained (e.g., decrease size of reference transistor to
W = 40 micrometers L = 10 micrometers, which reduces the
value of ~, and increases VGS to 1.815 volts, so that
R = 18.15K, which produces approximately zero ~.C. for
IR)o
Note that a positive, zero, or negative T.C. for
IR can be thus obtained. Other methodologies are also
possible.
Note that in FIG. 3, the reference transistor M45
as shown is in its own P-tub, with the back-gate bias,
VBX=0. This is desirable to minimize power supply induced
variations on the back gate. For this reason, the circuit
performance is typically better in CMOS than it would be in
NMOS. If a CMOS technology using isolated N-tubs were
used, the entire circuit would simply be "flipped" over
vertically, and M45 would be a P channel device in an
isolated N-tub. However, the present technique can also be
usefully implemented in NMOS (or PM~S) technology, when
isolated tubs are not available. In that case, the back-
gate of the current control transistor is then connected to
the se~niconductor substrate, which is connected to the
negative (N-channel) or positive (P-channel) power supply
terminal.
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To compare the present technique wikh prior art
techniques, computer simulations were done on four
different current sources. The norninal current at 25~C was
set at 100~a for all four sources. The effect of
temperature on these sources, as well as process variations
for both low speed (worst-case slow) and high speed (worst-
case fast) conditions, were investigated. rrhe four sources
were as follows:
Source A 100~a ideal source
Source B Band-gap source, I=VBG/~,
VBG=1.2 volts
Source C VBE/R source
~ource D VGS/R source (FIG. 3)
In sources B-D, the resistor ~ was assumed to be
made with P+ diffusion, and to have a plus or minus 15%
maximum variation with processing.
Varying the temperature frorn 0 to 100C showed
that the VBE/R source has by far the largest temperature
variation. However, the band-gap source (B) also has an
appreciable TCC due to the finite TCR of the resistor. The
self-compensating feature of the VGS/R source was apparent.
At 25~, the low speed process gives 35% higher current, and
the high speed process 30% lower current than nominal.
Both cases show a larger TCC than e~ists with the nominal
process, but no worse than that of the band-gap source
(B).
The effect of the different current sources on the
performance of a typical operational amplifier (op-amp) has
also been investigated. The op-amp used in these
simulations was a simple two stage design. There are two
independent effects of temperature on op-amp performance.
The first is the intrinsic effect of temperature on the op
amp, independent of current. The second is the effect of
current variations due to the temperature ~ of the
current source. The ideal current source ~A) is used in
_
these simulations to separate these two effects. The slew
rate, gain-bandwidth product (GBW), and gain, as a
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function of temperature, were investigated for nominal
processing at a constant current of 100~a.
The effect of current variation on these same
parameters was also investigated for "~70rst case (~-C)
fast" and "worst case (W-C) slow" conditions, as follows:
Condition Tr~nsiators Resistors Tem ~ ure
W-C Fast Fast 15% Low O Degrees C
W-C Slow Slow 15~ High 100 Degrees C
The minimum and maximum values, and the total
spread expressed as a ~ of the median value of the three
parameters, are summed up in Table I.
TABLE I
Maximum, minimum, and total spread of slew rate, GBW, and
gain of an op-amp under worst case fast and worst-case slow
conditions:
CURRENTSLEW RATE GBW
SOURCE(v/us) (MHz)
Min. Max. Spread Min. Max. Spread
(%) (%)
.~ _______ _________ _
A. Constant 10.3 13.5 27 3.83 6.95 58
B. Band-Gap 3.2 15.5 49 3.58 7.36 69
C. VBE/R 7.5 16.1 73 3.52 7.63 73
25 D. VGS/R 11.6 12.8 10 4.08 6.66 48
CURRENT GAIN
SOURCE (dB)
Min. Max. Spread
3~ (%)
__ ______ ~
A. Constant 63.6 70.5 10.4
B. Band-Gap 63.1 71.3 12.1
C. VBE/R 62.7 72.3 14.3
35 D. VGS/R 63.9 69.6 8.6
,
,
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33. 7
The performance improve~ent is rnost noticeable in
those parameters which have the strongest deperldence on
current, but in all cases the VGS/R source results in a
higher mlnumum value and a lower maximum value. Some
insight as to the relative efforts of temperature and
process variations can be gained by independently varyiny
these inputs while keeping the reference current set at
100~a. The results are shown in Table II. Both the slew
rate and gain are more strongly effected by the process
variations than by temperature, while the GBW is e~ually
effected.
TABLE II
Total variations in op-amp performance due to (1) a 100C
temperature variations, and (2) the difference between
"fast" and "slow" transistor processing, with the reference
current held at 100~a:
VARIATION DUE TO VARIATION DUE TO
20 PARAMETER TEMPERATURE (%) PROCESSING (~)
Slew Rate 7.~ 15.5
Gain 1.3 13.8
GBW 27~0 28.0
Among the other parameters of interest in op-amps
and other linear circuits are power supply rejection ratio
(PSRR?, common mode rejection ratio (CMRR), and common
mode range. Computer simulations show that the inventive
supply is slightly better than the others in both PSRR and
CMRR. The common mode range, however, is somewhat worse.
This is due to exactly the self-compensating feature that
improves the other parameters. The smallest common mode
range exists when the translstors are slow and the current
is high. In other current sources there is no connection
between these two; even when the worst-case assumption of
high current is made, it is not as high as it is in the
self-compensating source. For the op amp used here, this
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results in a worse-case loss of 500mv of input range. This
op-amp was not designed to glve a particularly large common
mode range, and the loss would be proportionally less on
op-amps with larger Z/L ratios on ~he input transistors.
All of the discussion and results up to t'nis point
has assumed that the value of the reference resistor R1 in
the inventive current source is independent of the
transistor process. This is a good assumption for
resistors made in the usual manner, as shown in FIGS. 6 and
7. In this technique, an opening etched in the field oxide
allows the resistor to be formed by doping ~as by ion
implantation) the semiconductor in the region thus defined.
For the resistor shown in FIG. 6, the total resistance is:
R = Rs (L/W) (5)
where Rs is the sheet resistance of the doped
semiconductor, and L and ~ are the length and width of the
field oxide defined opening. An insulating layer (e.g., a
glass), is typically deposited over the resistor, with
contact windows then etched therethrough.
Another way to define the resistor is shown in
FIGS. 8 and 9. In this case, the polysilicon (poly) level
is used instead oE the field oxide to define the feature
size. The poly line size is one of the most crLtical and
well controlled parameters in the process, and in self-
aligned silicon gate technology, the polysilicon layer
defines the gate electrode size. Hence, the poly line size
will often determine whether any given wafer is "slow" or
"fast". For this reason, a resistor defined by the layer
that defines the gate electrode can have a tighter design
tolerance than one defined by the field oxide. Let us
assume that the actual poly line size differs from the
nominal size by an amount DL. A positive DL means wider
poly and a slower process, negative ~L means narrow poly
and a fast process. AS shown in FIG. 11, the resistor
width is W - ~L, so that :
: ~ ,
:,
~. :
~2~
R = Rs (L/W DI.) (6,
A positive DL (slow process) causes the resistor
to increase, and the negative DL (fast process) causes it
to decrease from the design value. This will oppose the
"self-compensation" feature of the VGS/R source, since
process induced changes in VGS will now be tracked by a
similar change in R. The relative value of these two
quantities depends on the resistor's nominal width. For an
extremely wide resistor, R does not depend on DL at all.
AS the resistor width decreases, the effect of DL becomes
larger. Note that other self-aligne3 gate electrode
materials (e.g., a refractory metal or metal silicide) can
be used to define the resistor, to achieve this effect.
The current I = VGS/R for three different resistor
widths is shown in FIG. 11. It was calculated using the
40/10 N-channel transistor M45 in FIG. 3 and nominal
process conditions. The case of infinite resistor width
corresponds to the case discussed above. At 7 microns the
current is nearly independent of poly line size, and at 4
microns the process compensation is actually the reverse of
that discussed above.
The circuit shown in FIG. 3 has been implemented
in a typical 3.5 micron Twin-Tub CMOS process on a n-type
substrate on a lot in which the poly width was
intentionally varied. The resistor ~1 was poly defined,
with a nominal width of 4 microns. The current vs.
temperature curves for three different wafers were
determined. The sheet resistance of the P+ diffusion, was
measured at 10 percent below the nominal ~alue for this
lot. This accounts for most of the difference between the
measured current of 107~a and the design value of 100~a Eor
the nominal poly. For a wafer with a measur~d DL=+0.44~m,
the current calculated from FIG. 11 was 87~ of the nominal
value, and the measured current was 84% of the nominal.
For a wafer with a measured DLa 0.22~m, the calculated
current was 105$ nominal, and the measured current was 114
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of the nominal. For the nominal poly, the maximum
variation o~ current over the temperature range
10C - 120C was 2 1~. From 25C - 120UC i~ is 1.5%. Both
the narrow and wide poly had similar temperature variations
of their current.
The foregoing has sho~m that in the present
technique the temperature coefficient of current can be
selected to be either zero (nominally, as second order
effects give a slight curvature), positive, or negative.
If a zero temperature coefficient of current is desired,
the resulting controlled current can be readily maintained
within +5 percent, and typically within ~2 percent, of the
average value, over a temperature range of from 0C to
100C, or even wider. These values are even more readily
obtained over a typical commercial te~nperature range of
from QnC to 70C. The current source automatically
compensates for variations in the transistor process, with
a "fast" process giving lower current and a "slow" one
giving a higher current. If desired, this compensation can
be reduced or eliminated with respect to variations in the
polysilicon line width size by proper resistor designO
While the above example has been for an enhancement mode
MOSFET, similar considerations apply for depletion mode
devices, including junction field effect transistors, and
Shottky gate field effect transistors (e.g., MESFETS)
implemented in gallium arsenide or other III-V materials.
Ho~ever, one advantage of the present technique is
that it does allow the use of enhancement mode FET' s; i.e.,
those having a threshold voltage, Vt, that is >0 Eor an n-
channel device, and Vt ~ 0 for a p-channel device, Note
that these voltages are measured at the gate in reference
to the source; i.e., VGS. Enhancement mode field effect
transistors are typically of the insulated gate ( I~FET)
type, of which MOSFET' s are an example. Their use is
advantageous because a smaller channel current can then
typically be utilized in the reference transistor than if
a depletion-mode device ~ere used. This is because in the
~':
2~
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present technique, the reference current is directed
through the reference resistor in the direction that causes
the channel current in the reference transistor to Flo~7 (or
to increase its flow), as the reference current increases.
That is, VGS is generated in the direction of forward bias
by the reference current. Hence, the power dissipation can
be less with enhancement mode FET's. Furthermore,
enhancement mode field effect transistors are usually
available on an integrated circuit using fewer process
steps than depletion mode devices require. A depletion
mode device may be used, however, by operating it in the
enhancement mode; i.e., where the channel current is
greater in magnitude than the channel current for VGS = 0.
Note that the means for causing the channel current and the
reference current to be proportional (e.g., a current
mirror) inherently produces the desired direction of
reference current flow. This is in contrast with the prior
art techni~ue of biasing a current source FET using
degenerativ~ feedback by placing a resistor in the source
path. In that case, an increase in the current through the
resistor causes a change in VGS in the direction that tends
to decrease the channel current of the E'ET.
While the present invention may be used in analog
integrated circuits, it may also be used in digital
integrated circuits. For example, in certain random access
memory designs, i~ is known to use a current source for the
sense amplifiers, for improved speed and sensitivity. In
addition, the use of a controlled current source is known
for use with digital logic circuits to reduce chip-to-chip
performance variations. In the past, the current source
associa~ed with the logic gates has been controlled using a
reference clock and comparator circuitry; see "Delay
Regulation - A Circuit Solution to the Power/Per~ormance
Tradeoff", E. Berndlmaier et al, IBM Journal of Rese_rch
~5 and Development, Vol. 25, pp. 135-141 (1981). The present
invention can advantageously be implemented on the same
chip or wafer as the logic gates to perform this function.
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Since processing conditions are similar for all circui~cs on
a given semiconductor wafer, the presen~ technique lends
itself to wafer scale integration uses. If desired, a
single bias circuit (e.g., FIG. 3) can provide control of a
plurality of current output transistors (FIGS. 4, 5)
located at various places on a chip or wa~er. The tenn
"integrated circuit" as used herein includes both
utilizations. The controlled current from the present
source can be used to produce a controlle~ voltage, as by
passing it through a resistor having a given temperature
coefficient, or through a resistor-diode combination; i.e.,
a band-gap reference, etc. The characteristics of a band-
gap reference are described in "New Developments in IC
Voltage Regulators", R. J. Widlar, IEEE Journal of Solid
State Circuits, Vol. SC-6, pp. 2~7 (1971). Since the
controlled current can have a desired temperature
coefficient chosen over a wide range, the resulting voltage
can be used for a variety of purposes. Also, the device
receiving the controlled current may be formed on a
different substrate from the current source. For example,
an optical emitter (e.g., light emitting diode or laser
diode) can be driven by current supplied from the present
source and adjusted so that IR has a positive T~C., to
compensate for the reduction in optical output from the
source with increasing temperature. Still other
applications will be apparent to a person of skill in the
art.
APPENDIX
Referring to the current source shown in FIG. 2;
define a reference current I~ as the current through R1,
IDS3 as the current through M3 with gate to source voltage
VGS3, and KIR as the current through M4, where K is the
feedback constant determined by the relative sizes of M1,
M2, M4, and M5. The value of K shown in FIG. 2 is two, but
it may be any value consistent with stability. Summing the
currents at the drain of M4 gives:
3S
- 17 -
IDS3 = (K-1) IR- (1A)
However:
IR= VGS3 = 1 ¦ 2IDS3 ¦ 1/2 ~ t . (2A)
Substituting (1A~ into (2A) and rearranging giveso
I 1 ¦ 2(K~ 1/2 (I ) 1/2 _ Vt = 0 (3A)
which is quadratic in (IR)1/2. Solving gives:
(I )1/2 = 1 ¦ ~ ¦ 1/2
2 ¦ R1 21 ~ (K~ Vt 1 1/2 (4A)
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Squaring and rearranging gives:
IR Vt ~ 1 + ~ 1 ~ VtR1B ~ ~ (5A)
As can be seen in (5A), there are two real solutions;
however, the solution with the negative sign in the bracket
is a class of solutions for VGS2 < Vt, or zero current
through M3. These solutions correspond to loss of
regulation in the source.
For R1~/(K-1) 1, Equation ~5A) reduces to:
R t/ (6A)
Which has an inherent negative temperature coefficient.
For R1~/(K-1) 1, Equation (5A) reduces to:
IR # 2 (K-1)/R1
which has an inherent positive temperature coefficient.
Even though 1/R12 has negative temperature behavior, it
is outweighed by 1/~ which goes as T3/2.
It can also be shown that if at 25C, R1~/(K-1)#2, then
~T ¦ 25 C # (78A)
33~
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and that IR at this value of R1~/(K-1) varies slowly with
temperature.
The temperature behavior of this current source
can be varied negative or positive, or made essentially
zero, by proper choices of value o~ the reference resistor,
R1, the size of transistor M3, and the value of the feedbac
constant Ko Note that these factors influence the channel k
current through the reference transistor, as indicated by
(1A).
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