Note : Les descriptions sont présentées dans la langue officielle dans laquelle elles ont été soumises.
3L~5~i71 66~2-225l~
BACKGROUND OF THE INVENTIQN
This application is a division o~ our Canadian
application Serial Number 522,305, filed November 6, 1986.
This invention relates to test systems for complex
VLSI (Very Large Scale Integrated) circuit chips found in the
state of the art digital electronics system. In particular,
this invention relates to special test and diagnostic circuitry
that resides on or is imbedded in a VLSI chip together with the
circuitry which performs the specified chip function. This
test and diagnostic circuitry may be used for initial testing
of the chip or testing at any time during the useful life of
the chip and may include testing of the electronic system in
which the chip resides. The flexible imbedded test system is
sometimes known as FITS.
Known in the prior art is U.S.Patent No. 4,357,703
entitled "Test System for LSI Circuits Resident on LSI Chips".
This patent shows a test system which has switchable gates for
controlling internal data flow at the input and output of the
logic, shiEt registers for serially receiving data and
transmitting data in parallel and a test generator and receiver
system. In practice, this system has been very useful in logic
design. However, as VLSI logic gets more complex with an ever
increasing number of gates on a chip, design and testing needs
to become more sophisticated. The deslgn in this patent does
not provide adequate ability to look backward in the chip logic
sequence from the output register to Eind the source of
transient and intermittent faults. Thus, there is a need to
provide for improved detection and isolation of error
conditions within chip logic circuitry.
I` ~L25~6~ ~
1 ¦ A150 known in the prior art i6 U.S. Patent No. 4,244r~48
2 ¦ entitled ~Chip and Wafer Configuration and Testing Method for
3 Large Scale Integrated Circuits.a This patent sho~s a scan
4 1 design chip testing method which can be implemented both on
individual chips and also on a wafer c~ntaining a number of
61 chips during fabrication. This patent ~hows implementation of
7 BCan design techn~logy which reduced to simplest terms refers
8¦ to the ability of a register or a rank of flip-flops to
9 ~erlally scan data into and out of the rank for testing
10 purpo~e~ but which normally conveys data ~n ~ parallel fashion
11 ¦ from one stage of combinational ~ogic to another 6tage of
12 combinational logic. A chip having Bcan de~ign can allow the
13 entire chip contents or only selected operands to be read in or
14 out, However, with scan design, the entire ecan data path must
be acces~ed every time it iB u~ed including portions which may
~6 1 not ~e of intecest. All of this serial tran fer of a one bit
17 wide data path takes a lot of time.
lB l
19 ¦ A~ loglc chips become larger and larger, the dif~iculty of
using a scan design increases becau~e of tbe number of control
2~ signal6 required and the number of bit~ contained in all of the
22 flip-flop or regi~ter ranks on a large chip. These make the
23 te~ting or diagnostic overhead sufficlently large that it
24 becomes a problem in itself~ ~or example, a large number of
flip-flop bit sequences requires a very substantial data base
26 of test operands and expected results. Similarly, each
27 diferent chip type or design requires its own special testing
28 and diagnostic ~equences. Thus, while a scan design offers
29 Bome advantage~ for determining the contents of ~he registers
or flip-flops in a chip, it also has the burden of produclng a
31 cumbersome amoun~ o~ data~ rhu6~ tnere ~s a need to provide
- 3 -
2 ~ 7 ~ ~
1 for a way of using the benefits of 6can design but avoiding
2I unneces~arily large data bases of test operand6 and for
3 producing a more manageable chip testing routine.
5 ¦ SUMMARY OF THE IN~ENTION
61
7I The present invention i8 a 6ystem of diagnostic and
B testing circuitry which i8 incorporated lnto a VLSI chip to
9 provide various diagnostic and maintenance te~ting and
verification procedures. A logic chip according to the present
11 invention 18 constructed of the neces6ary input buffer~ and
12 output buffers for the intended l~gic unction. The logic of
13 the chip con6i6ts of various combinational logic elements and
14 flip-flops ~erially connected in data paths between the input
and output buffers.
16
17 In addition to the necessary combinational logic and
18 flip-flops on the chip, the necessary elements of an on-chip
19 ¦ maintenance system according to the di~closure of U.S. Patent
No. 4,357,70~ are~ incorporated. Those unit~ consist of a
21 ¦ maintenance control register with its associated control input,
22 an input serial to parallel register, an output serial to
23 parallel register, which is connected in series, as well as
24 ¦ interconnections with the various data paths on the chip. The
input register has the necessary connections to provide
26 pseudorandom number generating capabilitie~ to produce test
27 ¦ operands internallyc
28
29 In addition, the logic paths have several ranks of
flip-10p~ having special capabilities included. Early in the
3' data path is a t~o-to-ene m~ltiplex switc~ ~hich receives b~th
-- 4 --
1 2 r~ ~ 7 ~
1 the conventional logic input as well as an input for test data
2 purpose6. Normally, this te~t data input takes data fro~ the
3 last Plip-flop in the adjacent logic chain 80 that all of the
4 ¦ logic at the output end of the 1G9iC chain can be place~ back
5 ¦ at the beginning of an adjacent logic chain. The flip-flops
6 used in the logic chain~ are of a special design having two
7 inputs and two outputs. The conventional input and output
8 ~equence iB from one combinational logic unit to the ~ucceeding
9 comblnational logic unit ~nd con~l~ts of the normal data path.
The second lnput comes from the preceding rank of flip-flops
ll bypa6sing the combinational logic unit6 in between and the
12 second distinct output goe~ to the following rank of flip-flops
13 bypas~ing the aucceeding combinational logic inputs.
14
Thus, the flip-flop6 by proper gatlng may bypass
16 combinational logic un~ts under control 80 that specific
17 combinational logic units within a chip may be isolated from
l8 all other combinational logic units and receive Rpecial input
19 operAn~s and have those specific output operands gated as
output~ for diagnostic purpo~es. The multiplex switches at the
21 beyinning and ending of each logic chain allow for special
22 gating of outputE to inputs for serial writing and reading of
23 ~peclal operands into the chip and out of the chip. However,
24 not all of the flip-flops on the array need to be of a special
design, the actual implementation depends on design
26 requirementR. ~his allow~ for a flexible trade-of~ of speed
27 versus ea~ier and more extenslve testing. The parallel
2B connection vf the special flip-flop ranks allo~s for an easy
29 ~nd ast testing of a specific portion of the VLSl chip.
32
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. 66082-225D
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In accordance with a broad aspect of the invention
there ls provided a flip-1Op comprising:
first transmission gate means connected in a
data path from a data input to said flip-flop,
second transmi~sion gate means connected in a
testability input data path to said flip-flop,
normal operation gate means for cont:rolling said
irst and second transmission gate means to control which
of said i.nput data paths are provided as the output of
said flip-flop,
clock signal control means for controlling the
timing of the output of data in said output data path,
clock enable input means for controlling the
enabling of input data in said first data input path to
said flip-flop,
SET and RESET control means for said flip-flop
for controlling the output of said flip-flop to be a
predetermined quantity regardless of the input signal on
either of said first or second da-ta input paths, and
two separate isolated data output paths from said
flip-flop.
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i71
66082-225
IN TIIE FIGURES:
Figure 1 is a block diagram of the flexible imbedded
test system according to the present invention.
Figure Z is a schematic diagram of an initiali~ation
~ , .. .
sequence Eor a logic array using a parallel-serial design to
show full definition of the contents of all logic chip ranks
according to the present invention. Its ~arts, designated
2a-e show sequence order.
Figure 3 shows the invention oE Figure 1 in the logic
analyzer sequence mode.
Figure 4 shows the invention of Figure 1 in the chip
interconnect test mode.
Figure 5 shows the invention of Figure 1 in the
static chip test mode.
Figure 6 shows the invention of Figure 1 in the
dynamic signature analysis test mode.
Figure 7 shows the invention o Figure 1 in the
design fault detection mode Eor an error located between
two flip-flop ranks.
Figure 8 shows the invention of Figure 1 in the
design fault detection mode for an error located between the
last flip-flop rank and tlle outpu-t register.
Figure 9 shows the invention o Figure 1 in the
design ault detection mode for an error located between an
inpu~ buEfer and the Eirst Elip-Elop rank.
--6--
1 ~ig. 10 shows the inve~tion of ~ig. 1 in a test mode
2 forcing every 1ip-10p on the chip ~o a pseudorandom value.
3 l
4 Fig. 11 6hows the inYenti~n of Fig. 1 in a test mode
forcing every flip-flop on a chip to a predetermined value
61 using the input pins.
71
~¦ Fig. 12 shows the invention of Fig. 1 in a test ~ode for
9 flip-~lop integrity checking.
10 l
Il Fig. 13 Rhow~ the lnvent~on of Fig. 1 in a te~t mode for.a
12 6erial data shift into the flip-10p and shift out.
13
14 Fig. 14a i,s a ~chematic diagrar,l of a fir~t special
flip-flop design for use in the pre~ent invention.
16
17 Fi~. 14b 18 a truth table for the flip-flop de~ign of
I8 ¦ F~g. 14a.
19
Fig. 15a i8 a 13chematic diagram c~f another special
21 flip-1Op design for use in the pre6ent invention.
22
23 Fig. 15b is a truth table or the f?ip-flop of Fig. 15a.
24
Fig. 16a i~ a ~chematic diagram of yet another ~pecial
26 ~lip-~lop design for use in the present invention.
27
28 Fig. 16b is a truth table for the flip-flop of Fig. 16a,.
29
31
32 - 7 -
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' ~ ~2~i~6~7
1 DESCRIPTION OP THE PREFER~ED EMBODIMENTS
3 ¦ Referring to Fig. 1, an embodiment of the present
4 inventlon 10 i8 ~ho~n~ on a. conventional logic chip. The logic
~¦ chip ha~ a plurality of ~nput pins 12 each of which is
61 oonnected with an input buffer 14. The output from each input
7 buffer i8 switchably connected to a combinational logic unit 16
81 o~ #ome sort as required for operation of the intended purpose
9 of the logic chip. In addition, each $nput buffer has a
separ~te switchable cDnnection lB, 20, 22, 24 and 80 forth to a
Il ¦ separate bit of an ~nput regi~ter 26 which i8 part of the
12 on-chip maintenance ~ystem a~ described in U.S. Patent No. ~5,
13 357 9703. The input register 26 and control register 28 have
14 the capability o generating pseudorandom number~ and of
~ending and receiving data ln aerial or parallel form. ~n. put
l6 cegister 26 ~s connected by a data path 30 to a ~imilar output
17 register 32. The content~ of output register 32 are connected
lB ¦ through a two-to-one multiplex gate 34 to the test data output
Ig pin 36. The te~t data input pin is pro~lded at 38.
21 The output of each similar combinational logic unit 16 is
22 c~nnected to a eank o~ multiplex dat~ ~witche~ 4~. Each
23 multiplex data switch 40 receives a test data input 4~ whlch i6
24 feom another portion of the logic chip as wlll be described.
Each multiplex ~witch 40 has a control input line 44 to control
26 whether the standard data path iB u6ed or a serial ~can mode
27 data path is used which transfers in the te~t data.
28
29 Each of the two-to-one multiplex switches 40 is connected
to a fir6t rank of special flip-flops 50 having two distinct
~i input~ and two distinct outputs. The standard mode of
32 operation of the fl~p-flop rank is to have the normal operating
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~5~;7~
l data from the multiplex ~witch 40 be connected through the
2 normal input path 52 through the flip-flop tG the normal output
3 path 54 to the next combinational logic element 56. Two modes
4 ¦ of te3t data may be implemented, one in which the output data
~ passe~ through the te~t data path 5~ which bypasses the
6 combinational logic unit 56 and i~ gated to the test data input
7 of the next rank of flip-flops 60. The other data path is the
standard logic data path 54 which i5 connected to the
9¦ combinational logic units 56. The logic output of
10 combinational logic units 56 pa~ses through a conventional
11 . logic da'ca path 62 to the flip-flop rank 60.
12
13 ~lmilarly, fllp-flop eank 60 i5 connected directly to
14 combin~tional logic un~ts 90 which in turn are connected to yet
another f lip-f lop r ank 90 . Flip-f lop r ank 60 is also connected
16 through data path 70 directly to flip-flop rank 9Q. Thus, the
17 scheme of connection foL te~t purpo8eB i8 that each flip-flop -
lB rank is connected directly to the succeeding flip-flop rank so
19 that no logic processing operation occurrs in the combinational
logic unit and unchanged operands are passed within the chip.
21 However, for normal operation, data i~ pa6sed through the
22 ¦ combinatlonal logic units and ~he fli~-flop rank ~or the
Z3 required logic operations.
24
Finally, flip-flop rank 90 i~ connected directly to
26 combinational logic units 100. Fllp-flops 90 are also
27 connected through a bypass data path 94 to two-to-one multiplex
Z3 switche~ 110. Flip-flop rank 90 has a conventional da~a
29 path 92 to combinational logic unit 100 which in turn has a
conventional data path 96 output to multiplex ~witch 110. The
31 flip-flop test data bypass connection 94 between flip-flop rank
32 90 ~nd the multiplex switch 110 also includes a data path 42
_g_
1 1;~5.?671 `~ l
1 which is connected back as an input to the first rank of
2 two-to-one multiplex switches for use in the ~er ial scan test
3 mode.
4 : '
5 ¦ Finally, the output of the final multiplex switch 110 is
6 ~witchably connected to a rank of output buffers 120. The
7 output buffers all receive data either from output register 32
8 of the ma~ntenance and diagnostic system or from the two-to-one
9 multiplex switch output 110. Finally, the output of output
buffer~ 120 is connected to output pins 130 to provide the data
11 output for the chip.
12 l
13 Switches 150, 16~, 17~ and 180 are controlled by control
14 regi6ter 28 and form part of the control ~ystem of the on-chip
maintenance ~yqtem shown ~n Pat. No. 4,357,703. These switches
16 ~ontrol ~he data path ~n normal parallel in ~nd out mode and
17 allow register6 26 and 32 to provide 6erial data shifts.
18
19 Referring now to Fig. 2, an initlalization sequence is
shown for an array having five flip-flop ranks and in which
21 thele are di~ferent numbers of flip-flops in the different
2~ ranks. Al60, ~ome flip-flop ranks skip one or two possible
23 logic levels 60 that data passes more rapidly in one chain than
~4 another. Note for example that some flip-flops in rank 2 are
connected directly to rnnk~ 4 or S. The different cros~-hatch
26 patterns show a level o logic as it is clocked ~hrough the
27 flip-flops. Thi~ sequence shows that, even if some of the
28 flip-flop ranks haYe fewer flip-flops than other ranks, the
2~ content of every flip-flop on the chip is defined after a
3 number of clocks equal the number of flip-flop ranks.
32
1259~
l Fig, 3 Ehows the logic ~nalyzer sequence which is similar
2 to the standard operation of the malntenance and teQt system as
3 shown in Patent NQ. 4,357,703 in which input data i6 provided
4 through the input p,ins and lnput buffer~ and connected into the
test data input regi~ter 26. R~gister 26 i8 connected through
~¦ data path 30 to the output reglster 32 as well as to the input
7¦ o the output buffer rank 120. Output buffer~ 120 are
81 connected to output register 32 and hence to output pin 36 to
9 in~ure that the input/output value ~f the chip functions can be
monitvred dur~ng normal chip activity. In this mode, the SSM,
11 NOP and ~RFF values are Ret to 1.
1~
13 ~ig. 4 ~hows a basic chip interconnect test ~equence. ~he
14 SSM, NOP and LRFF values are ~et to 1.
16 Fig. 5 ~how~ a static chip test in which input data i6
17 provided to the input test regi~ter 26 and pas~ed through all
18 ¦ of the co~inational loglc and flip-flop ranks of the chip in
19 nor~al operating mode and connected through the output
regi6ter 32 to the test data-output pin 36. This test sequence
21 determines i~ all the logic in the chip i8 operating in a
2Z normal fashion independently of input and output pins and input
23 and output buffer~ and is thus a pure test o~ the logic in the
24 chip ~eparate and apart from lnput and output transients.
Again this ~unction i8 s~m~lar to that shown in Patent
Z6 No. 4,357,703.
27
2~ Fig. 6 show6 a similar test to that shown in Fig. 5. The
29 input test regi~ter 26 produces a pseudDrandcm input data
6y~tem and the output register 32 is checksumming the results.
31 Thi~ sequence i~ a dyna~ic signature analysis function.
1;~59671 - l
l Pig. 7 shows a test ln which the test data input
2 register 26 provide~ data to the conventional logic paths ln
3 the ch~p. However, the flip-~lop eank 50 is ~d~uRted to take
lnputs from the test"'data input path 48 ther~by bypassing
5 combinational logic rank l6. The output of flip-flop rank 44
is connected to combinational logic rank 56 which i8 to be
7 tested to determine if lt i~ faulty. The output flip-flop rank
8 from comblnational logic rank 56 is flip-flop rank 60 which is
9 selected to pas~ it~ output down the test data path through
other flip-flop ranks ~uch ~8 flip-flop rank 90, bypassing
11 other combinational logic ranks in the unlt such a~ rank BO so
12 that the output is connec~ed directly through the two-to-one
13 multiplex buffer ran~ llO into the output register 32. Thus,
14 the input pins, the input buffer~, the output buffers and
output pins are isolated out of the test. By proper selection
16 of the gating of the fllp-flop ranks SO, 60, 90 and the
17 multiplex switches 40 and ll~ the data pas6es only through
18 comoinational logic rank 56. The SSM value is 1. The NOP
19 value i8 set at O initially, then 1 for one clock period, then
O for the rest of the test. The LRFF value i8 O. Thus, a pure
21 te6t o comb~national logic rank 50 is provided between data
22 flowing ~rom input register 26 ~o output register 32 and
23 through the test data output pin 36.
24
Fig. 8 shows a similar test sequence where the presumed
26 faulty logic rank is combinational logic rank lOO and the data
27 byp~s~es the other combinational logic ranks of the system so
28 that the only data operation is performed in combindtional
29 logic rank 100.
31 Followiny a ~imilar patte~n, Fig. 9 hows a tes~ in which
32 the cnly combinational logic rank which has da~a passing
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~25~67~ - I
1 throuqh it i9 rank 16 and flip-flops 5~, 60, 90 and multiplex
Z ~witche~ 4U and llU are set to connect data fr~m the input
3 I register 26 to the output register 32 80 a~ to bypass all other
4 combinational logic'ranks. The SSM value ia 1 and the LRFF
5 ¦ value iB 0, The NOP value iB set ~o 1 for one clock and then
6 ¦ ~et to O ~or the ~est of the test.
B Fig. 10 shows the ca~e in which all combinational logic
9 units are bypa66ed BO that tect data from register 26 can be
pas6ed 2equentially to all flip-flop ranks SD, 60 ~md 90 to set
11 the condition of all flip-flops to be a predetermined
12 condition. The SSM value i~ 1 wh~le the NOP value i8 O.
13 I .
14 F~ g . 11 shows the same condition of forci~g every
15 fl~p-flop on ~ chlp to be a predetermined value but using the
16 conventional data inp~t pins 12 rather than the test data input
17 regi~ter 26 to provide the data path.
18
19 Fig, 12 shows the altuation ~n which the flip-flops ~nly
are te~ted for integr ity and in which no combinational logic
21 units sre employed on the chlp ~o that all data flows only
22 through the fllp-10ps on the chip and not through any of the
23 combinational logic units or the multiplex 6witch system. The
24 SSM value i~ 1 while the NOP and LRFF values ar~ 0.
26 Finally, Fig. 13 ~hows the situation in which the
27 multiplex 6witches 40 and llP are ~et for a ~can pattern
28 function with all of the f}ip-flops so that data may be scanned
29 serially through the entire chip starting from the test data
input 38 through first multiplex switch sequentially through
31 1 all of the flip-flops S~, 5~ and 90 in the first logic path and
ll - 13 -
125~71 - I
1 then aequentially through all of the ilip-~lop~ and out through
2 the test d~ta output pin. The SS~ and NOP valu~s are set to 0.
4 Pigs. 14a, 15~a and 16a~ how flip-flops for use in
connection~with the present invention ha~ing an increased
6 degree of complexity and controllability depending on the needs
7 of the designer. One of the advantages of the present
8 invention i8 it may be u~ed in connection with any one of a
9 numbe~ of different types of ~lip-flops in the various
flip-flop ranks, or it may be u6ed with several diEferent type~
11 of flip-flops in the different flip-flop rank~.
12
13 ' Referring now to Fig. 14a, the flip-flop 20a has a clock
14 ~nput 202 to an inverter 204 wbich i8 connected as one o~ the
input~ to an AND gate 206. The output of inverter 204 is also
16 connected to inverter 20~ and ~ND gate 210. The flip-flop has
17 a normal operation ~NO~) ~nput 212 which i8 connected with
la inverter 214 and provide~ the second input to AND gate 206.
19 The output of lnverter 214 provide~ ths second input to AND
gate 210. The outputs of AND gate~ 2~6 and 210 are both
21 inverted and connected to inverting drivers 216 and 218,
22 respectively. Drivers 216 and 21~ each drive transmission
23 gat0~ of a standard P-N ~unction type, al80 commonly referred
24 to as T-gates. T-gate~ are speclfic to CMOS technology but
this invention is not llmited to CMOS technology and may be
26 implemented in other ways. CMOS technology i6 a convenient
27 reference point for e%plainlng this embodiment of the invention.
28
29 Inverter driver 218 controls T-gate 22~ which is connected
3 in the testability input 222 to the flip-flop. Inverter driver
31 216 controls T-gate 224 wh~ch is in the data input 226 to the
32 flip-flop. The outputs of ~-gates 220 and 224 are connected to
- lq -
I lX596~
I ..
l the input to inverter 22B. The design of the flip-flop is such
2 ¦ that T-gates 22U and 224 will not be on at the ~ame time. The
3 ¦ output of ~nverter 208 is connected to invert~r driver 230
4 ¦ which drives T-gate 232 in the output of inverter 228. The
5 ¦ output of T-gate 232 i8 connected to inverter6 234 and 236 to
6 provide isolation in the output. Inverter 234 provides the
7¦ data output of the flip-10p, while inverter 236 provides the
~¦ testabllity output Qf the flip-flop.
91
Fig. 14b provides a truth table for the flip-~lop. The
11 normal operatlon input i8 ~hown together with the clock, data
12 in and testability input~ as related to the output. AS can be
13 seen from the schematic dia~ram, both the data output and the
14 ¦ testability output are the same. In the trutb table, ~he
~ymbol ~X~ refers to a rdoes not matter condition~ and the
16 ¦ symbol ~Q~ refer6 to a ~remain~ in the same condition as
~7 be~ore~ output~ The ~Q' output means that a previous binary 0
lB ¦ output remains at b~nary 0, and a previous binary 1 output
19 remains at 1.
21 ¦ Refe~ring now to Fig. lSa, a more complicated flip-flop
22 250 ~s shown which ha~ an additlonal clock enable lnput not
23 shown in the flip-10p of Fig. 14a. Plip-flop 250 has a clock
24 inpu~ 252 connected to an inverter 254 the output of which is
connected to inverter 256. The output of inverter 256 is
26 connected with inverter drlver 258 which controls T-gate 260.
27 The clock enable input ~62 is connected as one input to AND
28 gate 264 and to inverter 266. The output of inverter 266
29 provides one input to A~D gate 26~. The output of inverter
254, previously mentioned, provides a ~econd input to both AND
31 gate~ 264 ana 26~. Irhe normal operation input 270 is connected
32 ¦ to pro de a tbird input to botù AND gates 264 ~d 2S9. The
1259~71
1 normal operation input is al60 connected as one input to OR
21 gate 272. The second input to OR gate 272 i8 the cl~ck input
3I 252. The OR gate output i~ inverted and control~ inverter
41 driver ~74 which drives T-gate 276. T-gate 276 iR in the
testability input line 278. The output of AND gate 264
6~ control inverter drlver 280 which controls T-gate 2~2 which is
71 in the data input llne 284. The output of AND gate 268
81 control~ inverter drlver 286 which drives T-gate 288. The
9 input to T-gate 2B8 1B a wired connection of the outputs of
T-gate~ 2~2 and 2~6. The output of T-gate 2~2 i~ ~1BO
11 connected to inverter 29Q, the output of which i~ connected to
12 T-gate 260. The ou~put of T-gate 260 i8 connected to inverte~s
292 and 294 to provide i601ation for the data output line 296
14 ¦ and the te~t~bility output 2g8. In addition, thi~ output
~5 signal from T-gate 260 i8 al80 connected back through inverter
I 300 through T-gate Z8~ to provide an additional wired ~nput for
17 feedback to inverter 290. Fig. 15b i8 a truth table for the
lB ¦ flip-flop of Fig. 15a Rhowing ~he effect that the va~ious
19 state6 of ~he vae ious input~ has on the output of the
flip-flop. Ayain, the output o~ the testab~lity output and the
21 ¦ data output i8 the ~ame.
22
23 Referring now to Fig. 16a, a more complex flip-10p 310 i~
24 shown. This flip-flop is more complex than the flip-flop o~
~ig. l5a in that it ha~ SET input 312 connected to AND gate 314
26 ¦ and RESET input 316 connected with OR gate 31B as ~dditional.
27 ¦ inputs. The SET input 312 also provides a second input to OR
28 gate 3}~, RESET input 316 is connected through inverter 320 to
29 provide a second input to A~D gate 314. The output of AND gate
314 i~ inverted and connected as an input to AND gate 322. The
~1 output of ~p. 9~Le 31~ iE connected and provided as one input to
32 ~ both A D gdte6 324 and 326. The clock eoable input 323 is
l c~nnected as the ~econd input to AND gate 324, The clock
2 enable input 328 i~ connected through lnverter 330 to provide
3 the second input to AND gate 326. The output of AND gate 324
4 i~ inverted and connected a6 one input to OR gate 332. The
~ output of OR gate 332 is one input to AND gate 322. The output
6 of AND gate 326 ~ inverted and connected as one input to OR
7 gate 334. The output of OR gate 334 is the third input to AND
8 gate 322. The data input connection 336 goes through inverter
9 338 ~nd prov~de~ a second lnput to OR gate 332. The output of
AND gate 322 ls inverted ~nd connected to T-gate 340.
11
12 The testability input 342 is connected to T-gate 344. The
13 ~lock input 346 i6 conne~ted through inverter 348 to inverter
14 350. The normal operatlon ~NOP) input 352 18 connected through
inverter 354 to AND gate 356. One output of inverter 348
16 provides the second input to AND gate 356. The output of ~D
17 g~te 356 i~ connected to ~nverter driver 358 which controls
~a ¦ T-gate ~44. In Additlon, the norm21 operation input 5NOP) 352
19 ~a connected ~o AND gate 360. AND ~a~e 360 ceceives a second
~nput from inverter 348. The output of AND gate 36~ i~
2~ ~nverted and controls in~erter driver 362 which drives T-gate
22 340.
23
24 ~he output of tran~mi6sion gate 34~ and the output of
transmisslon gate 340 are combined as inputs to inverter 364.
26 The output of inverter 364 i~ connected as an input to
27 transmi~sion gate 366. TranRmi~sion ~ate 366 ig controlled by
2~ the output of inverter 3SC wh~ch has its output connected to
29 inverter driver 3680 The output of transmission gate 366 is
connected to inverters 37D and 372 which provide the outputs of
31 the flip-flop. The output o~ t~nsmi~si~n g~t~ is ~iso
32 provided as the ~econd input to OR gate 334,
- 17 -
~ 5~7~
I
1 Referring now to Pig. 16b, a truth table for the circuit
2 of Fig. 16a is ~hown. As can be seen from the truth table, all
3I the control ~eature~ of the flip-flops ~hown in Pigs. 14a and
4 15a are pre~ent, but wlth the addition that the use of the SET
~nd RESET input~ ta the flip-flop can be used to force the
6I ou~put to a O or a 1, as desiced.
~ The pre~ent lnvention has numerou6 advantayes. One
9 particular ~rea of advantage of the present invention is the
ease and conven~ence with which test operands may be loaded
11 into ~ chip for testing of combinational logic, and the ease
12 with wh~ch ~pecific combinational logic unit~ may be isolated
13 for testing. ~ecau~e loading of test operands into a
14 pa~ticular area of a cSlip may be accomplished in parallel by
15 ¦ direct gating through the tes~ability gates on flip-flops
16 skipping other combinational logic unit~, test routine~ may be
17 run far more quickly and efficiently than prev$ously. In
18 particular, the long time period for loading and unloading
19 ~equired for typical ecan designs i8 avoid~d.
21 Similarly, 6pecific combinational logic elements within a
22 chip may be te6ted and isolated from preceding and succeeding
23 comb~nat~onal loyic units in a way either not previously
24 possible or po~sible only with cumbersome techniques and a
complex scan design. The variou6 advantages of the scan design
26 are primarlly developed in connectlon with ~he flexibility that
27 this design provide~ for te~t routines of various sorts. In
28 addition to the ~lexibility o~ test routines that may be
29 adopted, this design is al80 flexible in that ~everal different
types of flip-flops can be placed on a logic chip so as to
31 avoid the r~strictions of some prev ous test d~siqns ~hich
- 18 -
~L~5~71
¦ required ~ single type cf flip-flop ln all lvcations in a logic
~¦ chip.
31
4 This ~ystem can te~t with the ~ame ease a restric~ed
~mount of combinational logic if it i~ before the first special
6 flip-flop rank, between two flip-flop rank~ or between the last
7 1ip-f}op rank and output. Any of these ~equences will not
6 require the lnitialization of every flip-flop on the array to a
gl predetermlned value, which i~ very t~me consuming and requires
l a larger data bAse.
12
~3
14
16
17
18
19
21 I .
22 .
23
2~
26
27
2B
~1 .
32
-19-
