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Sommaire du brevet 1260535 

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  • lorsque la demande peut être examinée par le public;
  • lorsque le brevet est émis (délivrance).
(12) Brevet: (11) CA 1260535
(21) Numéro de la demande: 1260535
(54) Titre français: CIRCUITS DE PROTECTION CONTRE LES SURTENSIONS
(54) Titre anglais: VOLTAGE SURGE ARRESTER CIRCUITS
Statut: Durée expirée - après l'octroi
Données bibliographiques
(51) Classification internationale des brevets (CIB):
  • H02H 09/02 (2006.01)
  • H04M 03/18 (2006.01)
  • H04Q 03/00 (2006.01)
(72) Inventeurs :
  • WALTER, KARL-HEINZ (Allemagne)
(73) Titulaires :
  • SIEMENS AKTIENGESELLSCHAFT
(71) Demandeurs :
  • SIEMENS AKTIENGESELLSCHAFT (Allemagne)
(74) Agent: SMART & BIGGAR LP
(74) Co-agent:
(45) Délivré: 1989-09-26
(22) Date de dépôt: 1984-11-09
Licence disponible: S.O.
Cédé au domaine public: S.O.
(25) Langue des documents déposés: Anglais

Traité de coopération en matière de brevets (PCT): Non

(30) Données de priorité de la demande:
Numéro de la demande Pays / territoire Date
P 33 40 927.7 (Allemagne) 1983-11-11

Abrégés

Abrégé anglais


SUMMARY:
VOLTAGE SURGE ARRESTER CIRCUITS:
A circuit arrangement for the diversion of surge
voltages, in particular for use in exchange systems, with a
main distributor (HV) and a subscriber assembly (TB) having
an electronic SLIC, in which there are arranged in the series
arms of the a/b-wires prior to each electronic SLIC two power-
type MOS-FETs connected in series and in mutual opposition and
serve as current delimiters.

Revendications

Note : Les revendications sont présentées dans la langue officielle dans laquelle elles ont été soumises.


THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
l. A circuit arrangement for drainage of over-voltages in
switching systems comprising a main distributor and a subscriber
module with an electronic SLIC (subscriber line interface
circuit), in which a two-pole electronic current limiter is in
each case arranged in series arms of a/b wires connecting the main
distributor to the electronic SLIC, characterized in that two in
series and oppositely connected power MOSFETs each are arranged as
current limiters and that optoelectronic couplers are used for
generating a positive bias voltage at gates of the power MOSFETs.
2. A circuit arrangement according to Claim 1,
characterized in that the power MOSFETs have drains which are
connected together.
3. A circuit arrangement according to Claim 1 or 2,
characterized in that additional power MOSFETs are arranged in the
series arms of the a/b wires for coupling in further functions.
4. A circuit arrangement according to Claim l or 2,
characterized in that the current limiter comprises a
monolithically integrated chip.
5. A circuit arrangement according to Claim 1 or 2,
characterized in that additional power MOSFETs are arranged in the

series arms of the a/b wires for coupling in further functions,
and in that the current limiter comprises a monolithically
integrated chip.

Description

Note : Les descriptions sont présentées dans la langue officielle dans laquelle elles ont été soumises.


~LZ~(1S35
20365-2~36
VQLTAGE SURG~A R~STER CI CUITS~
The invention relates to voltage surge arrester circuits
particularly for use in exchanye systems having a main distributor
and a subscriber assembly provided with an electronic SLIC
~Subscriber Line Interface Circuit).
The transition from conventional to electronic SLICs in
inteyrated technology necessitates a new form of protection that
is re~uired for IS -~eahnology. Previous proposals basically
provided only for the diversion of ~he currents produced by the
surge voltage. Relatlvely hlgh currents must still be diver~ed
from the subscr.tber assembly, which leads to elaborate
constructions incompatible with the construction of modern
electronic circults.
One object of the present invention is to provlde a
circult arrangement for t.he elimination of surge voltages which is
arranyed between the main distributor and the subscriber assembly
and which in the event of a surge voltage at the input permits
only a maximum permissible current level which can still be
tolerated by an electronic SLIC.
In accordance with the present invention there is
provided a circuit arrangement for drainage of over-voltages in
switching systems comprising a main dlstrlbutor and a subscriber
module with an electronic SLIC (subscriber line interface
circuit), in which a two-pole electronic current limiter is in
each case arranged in series arms of a/b wires connecting the main
distributor to the electronic SLIC, characterized in that two in
series and oppositely connected power MOSFETs each are arranged a~
~9

~26~3~ ~0365-2~36
current limiters and that optoelectronic couplers are used for
generating a positive bias voltaye at gates of the power MOSFETs.
la

~6~)S3~i
The invention will now be described with reference
to the drawings, in which:-
Figure 1 is a fundamental schematic circuit diagram
of one exemplary embodiment;
S Ei'igure 2 shows details of a current limiter of mono-
lithic construction;
Figure 3 is a graph showing the characteristic curve
of the current limiter shown in Figure 2: and
Fi~ure 4 is s simplified representation of a multiple
10 crosspoint having a support function.
The fundamental schematic circuit diagram shown in
Figure 1, is of an overall protection circuit for an exchan~e
system, which consists of a main distributor HV and a subscriber
assembly TB. In the main distributor HV, the components not
15 particularly liable to damage are provided with thyristor diode
protection, comprising two thyristors, Thl and Th2. This limits
residual voltage peaks to a specific value (e.g. 250V). Guide
values for the thyristor diodes Thl and Th2 are 100 A ( 10/100u s )
and 500 A (8/20,~s) respectively, for example. In highly endan-
20 gered zones where additional protection is required, ~as
discharge cells Ç1 and G2 are provided, with respective decoupling
resistor, R1 and R2, interposed between each gas discharge device,
G1 or G2, and the associated thyristor diode, Thl or Th2.
In this way all high discharge currents are restricted
25 to the main distributor HV, and only transient voltage peaks of
up to 250V can occur across the subscriber assembly TB.

~l2~0S35i
However, the electronic Sl,IC can withstand on]y a low blocking
voltage in the subscriber assembly TB, and a residual peak
voltage of 250 V is too high. Therefore, each of the two series
arms, a to a' and b to b', has interposed a current limiter,
5 S1 and S2 respectively, which each consists of two mutually opposed
power-type MOS-FET s connected in series . This ensures that ln
the event of a surge voltage appearing across the input, only a
maximum permissible current is allowed, which is low enough to
` be tolerated by the electronic SLIC. Thus in the event of a surge
10 voltage the current limiters Sl and S2 absorb the voltage peaks
as series voltage drops. It goes without saying that the dielectric
strength of these limiters S1 and S2 must exceed the maximurn
occurring peak voltage (e.g. 300 V).
The transmission technology requirernents to which a
15 series element is subjected, such as low resistance and linearity
in the operating range, are fulfilled by the power-type MOS-FETs.
Two power-type ~OS-FETs are required, connected in series in
mutual opposition to one another, in order that the transmission
and limitation functions can be fulfilled even in the event of
20 reversal of the current direction. It is advantageous to combine
the two drains in terms of circuitry, which facilitates a monolithic
integration of the current limiters S1 and S2.
The requirements imposed on the relative tolerance of
the current limiters Sa and Sb, which serve as series resistors
25 Ra ~ Rb in the two wires , a to a ' and b to b ', are governed
by the following logic-links:

)S35
Ra, Rb ~ 5 n for I ~ ~ 100 mA and ~ R = ¦Ra - Rb¦ ~ 1 n
If the maximum current is limited, e.g. to a level
of 150 mA at 300 V no overload can occur at the maximum
occurring transient interferences of one ms duration,
Although it is true that the peak currents which
continue to pass through the current limiter can still produce
voltages above the operating voltages across the SLIC inputs,
a ' and b ', these are diverted by c] amping diodes Dl to D4 which
~"`! are normally integrated into every SLIC. These clamping diodes
Dl to D4 are required for the relative protection of the electronic
SLIC and therefore do not ~generate additional costs. Because
the transient peak currents are limited to 1~;0 mA, these diodes
Dl to D4 can remain relatively small in dimensions.
The distribution of the protective measures between
the indivi dual protection locations results in the following
advantages . Only low vol tages occur at the output terminals,
a and b, of the main distributor HV and these require no
special spatial clearance in subseq uent insulation . The
~- absorbtion and reflection of the interference energy associated
20 with the surge voltage is carried out for the major part in the
main distributor HV which, in terms o~ its mechanical construction,
is also the most suitable to perform this task . The combina tion
of different protective principles, namely parallel diversion in
the main distributor HV and series current limitation in the
subscriber assembly TB, renders the protection for devices,
systems and individuals both effective and cost-~avourable. No

~2~ i3S
high voltages nor high currents need to be discharged from the
subscriber assembly TB. The diode protection in the electronic
SLIC provides the necessary relative protection, i~e. it is
operative when the surge vol tage exceeds the instantaneous
5 applied battery voltage. The distribution of the protection
locations also facilitates a clearly defined delimitation of
protection characteristics and protection level.
This method can also be used for the standardisation
of the protection values, which is advantageous since the
10 protection func-tions occur in different areas of responsibility,
such as individual operatin~g companies or system manufacturers,
for example.
Figure 2 gives the fundamental circuit diagram of a
monolithic current limiter S1 (S2) to be arranged in a series
15 wire from a to a ' or b to b ', between the main distributor and
the subscriber assembly. The current lirr.iter 51 (S2) consists
of two power-type MOS-FETs, T1 and T1 ', whose drains are
~` ~! combined in the circuit, and which are thus components connected
. . .
in series and in opposition to one another with a common sub-
20 strate drain. Series resistors R and R', and multiple diodes, M
and M ', serve to set the bias voltage for the current limitation
in the case of transistors of the enhancemen~ type.
In place of the multiple diodes, M and M' represented
in the drawing, the current limitation can also be effected with
25 the assistance of Zener diodes.

53S
More advantageous are transistors of the depletion
type which are conductive without the provision of any bias,
(gate and source connected). However, in this case the current
limitation value must be governed by the transistor parameters.
The graph shown in Figure 3 the charac-teristics
curve of the current limiter element corresponding to the Figure
2 arrangement. As can be seen from the drawing, the curve
exhibits an exact zero transition which is essential to the desired
current limiter function.
In Figure 4 there is a representation of a multiple
crosspoint having a protective function, with the assistance of
which not only is a current limiter function carried out in the
arm from a to a '; but which also can assume other functions in
the BORSCHT-concept, where BORSCHT signifies Battery Feeding,
Over Voltage Protection, Ringing, Signalling, _oding, Hybrid
(~ wire - 2 wire conversion), Testing). This multiple cross-
point includes four transistors Tl, Tl',Tl", T1"' whose drains are
combined in the circuit. At the crosspoints a" and a"' the
ringing voltage (R) can for example be input-coupled or test
devices (T) can be connected. In the exemplary embodiment
shown in Figure 4, respective opto-electronic couplers, 01, 01',
01" and 01"', serve to produce the necessary positive bias voltage
to set a current limit value.
The module represented in Figure 4 can also be designed
as a monolithic integrated modu~e, in which case further power-
type MOS-FETs (Tl"". . . ) can be additionally integrated for the
input-coupling of further of the above-described functions.

1%~)53~;
In addition to the above-described circuit arrangemen-t
for an exchange system, the invention can also be used as an
automatic series safety measure in general device technology.
In this case, to allow for the possibility of a long-term load,
S it is desirable to insert a heat sensor which can effect a
circuit separation if operated.

Dessin représentatif

Désolé, le dessin représentatif concernant le document de brevet no 1260535 est introuvable.

États administratifs

2024-08-01 : Dans le cadre de la transition vers les Brevets de nouvelle génération (BNG), la base de données sur les brevets canadiens (BDBC) contient désormais un Historique d'événement plus détaillé, qui reproduit le Journal des événements de notre nouvelle solution interne.

Veuillez noter que les événements débutant par « Inactive : » se réfèrent à des événements qui ne sont plus utilisés dans notre nouvelle solution interne.

Pour une meilleure compréhension de l'état de la demande ou brevet qui figure sur cette page, la rubrique Mise en garde , et les descriptions de Brevet , Historique d'événement , Taxes périodiques et Historique des paiements devraient être consultées.

Historique d'événement

Description Date
Inactive : Périmé (brevet sous l'ancienne loi) date de péremption possible la plus tardive 2006-09-26
Inactive : CIB de MCD 2006-03-11
Accordé par délivrance 1989-09-26

Historique d'abandonnement

Il n'y a pas d'historique d'abandonnement

Titulaires au dossier

Les titulaires actuels et antérieures au dossier sont affichés en ordre alphabétique.

Titulaires actuels au dossier
SIEMENS AKTIENGESELLSCHAFT
Titulaires antérieures au dossier
KARL-HEINZ WALTER
Les propriétaires antérieurs qui ne figurent pas dans la liste des « Propriétaires au dossier » apparaîtront dans d'autres documents au dossier.
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Description du
Document 
Date
(aaaa-mm-jj) 
Nombre de pages   Taille de l'image (Ko) 
Abrégé 1993-09-12 1 11
Revendications 1993-09-12 2 37
Dessins 1993-09-12 3 50
Description 1993-09-12 8 198