Note : Les descriptions sont présentées dans la langue officielle dans laquelle elles ont été soumises.
Back~round of the Invention
This invention relates generally to apparatus for
obtaining and s~orlng information about physical parameters
or phenomena detected in a well bore and more particularly,
but not by way of limitation, to an improved self-contained
downhole gauge for locally detecting and internally
recording pressure and temperature information for later use
at the surface of a well bore after the gauge has been
withdrawn from the well bore.
It is well known in the art that there is a need for
apparatus which can measure environmental conditions or phy-
sical phenomena, such as pressure and temperature, in
downhole locations within a well bore. The Bourdon tube is
well known and has been used for many years to mechanically
record pressure by means of a chart scribed on a metallic
plate in response to pressure. Electronic recording gauges
have also been used in well bores. In one type of electro-
nic gauge, the information is obtained and substantially
immediately transmitted to the surface, such as over a wire
line, for real-time display. Another type of electronic
gauge obtains and stores the information within itself
downhole for use only after the gauge has been extracted
from the well bore.
Althougn several different types of gauges have been
proposed or used in the industry, we are not aware of any
., ~
-2-
gauge which accommodates several different transducers
having di~ferent output signal characteristics. Nor are we
aware of a micrspr~cessor-based gauge which monitors itself
to insure it is operating within normal limits, and which
S permits sample rates and resolutions to be varied in
response to both software and hardware monitored changes in
the downhole pressure (or other monitored condition) and to
changes in battery life and remaining memory capacity, and
which can be automatically selectively powered down, and
o which has increased storage capacity achieved with highly
reliable, duty-cycled for low power consumption, m~gnetic
core memory densely packed in a folded configuration.
Likewise, we do not know of any such apparatus which permits
such increased storage capacity to be accessed with a bit-
5 by-bit technique that reduces the chances of losing complete
words of stored information should there be a failsre within
the storage elements. We are not aware of any such appara-
tus which can determine which, if any, memory cell~ are in~-
perable and which thereafter does not attempt to store
2D information in those bad memory cells. Although to our
knowledge there is not a downhole apparatus having each of
the foregoing features, such an apparatus is needed because
of the following advantages which are or can be obtained by
appropriately implementing these features as is done in the
2 5 present invention.
A gauge which accommodates different types of trans-
ducers is needed to provide flexibility of use since a
--3--
single downhole gauge is used in different locations where
certain types of transducers may not be available and for
different customers who may specify different types of
transducers.
S Self-monitoring is an important feature in a
microprocessor-based gauge because it enables the micropro-
cessor to be reset should the microprocessor operate outside
normal operating limits. This insures accurate data collec-
tion.
o The software and hardware features by which sample rates
and resolutions of the samples can be changed are important
for at least two reasons. The software monitoring is impor
tant because it effectively increases the length of time
over which samples can be obtained by reducing the sample
~5 rate when there is little or no change between or among con-
secutive samples of a parameter or when changes are substan-
tially linear. The hardware monitoring is important because
it detects, and forces the gauge to record, rapid changes
which occur between the software set sample times and which
20 thus would otherwise be lost. Adjusting the sample rate
based upon the remaining battery life and memory insures
that meaningful information is always obtained and properly
stored. Theoretically, it is desirable to slow the sample
rate suEficiently so that samples are obtained and stored
25 without ever totally exhaustlng the battery life or the
memory capacity prior to the time the apparatus is withdrawn
from the well bore and deactivated~ ~aving a selectable
7~
~ _
resolution i~ important so that suitable precision is
obtained at each sample rate.
The ~eature of automatically selectively powering down
selectable parts o~ the apparatus is important because i~
5 conserves the remaining battery life. Section selectability
maximizes the conservation at any one time by powering only
those sections which need to b~ operated at that time.
Selective power down of substantially the entire tool both
at scheduled times and at unscheduled times when nothing
significant is happening further assists in energy conser-
vation.
Having an increased storage capacity is critical in an
apparatus which is to be placed downhole and left for
extended periods of time without having ~he information
5 immediately transmitted to the sur~ace. Because monitoring
which needs to be done ;n a downhole environment might
extend over several hours or days, a large storage capacity
is needed to retain all the necessary samples required to
per~orm the analyses which are to be made with the infor-
20 mation as known to the art.
The specific bit-by-bit technique for using the memory
in the downhole environment is important to prevent lost
information and, therefore, to prevent lost time and money
in ob-taining valid samples. Knowing those locations within
2 5 a memory device which are inoperable at the time the memory
is made or subsequently tested, but prior to introducing it
into the downhole environment, is advantageous so that, once
_5_
the device is downhole, information will not be written
into, and thus not b~ los~ from, ~uch bad locations, pre-
venting lost time and money in obtaining valid samples.
Although there are several types of gauges which have
S been proposed or used for recording information in a
downhole environment, we are not aware of one which meets
each of the foregoing needs in a single apparatus.
Summary of the Invention
o The present invention overcomes the above-noted and
other shortcomings of the prior art by providing a novel and
improved self contained downhole gauge system.
The self-contained downhole gauge system of the present
invention includes both software and hardware monitoring of
~5 changes in the sampled parameter or condition. The software
control is also responsive to remaining battery life and
memory capacity. The present invention utilizes a plurality
of transducer interface means so that any of several commer-
cially available transducers having different outputs can be
20 interfaced to the remainder of the present invention. The
present invention also utilizes a selectable one of a semi-
conductor memory or a magnetic core memory, which magnetic
core memory is tested for inoperable locations and is
addressed bit-by-bit. The present invention also includes a
25 plurality of different electronic circuits which can be
separately or independently powered up and powered down to
conserve the internal power supply. The present invention
--6--
also includes means by ~hich different resolutions can be
selected dependent upon correspondin~ly selected sample
rates. A watchdog circuit is also included to oversee the
operation of the microprocessor to insure that it is
S operating within a selectable timing period.
The present invention described herein includes a
housing having three sections linearly and releasably inter-
connected. The invention also includes a selectable one of
a plurality of transducer interface means, connected to one
o or more transducers which detect the environmental con-
ditions to be monitored, for converting the type of output
received from the respective transducers into respective
electrical signals having a predetermined format regardless
of the transducers used. In the preferred embodiment this
15 format includes a characteristic such as frequency
corresponding to the magnitude of the sampled parameter.
The selected one of the plurality of transducer interface
means is disposed in a first section of the housing. The
invention further includes microcomputer means, disposed in
23 a second section of the housing, for receiving the electri-
cal signals from the selected one of the transducer inter-
face means in the first section of the housing, for deriving
from the electrical signals digital signals and for storing
the digital signals within the invention. Furthermore, the
25 invention includes power supply means, disposed in the third
section of the housing, for providing power to the trans-
ducer Interface means and the microcomputer means.
_7
The microcomputer means includes various circuits which
are independently energizable in responsa to different
switchable power signals provided by respective power switch
means. The power signals are provided at at least one
5 voltage level.
One of these electrical circuits defines a conversion
means including a primary counter means for providing digi-
tal counts in response to a characteristic of the electrical
signals from the transducer interface means, and it also
includes resolution timing counter means, respons ve to the
electrical signals for providing a plurality of count timing
signals, each of the count timing siynals designating a dif-
ferent length of time. The conversion means also includes
multiplexer means, having lnputs conn~cted to the resolution
~5 timing counter means for receiving the plurality of count
timing signals and having an output, for selectably con-
necting one of the inputs, and the respective one of the
plurality of timing signals connected thereto, to the output
so that the different counting periods of the primary
20 counter means are selectable. The conversion means still
further includes means for connecting the output of the
multiplexer to the primary counter means so that the primary
counter means is disabled when the respective timing signal
connected to the selected input of the multiplexer means is
25 provided to the primary counter means.
The circuits also comprise counter means for generating
a sequential digital output in response to a first clocking
L~
--8--
signal, which counter means has reset input means for
receiving a reset signal which resets the counter means to
an initial count. ~ second clocking signal drives a pro-
cessor me~ns or periodicall~ generating a re~et ~ignal to
the reset input means. The processor means has a processor
reset input. The circuits also include means, connected
between the counter means and the processor reset input and
responsive to the sequential digital output of the counter
means r for resetting the processor means when the reset
signal is not generated by the processor means and received
by the reset input means within a preselected count of the
sequential digital output o~ the counter means.
In accordance with the inven-tion-there is also provided
a memory gauge for obtaininy information pertinent -to an
environmental condition i.n a well bore. The memory gauge
comprises means for repe-titively sampling the environmen-tal
conclition in the well bore at sample rate in-tervals so that
inEormation pertinent to -the environmental condition is
ob-tained in correspondence with the sampling; and circuit
means, connected wi-th the sampling means, for causing the
sampling means to sample the environmental condition to
ob-tain informa-tion pertinent thereto whenever the environ-
mental condition changes at a rate passing a prede-termined
threshold irrespec-tive of the sample rate intervals, the
circuit means including: (a) means for sensing the environ-
mental condition and for providing an electrical signal
having a characteristic which changes with changes in the
-8a-
environmental condition; (b) means for defining a rate-of-
change threshold and for determining, in response to the
electrical signal and the characteristic thereof, whenever
the environmental condition changes at a rate passing -the
defined rate-of-change threshold irrespective of the sample
rate intervals; and (c) means, responsive to the means (b),
or providing a con-trol signal to the sampling means to
cause the sampling means to sample the environmental
condition.
Therefore, 'rom the foregoing, it is a general object
of the present invention to provide a novel and improved
self-con-tained downhole gauge system. Other and further
objects, features and advantages of the present invention
will be readily apparen-t to those skilled in the art when
the following description of the preferred embodiment is
read in conjunc-tion with -the accompanying drawings.
srief Description of the Drawings
FIG. 1 is a schematic illustration of a self-contained
downhole gauge of the present inven-tion shown in a downhole
loca-tion and, in dot-dash lines, in a surface location con-
nected by an interface to a computer.
FIGS. 2A and 2B are a block diagram of the in-terface
and computer system shown in FIG. 1 and of the downhole gauge
~.2~
which is shown to include a transducer section, a
controller/power converter and control/memory section, and a
battery section.
FIG~ 3 is a schematic circuit diagram of the preferred
S embodiment of the temperature VCO circuit shown in FIG~ 2 as
forming part of the transducer section.
FIG~ 4 is a schematic circuit diagram of the preferred
embodiment of the pressure VCO circuit shown in FIGo 2 as
forming part of the transducer section.
3 FIG~ 5 is a schematic circuit diagram of the preferred
embodiment of the ~P circuit shown in FIG~ 2 as forming part
of the transducer section.
FIG~ 6 iS a schematic circuit diagram of the preferred
embodiment of a +10-volt reference circuit contained within
S the transducer section.
FIG~ 7 is a schematic circuit diagram of an alternate
embodiment of the QP circuit.
FIG~ 8 is a schematic circuit diagram of another alter-
nate embodiment of the ~P circuit.
FIG. 9 is a schematic circuit diagram of still another
alternate embodiment of the ~P circuit.
FIGS~ lOA-lOC are a schematic circuit diagram of the
preferred embodiment of a central processing unit circuit of
the controller portion of the controller/power converter and
2s control/ memory section.
FIGS~ llA and llB are a schematic circuit diagram of the
preferred embodiment of a real-time clock circuit of the
--10 -
controller portion of the controller/power converter and
control/memory section.
FIG. 12~ is a schematic circuit diagram of the preferred
embodiment of a data recording module interface circuit of
5 the controller portion of the controller/power converter and
control/ memory sectlon.
FIG~ 12B is a schematic circuit diagram of the preferred
embodiment oE a power switching, ~P interrupt power-up, time
- interval power-up and watchdog timing circuit oE the
~ controller portion of the controller/power converter and
control/memory section.
FIGS~ 13A-13C are a schematic circuit diagram of the
preferred embodiment of a frequency-to-binary conversion
circuit of the controller portion of the controller/power
15 converter and control/memory section.
FIG. 14 is a s~hematic circuit diagram of ~he preferred
embodiment of a ~5-volt regulated power circuit of the power
converter and control portion of the controller/power con-
verter and control/memory section.
23 FIGo 15 is a schematic circuit diagram of the preferred
embodiment of a DC to DC converter for CMOS logic voltaget~VSUPPLY) and transducer section voltage (~ 15-volt) power
sources of the power converter and control portion of the
controller/power converter and control/memory section.
25 FIG~ 16 is a schematic circuit diagram of the preferred
embodiment of a controllable interconnection circuit for the
15voltage source of the power converter and control portion
17~
--11--
of the controller/power converter and control/memory sec-
tion.
FIG. 17 is a schematic circuit diagram o the preferred
embodiment of a memory power circuit of the power converter
5 and control portion of the controller/power converter and
control/memory section.
FIG. 18 is a schematic circuit diagram of the preferred
embodiment of an addressing/interface circuit of the memory
portion of the controller/power converter and control/memory
10 section~
FIGS. l9A-l9c are a schematic circuit diagram of the
preferred embodiment of a semiconductor memory circuit of
the memory portion of the controller/power converter and
control/memory section.
I 5 FIG. 20 is a schematic circuit diagram of the preferred
embodiment of a magnetic core memory circuit of the memory
portion of the controller/power converter and control/memory
section.
FIG. 21 is a perspective view o~ the magnetic core
20 memory shown in an unfolded configuration.
FIG. 22 is an exploded view showing the magnetic core
memory in partially Eolded configuration between its upper
and lower housing parts.
FIG. 23 is a schematic illustration of an eight by eight
2 5 memory array.
FIG. 24 is a diagram of a pressure graph exemplifying
pressure within a well bore over time.
-12-
FIGS. 25A-25B disclose a flow chart oE the preferred
embodiment of a sample rate change control program which
responds to software-detected changes in the monitored con-
ditions as well as to hardware-detected rapid pressure
5 changes.
FIG. 26 discloses a flow chart of the preferred embodi-
ment of a sample rate modification program for modifying the
sample rate in response to a low battery indication or a
substantially full memory indication.
o FIG. 27 discloses a flow chart of the preferred embodi-
ment of a power control program by which samples of the
monitored conditions are ob~ained, formatted, and recorded.
FIG. 28 discloses a flow chart of the preferred embodi-
ment of a program for generating at least one programming
5 pulse to record information in the semiconductor memory of
the present invention.
FIG. 29A discloses a flow chart of the preferred embodi-
ment o~ a scheduled sleep time program by which the present
invention can be preprogrammed to de-energi~e itself at
2~ scheduled times for conserving electrical energy.
FIG. 29B discloses a flow chart of the preferred embodi-
ment of an unscheduled sleep time program by which the pre-
sent invention can turn itself off dependent upon how much
time there i5 until the next sample is to be taken for also
2 5 conserving electrical energy.
FIG. 30 discloses a flow chart of the preferred embodi-
ment of a magnetic core memory test program by which the
sink/drive transistor pairs are tested for operability.
-~3-
FIG. 31 discloses a flow chart o~ the preferred embodi-
ment of a failure isolation program re~erred to in FIG. 30.
FIGS. 32A-32C disclose a flow chart of the preferred
mbodiment of a system control program.
It will be noted that FIG., 6 is on the same sheet as FIG. 3,
FIG. 16 is on the s~me sheet as, FIG. 14, FIG. 19C is on the same
sheet as FIG. l9A and FIG. 25B is on the same sheet as FIG. 24.
Detailed DescriDtion of the Preferred Embodiments
FIG. 1 shows a self-contained downhole gauge 2 disposed
in a well bore 4 by a suitable hoisting or tool carrier
means 6 of a type as known to the art. For example, the
means 6 can be a wire line (although there are no electrical
communications over the wire line between the surface and
the downhole l,ocation of the gauge 2 in the preferred embo-
diment) or a drill string of which the gauge 2 is a part andwhich is raised and lowered such as by the draw works and
traveling bl,ock as known to the art. The self-contained
gauge 2 is constructed in accordance with the preferred
embodiment as will be more particularly described h~rein-
below with reerence to the remaining drawings.
FIG. 1 also shows, in dot-dash outline, the gauge 2
located at the surface and connected by an electronic inter-
face 8 to a computer system 10. Because in the preferred
embodiment communications do not occur between the surface
and the gauge 2 when the gauge 2 is located in the well bore
4, the interface 8 and the computer system,10 are used to
communicate with the gauge 2 when it is at the surface.
Such co~nunications can occur, prior to lowering the gauge 2
-14-
into the hole, for the purpose of entering information or
presetting variables within the gauge 2 or, after the gauge
2 has been withdrawn or extracted from the well bore 4, for
reading the stored information from the gauge 2 into the
5 computer system 10 50 that the information can be analyzed,
for example.
FIGS. 2A and 2B show, in block diagram format, elements
comprising the preferred embodiment of the gauge 2, the
interface 8 and the computer system 10. The preferred embo-
~ diment of the gauge 2 is made of three detachable segmentsor sections which are electrically and mechanically inter-
connectible through multiple conductor male and female con-
nectors which are mated as the sections are connected.
These three sections are contained within respective
~5 linearly interconnectible tubular metallic housings of
suitable types as known in the art for use in downhole
environments. As illustrated in FIG. 1 and more par-
ticularly shown in FIGS. 2A and 2B, the three sections of
the gauge 2 include ~1) a transducer section 12, (2) a
2 controller/power converter and control/memory section 14
comprising controller and power converter and control por-
tion 14a and a data recording module including an
interchangeable semiconductor memory portion 14b or magnetic
core memory portion 14c, and (3) a battery section 16.
25 Various types of a plurality of specific embodiments of
the transducer section 12 can be used for interfacing the
gauge 2 with any suitable type of transducer~ regardless of
--15--
type of output. In the preferred embodiment, suitable
transducers include a CEC pressure-sensing strain gauge with
a platinum RTD, a HewlettPac~ard ~813B quartz pressure probe
with temperature sub, a Geophysical Research Corporation
EPG-520H pressure and temper~tura transduc~r, and ~ Well
Test Instruments 15K-001 quartz pressure and temperature
transducer. However, regardless of the specific construc-
tion used to accommodate the particular output of any speci-
fic type of transducer which may be used, the preferred
o embodimen. of the transducer section 12 includes a temper-
ature voltage controlled oscillator circuit 18 which
receives the output from the particular type of temperature
transducer used and converts it into a suitable predeter-
mined format ~such as an electrical signal having a fre-
lS quency proportional to the magnitude of the detectedcondition) for use by tne controller portion in the section
14 of the gauge 2. The preferred embodiment of the trans-
ducer section 12 also includes a pressure voltage controlled
oscillator circuit 20 for similarly interfacing the speciEic
20 type of pressure transducer with the controller portion o~
--- the section 14. Associated with the pressure voltage con-
trolled oscillator circuit 20 in the preferred embodiment is
a del-ta pressure (~P) circuit 22 which provides hardware
monitoring oE rapid pressure changes and which generates a
~5 control signal in response to positive or negative pressure
changes which pass a predetermined threshold. These three
circuits, along with a voltage reEerence circuit contained
* Trademark
.. , . . . . . .. :
t- A
-16-
in the transducer section 12, will be described in more
detail hereinbelow with reference to FIGS. 3-9.
The controller portion of the controller/power converter
and control/memory section 14 includes a central processing
5 unit circuit 24, a real time clock circuit 26, a data
recording module inter~ace circuit 28 and a frequency-to-
binary converter circuit 30, which elements generally deine
a microcomputer means for receiving electrical signals in
the predetermined format from the transducer section 12, for
o deriving from the electrical signals digital signals corre-
lated to a quantification of the magnitude of the detected
parameter and for storing the digital signals in the memory
portion of the section 14. These our circuits communicate
with each other over a suitable bus and suitable control
5 lines generally indicated in FIG. 2 by the reference numeral
32. The central processing unit circuit 24 also com-
municates with the computer system 10 through the interface
8 as indica~ed by the commonly labeled interface lines shown
in FIG. 2B. The central processing unit 24 also communi-
20 cates, through a part of the circuitry contained on the cir-
cuit card on which the data recording module interace
circuit 28 is mounted, with the transducer section 12 to
receive an interrupt signal generated in response to the P
signal from the ~P circuit 22~ The frequency-to-binary con-
25 verter circuit 30 also communicates with the transducer sec-
tion 12 by receiving the temperature and pressure signals
from the circuits 18, 20, respectively. The circuit 30 con-
~L~ 7
. -17-
verts these signals into digital signals representi.ng num-
bers correspondiny to the detected magnitudes oE the
respective environmental condition. The real time clock
circuit 26 provides clocking to variably control the opera-
5 tive periods of the central processing unit 24. The datarecording module interface circuit 28 provides, under
control by the central processing uni.t 24, control signals
to the memory portion of the section 14. Each of the cir-
cuits 24, 26, 28, 30 will be more particularly described
hereinbelow with reference to FIGS. lO, 11, 12 and 13,
respectively.
The power conver-ter and control portion of the section
14 includes circuits for providing electrical energy at
variously needed DC voltage levels for activating the
lS various electrical components within the gauge 2. This por-
tion also includes an interconnect circuit for controlling
the application oE at least one voltage to respective por-
tions of the gauge 2 so tha-t these portions of the gauge 2
can be selectively powered down to conserve energy of the
20 batteries in the battery section 16. The specific portions
of the preferred embodiment of the power converter and
control portion will be described hereinbelow with reference
to FIGSo 14-17.
The data recording module or memory portion of the sec-
25 tion 14 includes either the semiconductor memory portion 14b
or the magnetic core portion 14c or a combination of the
two. Each oE these portions includes an
18-
addressing/interface, or memory decoders and drivers, sec-
tion 34. ~he semiconductor memory portion 14b further
includes four 64K x 8 (K=1024) arrays of integrated circuit,
solid state semiconductor memory. These are ~enerally indi-
5 cated by the reference numeral 36 in FIG. 2A. A 21-VDC
power supply 38 is contained within the portion 14b for pro-
viding a programming voltage for use in writing information
into the memory 36. The magnetic core memory portion 14c
includes a 256K x 1 array of magnetic core memory generally
o identified in FIG. 2A by the reference numeral 40. These
elements of the memory portion will be more particularly
described hereinbelow with reference to FIGS. 18-23.
The battery section 16 shown in FIG. 2A includes, in the
preferred embodiment, a plurality of lithium-thionyl
5 chloride or lithium-copper oxyphosphate, C-size cells.
These cells are arranged in si~ parallel stacks of four
series-wired cells. Two of these stacks are shown in FIG.
2A and identified by the reference numerals 42a, 4~b. Each
series is protected by a diode, such as diodes 44a, 44b
20 shown in FIG. 2A, and each parallel stack is electrically
connected to the power converter and control portion through
a fuse, such as fuse 46 shown in FIG. 2A. In the preferred
embodiment the parallel stacks are encapsulated with a high
temperature epoxy inside a fiber glass tube. These battery
25 packs are removable and disposable, and the packs have wires
provided for voltage and ground at one end oE the battery
section. The batteries are installed in the gauge 2 at the
time of initialization of the gauge.
-19-
The portions of the gauge 2 are shown in FIGS. 2A-2B to
communicate with each other with the various power, control
and data signals shown between the respective portions.
FIGS. 2A-2s should be viewed with FIG. 2A placed to the left
5 of FIG. 2B so that the signals between portions 14a and 14b
match.
The interface 8 through which the gauge 2 communicates
with the computer system 10 comprises suitable circuitry as
would be readily known to those skilled in the art for con
o verting the signal lines specified in FIG. 2B into the
appropriate format recognizable by the computer system 10.
In the preferred embodiment this conversion is from the
designated input signals at the inputs of the interface 8 to
suitable IEEE-488 standard interface format output signals
15 a-t -the outputs of the interface 8. The input lines to the
interface 8 are generally identified by the reference
numeral 48 and the IEEE-488 output is designated by the
block marked with the reference numeral 50. The preferxed
embodiment is also capable of converting the input signals
20 into ~S-232 standard format. Broadly, the interface 8
includes an 8-bit parallel data bus and four hand shake
lines. The four hand shake lines are referred to as in-
strobe (INSTB), out-strobe (~ , in-strobe acknowledge
(INSTBACK), and out-strobe acknowledge (OUTSTBACK). As data
2s are placed onto the data bus, an in-strobe or out-s-trobe is
indicated; and after the data are read, an in-strobe
acknowledge or an out-strobe acknowledge is provided. The
-20-
SPAC signal shown in FIG~ 2B is provided by the intexface 8to indicate that the gauge 2 is connected to the interface
8. The ~STPWR signal shown in FIG. 2~ is generated by the
interface 8 to "wake-up" the gauge ~. These last two
5 signals are shown elsewhere in the drawings to indicate
their uses. In an alternate embodiment the interface 8 can
be made an integral part of the gauge 2.
The computer system 10 of the preferred embodiment with
which the interface 8 communicates is a Hewlett-Packard
~ Model 9816 or Model 9~26 microcomputer with a
Hewlett-Packard Model 2921 dual disk drive. The microcom-
puter is labeled in FIG. 2B with the reEerence numeral 52
and the dual disk drive is labeled with the reference
numeral 54. Suitably associated with the microcomputer 52
15 in a manner as known to the art are a printer 56, a keyboard
58 and a plotter 60. Although not part of the presently
claimed invention, it is contemplated that the computer 52
can be programmed to perform sevexal functions related to
the use of the gauge 2. An operator interface program
20 enables an operator to control the operation of the computer
through simple commands entered through the keyboard 58. A
test mode program is used to test the communication link
between the computer 52 and the interface 8. A tool test
mode program provides means by whlch the operator can test
Z5 the gauge 2 to verify proper operation. A received data
mode program controls the interface 8 to read out the con-
tents of the memory of the gauge 2; after the memory has
'7~
-21-
been read into the interface 8, the information is
transmitted to the computer 52 with several different veri-
fication schemes used to insure that proper transmission has
occurred. A write data mode program within the compu~er 52
5 automatically writes the data received from the interface ~
to one or both of the disks as an ASCII file so that it may
be accessed by HPL, sasic, Pascal, or Fortran 77 programming
languages. A set-up job program allows the operator to
obtain various selectable job parameters and pass them to
lD the interface 8. A monitor job program a,llows the operator
to monitor any job in progress~
Under control of the aforementioned programs in the com-
puter 52, several programs can be run on a microprocessor
within the interface 8. A core memory test program in the
5 gauge 2 reads and writes, under control from the interface
8, a memory checkerboard pattern to read and verify proper
operation of the magnetic core memory in the gauge 2 when it
is connected to the interface 8 and to maintain a list of
any bad memory locations detected. A proce~sor check
2D program checks the status of a microprocessor within the
gauge 2, and a battery check program checks the voltage of
the power cells in the gauge 2 to insure proper voltage for
operation. A tool mode select program places -the gauge 2 in
the proper mode for the test being run, and a set-up job
2 5 program further configures the gauge 2 for the ~ob to be
run. A core memory transfer program reads the contents of
the memory of the gauge 2 and stores that information in
7~1
-22-
memory within the inter~ace 8 prior to transfer to the com-
puter 5~.
Through the use of the foregoing programs, the tool
operator initializes the gauge 2 prior to lowering the gauge
S 2 into the well bore 4. In the preferred embodiment the
operator initializes the gauge 2 using a pre-defined
question and answer protocol. The operating parameters,
such as sampling mode, test delay times, serial numbers of
the individual instruments, estimated testing time and a
self-test or confidence test, are established at initializa-
tion and input through the question and answer protocol.
The sampling rates for sampling the pressure and temperature
and the corresponding resolution control information are
entered in a table by t~e operator at this initialization;
the specific sampling rate and resolution used by the gauge
at any one time are automatically selected from this table
as subsequently described hereinbelow. In the preferred
embodimentl the sampling mode to be selected is either a
fixed time interval mode, wherein the sampling occurs at a
20 fixed time interval, or a variable time interval mode,
wherein the particular sample rate is selected from the
table based upon a software detected change in the pressure
sensed by the pressure transducer.
After the downhole test has been run and the gauge 2 has
25 been removed from the well bore 4, the tool operator con-
nects the tool 2, specifically the memory portion, with the
interface 8 to read out the temperature, pressure and time
-23-
data stored w_thin the memory section 14b or 14c. Through
another question and answer protocol and other suitable
tests, the operator insures that the gauge 2 is capable of
outputting the data without faults. When the data is to be
5 read out, it is passed through the inter~ace 8 to the com-
puter system 10 for s-torage on the disks within the disk
drive 54 for analysis.
Although -the interface 8 and the computer system 10 form
parts of the overall system of which the gauge 2 is also a
o part, they do not form parts of the present claimed inven-
tion directed to the gauge 2.
With the foregoing general description of the present
invention, a more detailed description of the elements of
which the gauge 2 is comprised will be given with reference
~5 to FIGS. 3-32.
The preferred enbodiment of the tamperature voltage con--
trolled oscillator circuit 18 providing the temperature
transducer interface circuit for the preferred embodiment is
shown in FIG. 3. This circuit includes a comparator 62
20 having an inverting input to which a suitable temperature
sensor 64 is connected. The comparator 62 has a non-
inverting input to which an R-C charging circuit, comprising
resistors 66, 68 and capacitors 70, 72, is connectedO The
comparator 62 has an output connected to a trigger input of
25 a one-shot device 74~ The voltage at the inver-ting input oE
the comparator 62 is determined by the resistance of the
temperature sensor 64, which resistance is a function of the
-24-
temperature detected by the transducer. The voltage at the
non-inverting input of the comparator 62 charges Erom zero
volts through the charging R-C circuit comprising the ele-
ments 66-72. When the charging voltage at the non-inverting
5 input rises to the voltage determined by the resistance of
the transducer 64 ~and a resistor 76 ~onnected between the
transducer and the ~15SW-volt source), the comparator 62
triggers the one-shot 74. Triggering of the one-shot 74
generates a fixed width pulse through a transistor 78. The
transistor 78 is coupled, through a suitable mechanical and
electrical connector such as previously mentioned, to the
controller/power converter and control/memory section 14.
Triggering of the one-shot 74 also actuates a transistor 80
through which capacitors 70, 72 are discharged to reset the
15 comparator 62 so that it can be retriggered when the
charging voltage again rises to the voltage determined by
the resistance of the transducer 64. The fr~quency at which
the triggering of the one-shot 74 occurs as a result oE this
action of the comparator 62, and thus the frequency of the
20 pulse train passed through the transistor 78, is inversely
proportional to the temperature detected by the tran~ducer
64. The transistor 78 provides a low-power CMOS logic
interface between the transducer section 12 and the section
14. These components shown in FIG. 3 are energized by the
25 +15-volt switched source (~15SW, -15SW), shown in FIG. 16,
of the power converter and control portion of the section 14
so that these elements can be selectably powered up and
powered down as subsequently described hereinbelow.
. -25-
The preEexred embodiment of the pressure voltage
controlled oscillator circuit 20 providing the pressure
transducer interface circuit for the preEerred embodiment is
shown in FIG. 4. This preferred embodiment is for use with
S a strain gauge type of transducer. This transducer is con-
nected to the non-inverting inputs of differential ampli-
fiers 82, and the transducer is continually energized by a
constant +15-volt source (see FIG. 15) so that the trans-
ducer is continuously responsive to the pressure in the well
~ bore. The outputs of these differential amplifiers are pro-
vided to the inputs of an amplifier 84. The amplifiers 82,
84 provide a precision differential to ~ingle-ended
amplifier circuit. The output of the amplifier a4 is con-
nected to the non-inverting input of a positive feedback
~5 integrator 86. The output signal from the integrator 86
slews toward ~10 volts at a rate set by the output of the
amplifier 84. This output signal is input into the non-
inverting input of a comparator 88. When the comparator 88
is tripped in response to the output signal from the
20 integrator 86, this triggers a one-shot device 90. The one~
shot 90 provides a fixed-width pulse through a transistor 92
interfacing with the controller/power converting and
control/ memory section 14. The one-shot 90 also drives a
transistor 94 to discharge capacitors 96, 98 forming part of
25 the integrator 86. As with the temperature voltage
controlled oscillator circuit 18, the pressure voltage
controlled oscillator circuit 20 provides in the preferred
-26-
embodiment a CMOS logic interface by means of the transistor
92. The circuit 18 is also primarily powered in response to
the ~15SW and -15SW switchable power signals shown in FIG.
16.
An analog ground (ANALOG GND) for use with the frequency
signals coming from the transducer section 12 is provided as
shown in FIG. 2B~ This is the connection for the signal
returns labeled in FIGS. 3-5.
The ~P circuit 22 of the preferred embodiment is shown
in FIG. 5. Pressure pulses, such as would occur when there
is rapidly changing pressure within the borehole fluid, are
received by a pressure transducer to which the ~P circuit 22
is connected. In the preferred embodiment this pressure
transducer is the continuously energized strain gauge
5 pressure transducer to which the pressure voltage controlled
oscillator circuit 20 is also connected. However, a
separate, auxiliary pressure measuring device can be used.
In the illustrated preferxed embodimen~, the strain
2D gauge transducer is AC-coupled through capacitors 100, 102
to the input of a differential amplifier 104. The output of
the amplifier 104 is connected to a positive sensing com-
parator 106 and a negative sensing comparator 108 so that
both positive and negative-going pressure pulses are
25 detected. Level translating pulse output circuits 110, 112
are connected to the outputs of the comparators 106, 108,
respectively. These circuits 110, 112 are commonly con
-27-
nected to an input of a one-shot device 114. When either of
the comparators 10~, 108 detects a suitable pressure change,
as indicated by the output from the amplifier 104 passing
one of the respective thresholds of the comparators 106,
5 108, the respective one of the output devices 110, 112 acti-
vates the one-shot device 114 to generate a time~ pulse
which is interfaced to the section 14 through a transistor
116. In the preferred embodiment, the differential
amplifier 104 responds only to rapidly time-varying pressure
~ signals slewing on the order of 100 psi per second or
greater with peak changes of 300 psi or greater; however,
other pressure changes, and even changes in other environ-
mental conditions, can be used and remain within the scope
of the present invention. These elements are continuously
5 energi~ed from the constant ~i.e., unswitched) +15-volt
source shown in FIG. 15 so that the ~P circuit 2~ is con-
tinuously monitoring for rapid pressure changes.
Features of the ~P circuit 22 of particular note include
the AC-coupling which prevents interference by the ~P cir-
20 cuit with the precision transduction of steady or slowlyvarying pressures which are to be detected by the circuit 20
shown in FIGD 4. The AC-coupling also makes the ~P circuit
22 responsive only to large, rapidly slewing pressure
changes. Being bipolar, the circuit 22 responds to both
25 increasing and decreasing pressures. The circuit is also
constructed of devices which are low in power consumption.
Through the use of the ~P circuit, re-enabling signals are
-28-
provided to the gauge 2 to "wake-up" the gauge, if it has
been powered down into a sleep mode to conserve energyr to
cause the controller portion to take a new sample irrespec-
tive of the software implemented sample rate interval. This
signal is also used within the controller portion of the
section 14 to cause the software to use the fastest sample
rate. These last two features are further described herein-
below.
FIGS. 7-9 show alternate embodiments of circuits which
can be used for detecting rapid pressure changes. Each of
these circuits is directed to a piezoelectric pressure sen-
sor which is an extremely low power consuming device. In
FIG. 7, a piezoelectri~ pressure sensor 118 converts
detected pressure into corresponding electrical signals. A
15 high pass filter, comprising a capacitor 120 and a resistor
122, passes only rapidly changing signals from the sensor
118 to an amplifier 124. The amplifier 124 converts the
electrical signals passed by the high-pass filter to a digi-
tal format for controlling a latch element 126. When a
20 suitable high frequency signal is generated by the sensor
118 and passed through the amplifier 124, the latch element
126 generates a signal which makes a transistor 128 conduc-
tive for connecting the load (such as circuits within the
gauge 2) to a voltage source, +V. A signal labeled
25 "shutdown" in FIG. 7 can be generated (such as by the
controller portion of the gauge 2) to reset the latch ele-
ment 126 and turn off the transistor 128, thereby dis-
-29-
connectiny~ or shutting down, the operation of the load 130.
The shutdown signal can be generated by any suitable means.
The circuit shown in FIG. B is similar to the circuit
shown in FIG. 7 in that it includes a piezoelectric sensor,
identi~ied by the reference numeral 132, a high-pass filter
comprising a capacitor 134 and a resistor 135, an amplifier
138 and a latch element 140. ~owever, the capacitor 134 and
the resistor 136 are variable so that the '~rate of change in
pressure" set point can be adjusted in the FIG. 8 circuit.
The FIG. 8 circuit also includes a resistor 142 which can be
adjusted to control the amplitude set point at which a
suitable ~P pulse is to be detected by the amplifier 138.
The latch 140 is shown connected in a specific application
for providing an interrupt to a microprocessor and receiving
an interrupt acknowledge from the microprocessor.
FIG. 9 shows the same circuit illustrated in FIG. 8, as
indicated by like re-Eerence n~merals, except for the dif-
ferent application of the latch element 140 being connected
to an external alarm circuit 144 and being connected to a
push-button reset circuit 146 used to reset the alarm cir-
cuit 144.
In the ~P circuit 22, the sensitivity or thresholds o~
the detecting circuitry can be adjusted such as illustrated
in FIGS~ 8 and 9 or by other suitable means, such as
through analog switches, whose uses would be readily known
to those in the àrt.
The circuits 18, 20, 22 are analog circuits which are
energized by the ~15-volt sources, either constant or
-30-
switched as previously described, generated from the sec-
tions 1~, 16.
Also included in the transducer section 12 is a preci-
sion +10 voltage reference for use by the transducers~ The
preferred embodiment of this voltage reference circuit is
shown in FIG. 6. This circuit is continuously energized by
the constant ~15-volt source.
The schematic circuit diagram of the preferred embodi-
ment of the central processing unit circuit 24 of the sec-
tion 14 is shown in FIGS. lOA-lOC. In the preferred
embodiment this circuit is mounted on one printed circuit
card contained in the section 14 of the gauge 2. Generally,
the central processing unit controls the operation of the
gauge ~ once it is placed in the downhole position where
pressure and temperature are to be monitored. More par-
ticularly, in the preferred embodiment the central pro-
cessing unit controls and takes measurements from the
transducer section, compresses and stores the data in the
memory portion, controls the power management function, and
runs tool diagnostics throughout the time the gauge 2 is
downhole and records the results of the tests. At the sur-
face, the central processing unit also initializes the tool
with information received through the interface 8 (such as
initializing the gauge with any bad memory locations), and
it performs diagnostic testing upon initial energization
with the interface 8 connected and reports the results of
the testing to the interace 8.
`
~31-
Structurally, the central processing unit circuit 24
includes a microprocessor 148 of a suitable type. In the
preferred embodiment the microprocessor 148 is a low-power
CMOS circuit capable o functioning in the higil temperature
5 environments found in oil and--gas well bores. The timing at
which the microprocessor 148 runs is primarily provided by a
clock 150 of a suitable type. In the preerred embodiment
the cloc~ 150 provides a nominal one megahert~ timing
signal. The microprocessor 148 operates under the control
13 of suitable programs (see FIGS. 25-32) stored in an 8K x 8
read only memory 152 shown in FIG~ 10B and in response to a
processor reset signal, RESET, an interrupt signal, INT, and
a pressure change interrupt signal, ~PINT, provided to
respective inputs as shown in FIG. lOAo The microprocessor
~5 148 also responds to the end of count signal, EOC, and the
stop processing signal, WAIT/ during data monitoring and to
the SPAC interconnect and the INSTB and O~TSTBACK handshake
signals during communications with the lnterface 8~
A random access memory 154 capable of storing 128 8-bit
20 bytes of information is also shown in FIG. 10B; this memory
154 provides working storage space, such as for software
controlled registers, for use by the programs as would be
readily known to those skilled in the pertinent arts.
To permit 16-bit addressing, the central processing unit
~5 is also shown in FIG. lOA to include a high address byte
latch 156 which receives address signals over an address bus
157.
-32-
Latch elements 158, 160, 162 and channel selectors, or
decoders, 164, 166 shown in FIGS. lOA and lOB are used to
provide the various control signals designated in the
drawings. The SRFPSEL signal, which is used to select cir-
5 cuits in the interface 8, is provided from the decoder 166shown in FIG. lOB to the interface 8 as indicated in FIG. 2B
by the common label; the other signals from the latches 158,
160, 162 and the decoders 164, 166 are used elsewhere in the
gauge 2 as shown throughout the drawings by like labels.
A multiplexer 168 shown in FIG. lOA receives the various
designated signals previously described and selectably pro-
vides them to respective inputs of the microprocessor 1~8.
FIG. lOB also shows a tri-state buffer 170 which has an
input section powered by one power source through a conduc-
tor 172 and an output section powered by another power
source through a conductor 174. The power source connected
through the conductor 172 is switchable so that the input
stage of the latch 170 can be deactivated to conserve power
at selectabla times during the operation of the gauge 2 in
2D its downhole location. However, the source connected
through the conductor 174 is a continuous power supply so
that the outputs are always ready to receive information
once the gauge 2 is energized and so that the inputs of the
random access memory 154 are properly maintained. The power
25 supply for continuously energizing the logic circuits of the
controller portion of the section 15 is designated in FIG.
lOB and elsewhere throughout the drawings by the label
+VS~BY. The switchable power supply for the central pro-
cessing unit and other circuits shown in subsequent drawings
is designated throughout by the label +VCPU (other
switchable supplies will be described hereinbelow). The
random access memory 154 is powered by the continuous
source, +VSTBY, so that volatile information stored therein
is retained.
FIG. 10C shows a hex D-type latch 176 which receives
information over a data bus 178 from the microprocessor 148.
The latch 176 is clocked in response to the power select
(PWRSEL) and memory write (MWR~ control signals as indicated
in FIG. 10C. The latch 176 has five independently selec-
table outputs, each of which is connected to a respective
one of five transistors 180, 182, 184, 186, 188. The tran-
sistors 180, 182, 184 and 188 control additional transistors
190, 192, 194, 196, respectively, to define power switch
means for providing the respective selective power signals
labeled in FIG. 10C. The -~15MEM power signal, switchably
connectable to the memory portion of the section 14 as power
source signals +15Vl and ~15V2, is generated by the circuit
shown in FIG. 17; and the +VSU~PLY signal, switchably con-
nectable to respective digital circuits in the control por-
tion of the section 14 as the ~VDRM and +VFBC power source
signals, is the CMOS logic power source signal generated by
the circuit shown in FIG. 15. The transistor 186 is
controlled to provide a transducer power switch control
signal, XDRSW, to -the power switching circuit shown in FIG.
34-
16. The outputs of the latch 176, and thus the operation of
the transistors 180-192, are independently controllable by
the microprocessor so that selectable combinations of power
signals can be provided.
Each of the components in the central processing unit
circuit 24 shown in FIGS. 10A-10C are, in the preferred
embodiment, CMOS semiconductor members or otherwise com-
patible with CMOS circuitry so that power consumption is
reduced. This type o~ construction is used throughout the
gauge 2 to reduce the overall power consumption of the
electronic circuits. Suitable specific model types of such
elements are known to the art
The circuit diagram of the real time clock circuit 26 of
the section 14 is shown in FIGS. llA and llB. This circuit
5 is contained on one card in the controller section within
the gauge 2~ This circuit provides four timing OptiOIlS.
One is a real time option wherein the real time is initially
proyrammed at the surface by the interface 8 prior to the
gauge 2 being lowered into the well bore ~. Once downhole,
20 the real time function provides an elapsed time number which
is stored with each sample of the temperature and pressure
data so that the time of occurrence of the temperature and
pressure sample can be reconstructed at the surface. The
second timing option provides a wake-up signal, TIME, used
25 to automatically re-energize those portions of the gauge 2
which have been powered down after a selected time period,
entered from the central processing unit, has expired. In
the preferred embodiment, wake-up signals can be generated
within a range of 0 to 255 seconds o~ 0 to 255 minutes. The
third timin~ option is a iixed timing option wherein a fixed
timing signal is provided at one-second intervals; the
fourth timing option is a fixed timing option wherein a
fixed timing signal is provided at one-minute intervals.
Structurally, the real time clock circuit 26 includes an
integrated circuit timer 198 ~FIG. llB) which can be
programmed and con-trolled through data lines 200 and control
lines 202. Initialization of the timer 198 with the real
time is made at the surface by connecting the gauge 2 to the
interface 8 so that a write-enable interlock jumper within
the interface 8 is connected across normally open terminals
204 (FIG. llA). This closes the circuit to the wri-te input
(WR) of the timer 198, thereby enabling the timer 198 to be
programmed in response to the memory write signal and with
data transmitted over the data bus 178 from the micropro-
cessor 148. Transfers of data to and from the data lines
200 are made through an input buffer 206 and an output
buf~er 208, comprising tri-state elements, shown in FIG.
llA. The control lines 202 carry signals provided through a
latch 210 from the data bus 178. The latch 210 is con-
trolled by a signal from another tri-state buffer 212. FIG.
llA also shows a channel select member 214 (shown in two
parts) by which control signals are provided as shown in the
drawings.
Although the outputs from the timer 19~, as read over
the data lines 200, provide real time (more particularly,
~Z~i~L1'74
-36-
elapsed time in the preferred embodiment) information for
storage in the memory portion, one-second and one-minute
timing signals can also be taken from the data lines 200 for
selectably controlling a counter 216. The counter 216 can
be loaded with a preset count received over the data bus 178
from the microprocessor 148. Clocking of the counter 216
occurs over a line 218 coming from a multiplexer 220 into
which the one-second and one-minute signals are input. The
one of these two timing signals selected through the
multiplexer 220 is controlled by signals from a latch 222
which also receives inputs from the data bus 178. The latch
222 also provides time enable, TIMEEN, and delta pressure
enable, ~PEN, control signals ~used in the circuits shown in
FIG. l2s) in response to data bus signals from the central
processing unit. sy presetting the timer 216 with a selec-
table count, the TIME signal, a time period expiration
signal, is generated when the count is depleted in response
to the appropriate number of counts, or clock pulses, being
received over the line 218. This TIME signal is used to
generate "wake-up" signals so that power can be reapplied to
any powered-down sections tsee FIG. 12B).
FIG. 11~ shows that the timer 198 is clocked by a nomi-
nal 32-kilohertz signal from an oscillator 22~.
The timer 198, portions of the buffers 206, 208, 212,
the latch 210, the counter 216, the multiplexer 220, the
latch 222 and the oscillator 224 are continuously energized
by the continuous power supply, ~VSTBY, so that continuous
timing is maintained.
The schematic circuit diagram for the data recording
module inter~ace circuit 28, which is contained on a single
card within the section 14 of the gauge 2, is shown in FIG.
12A. FIG. 12A shows two tri-state buffers 226, 228 which
5 receive the indicated control signals from the central pro-
cessing unit. The output portions of the buffers 226, 228
are connected to the switchable ~VDRM power source shown in
FIG. lOC. The output of this same switchable po~er source
is supplied to the respective power inputs of a channel
13 selector 230, a latch 232, and a P-channel power switch chip
234, which chip 234 is operable by the central processing
unit to switch the +VDRM power signal, only after it in turn
has been switched on through the circuit in FIG. lOC, to its
outputs as the various VLOGIC power signals to be used to
5 energize the logic circuits in the data recording module
portion of the section 14. The outputs of these chips,
along with the data bus 178, are provided to the memory por-
tion of the section 14 as shown in FIG. 12A and FIGS. 2A-2B
by the common labels (the VLOGIC3 and VLOGIC4 signals are
20 spares in the preferred embodiment and are not shown in
FIGS. 2A-2B). Because these elements are powered by the
+VDRM power supply, they can be separately activated and de-
activated independently of the +VCPU and +VSTBY power sour-
ces.
The lower portion of FIG. 12A shows a transistor 236
which is responsive to the nominal 32-kilohertz signal from
the real time clock circuit 26. The output of the tran-
7f~
-38-
sistor 236 provides to the fre~uency-to-binary converter
circuit 30 an inverted nominal 32-kilohertz signal having a
magnitude between ground and the ~BC power source, which
power source is generated through the power switch circuitry
5 shown in FIG. lOC.
FIG. 12B shows a "watchdog" resetting circuit including
a counter 238 which is clocked by the inverted nominal
32-kilohertz signal from the real time clock circuit 26 to
provide a sequential digital output. The counter 238 is,
under normal operating conditions, continuously reset
through a reset input thereof by the KEEP ALIVE signal which
is generated by the central processing unit (see FIG. lOA)
and provided through an OR gate 240. A jumper 242 connected
at the outputs of the counter 238 is used to vary the length
of a processor reset time-out period. If no REEP ALIVE
signal is received by the counter 238 within the preselected
count defining the processor reset time-out period, the pro-
cessor reset signal/ RESET, is logically generated from the
count signal provided over a conductor 244 and through the
jumper 242. By appropriately connecting processor the
jumper 242, the length of time required before a processor
reset signal is generated can be varied. Regardless of
which length of time is selected by the jumper 242, the
central processing unit is programmed to periodically
generate the KEEP ALIVE signal, in response to the clock 150
(of different frequency than the nominal 32-kilohertz signal
clocking the counter 238) shown in FIG. lOA, at a rate which
-39-
is shorter than the jumper 242-selected time-out, or ter-
minal count, o~ the counter 238. Therefore, when the
central processing unit is operating within normal limits,
the counter 238 is continually reset before the time-out
period is counted by the counter 238. Should the central
processing unit begin to operate outside this time limit,
thereby indicating that the central processing unit has
started to malfunction, then the XEEP ALIVE signal will no
longer be generated within the selected time limit, whereby
the counter 238 will time-out by reaching the count detected
through the conductors 242, 244. This count is logically
combined by the logic gates shown in FIG. 12B to generate
the processor reset signal, R~SET, through the illustrated
transistor. Generation of the processor reset signal resets
the microprocessor 148 to which the counter 238 is connected
through the gates and transistor shown in FIG. 12B. To
disable the watchdog timer shown at the top o~ FIGo 12B when
the interface 8 is connected to the gauge 2, the SPAC signal
is connected to another input of the OR gate 240. The
watchdog timer is also disabled when the ~VCPU power signal
is not present because the counter 238 is energized by this
switcha~le power signal. Ther~ore, the watchdog timer is
not operational during sleep modes.
FIG~ 12B also shows the circuit by which the power-down
(sleep) and power-up (wake-up) signals for respectively
deactivating and activating the microprocessor 148 are
generated. A latch 2~6 is clocked by a GO TO SLE~P signal
~o~
--Ll O
generated by the central processing unit circuit 24 as shown
in FIG. lOA. The latch 2~6 is reset in response to any of
the labeled signals which are input into either of the O~
gates 248, 250 shown in FIG. 12~, including the power reset,
RSTPWR, signal generated by thP interface 8 to insure the
latch 246 is in a proper state~when 'he battery section 16
is attached because when this attachment occurs, the power
may fluctuate, causing the microprocessor to come-u~ ran-
aomly; therefore, the RSTPWR signal is provided to override
any GO TO SLEEP signal the mlcroprocessor may try to
generate upon attachment of the battery section 16. The
noninverted output (Q) of the latch 246 drives a transistor
252 that generates the W~IT control sigDal used to imme-
diately stop the microprocessor 148 shown in FIG. lOA. The
15 inverted output (~ of the latch 246 drlves a transistor 254
which in turn controls a ?ower switch transistor 256 t~rough
which the switchable +VCPU power source signal is provided
from the +VSUPPL~ signal. The constant logic circuit
energizing power signal, +VSTBY, is also shown in FIG. 12B
as being derived from the +VSUPPLY signal.
The lower portion of the circuit shown in FIG. 12B
includes two switch means for generating control signals to
the microprocessor 148. These include ~l) a latch 258
having an output used to control a transistor 262 for~pro-
25 viding a switchable ~P interrupt signal (~PINT) and ~2) atransistor 260 for providing a switchable interrupt signal
. .
'^8J~
(INT). Control of the transistor 260 occurs through the OR
gate 248 having one input connected to the output shown
logically derived Erom the AP and ~PEN signals. The gate
248 has another input connected to receive the inverted TIME
5 signal from the counter 216 shown in FIG. llB~ The latch
258 is clocked by the same ~P-responsive signal connected to
the first-mentioned input of the OR gate 248. The latch 258
is reset by an INTERRUPT RESET signal generated by the
microprocessor 148 as shown in FIG. 10A.
~ When the GO TO SLEEP signal is generated, the latch 246
actuates the transistor 252 to provide the WAIT signal to
suspend further operation of the microprocessor 148; and the
~VCPU signal is switched off. When either a time period
count in the counter 216 expires or the ~P signal indicates
5 a rapid pressure change has been detected, the latch 246 is
reset so that the WAIT signal is terminated and the +VGPU
signal is turned on. Additionally, the INT signal is
generated and causes the microprocessor to start a new
sample read. When the interrupt is caused by the ~P signal~
20 the ~PINT signal is also generated to advise the micro-
processor of the reason for the interrupt.
The schematic circuit diagram of the preferred embodi-
ment of the frequency-to-binary conversion circuit 30 is
shown in FIGS. 13A-13C. These circuits are contained on a
2 5 single card in the preferred embodiment. FIG. 13A shows
four tri-state buffers 264, 266, 268, 270 which receive the
indicated signals from the central processing unit circuit
. -42-
24 and provide them to the remainder oE the frequency-to-
binary conversion circuit 30 shown in FIGS. 13B and 13C.
FIG. 13A also shows a 5-megahertz reference clock oscillator
272 and a line 274 over which the inverted nominal
32-kilohertz signal from the data recording module interface
circuit 28 is provided. It is to be noted that the tri-
state buffers 264-270 have their outputs powered by the
switchable power source +VFBC whereas the inputs are powered
by the switchable source ~VCPU. The +VFBC power source is
used elsewhere in the frequency-to-binary conversion circuit
30 as shown in FIGS. 13B and 13C so that these portions can
be separately powerad up and powered down independently of
the +VCPU power source and the other independently
switchable power sources in the gauge 2.
FIGS. 13B and 13C show the circuitry by which the
pressure and temperature signals from the transducer section
12 are converted into binary counts used by the central pro-
cessing unit circuit 24 for storing the pressure and tem-
peratur~ information in the memory portion. A latch 276
receives multiplexer control information from the central
processing unit, through the circuits shown in FIG. 13A, for
controlling a multiplexer 278 and a multiplexer 280. The
principal information input into the multiplexer 278 inclu-
des the temperature and pressure signals Erom the transducer
section 12 and the inverted nominal 32-kilohertz signal
transferred by the conductor 274 shown in FIG. 13A. The
principal information input into the multiplexer 280 inclu-
Lt~
-43-
des resolution timing signals, deining different lengths of
xesolution timing intervals, taken from selected OUtplltS of
resolution timing counters 282, 284. The counters 282, 284
are clocked through a toggle latch 286 which is in turn
clocked by the selected one of the pressure, temperature or
inverted nominal 32-kilohertz signals passed through the
multiplexer 278. The selected resolution signal provided at
the output of the multiplexer 280 controls a latch 288
having an output which sets a latch 290 to stop or disable
1~
further counting or resolving oE the measured input selected
through the multiplexer 278.
Whichever input is selected through the multiplexer 278
and whichever resolution is selected through the multiplexer
280, the resolving occurring during the selected resolution
time is achieved by means of primary counters 292, 294.
These counters are clocked in response to the frequency of
the signal derived from the reference clock signal shown in
FIG. 13A as gated by the output oE the latch 290 through an
OR gate 297. The count accumulated by the counters 292, 294
i5 gated onto the data bus 178 through tri-state buffer
pairs 296a,b, 298a,b, 300a,b. These pairs of buffers are
controlled by respective control signals provided through a
channel selector, or decoder, 302 shown in FIG. 13B.
In an alternative embodiment, the counters 282, 284 can
be replaced by a programmable counter which is loaded by the
microprocessor and incremented by the selected transducer
signal. The output of such a programmable counter would
-44-
enable a counter, such as the counters 292, 294, which would
be directly driven by the reference clock.
The inverted nominal 32-kilohertz signal selected
through the multiplexer 27~ can be used for diagnostic pur-
5 poses to check the accuracy of the reference oscillator andthe reliability of the counters.
The circuits 24, 26, 28, 30 generally include digital
circuits which become operational when energized by the
switchable power signals previously described.
13 The power converter and control portion of the section
14 includes in the preferred embodiment the circuits schema-
tically illustrated in FIGS. 1~-17. FIG. 14 shows an
integrated circuit voltage regulator 302 which provides a
precision +5-volt source from the batteries in the battery
~5 section 16. This voltage level is used in the power cir-
cuits shown in FIGS. 15 and 17.
FIG. 15 shows the preferred embodiment schematic circuit
diagram of the CMOS logic power signal source, labeled
+VSUPPLY and used as the source for the non-switched logic
20 power signal +VSTBY and the switchable logic power signals
+VCPU, +VDRM and ~VFBC, and the ~15-volt source, used to
provide both the constant and switched power signals to the
transducer section 12. The circuit includes an oscillator
circuit 304 having an output which is divided by two through
25 a latch 306 that also provides squaring of the oscillating
signal. Another latch 308 provides another level of divi-
sion by two to further reduce the timing signal. The non-
-45-
inverted signal from the non inverted output of the latch
308 is provided through two NOR gates 310, 312 to a part of
a gate driver/level translator 314. The inverted signal
provided at the inverted output of the latch 30~3 is provided
5 through NOR gates 316, 318 into another part of the gate
driver/level translator 314. A transformer 320, energized
by the battery supply, is driven by the outputs Erom the
gate driver/ level translator 314 through transistors 322,
324 and their associated circuitry shown in FIG. 15. The
transformer 320 has one secondary winding 326 from which the
+15-volt sources are provided for use by the transducer cir-
cuit. The transformer 320 includes another secondary
winding 328 which provides the +VSUPPLY source used in the
CMOS logic circuits, which are operational throughout a
5 range of specified operating voltages as known to the art.
The NOR gates 310, 312, 316, 318 are controlled by a
pulse width modulator 330 comprising a one-shot 332 and an
R-C circuit 334. The one-shot 332 is actuated by a feedback
con~rol network 336 which compares a sample-of the ~VSUPPLY
20 source (labeled FB) to the +5 precision reference through a
comparator 338.
The +15-volt sources provided by the circuit shown in
FIG. 15 can be connected or disconnected, as the ~15SW and
-15SW power signals, to or from the transducer circuit,
2 5 under command of the XDRSW signal from the central pro-
cessing unit circuit 24, through the power switch circuit
schematically shown in FIG. 16. By controlling the logic
. -~6-
level of the ~DRSW signal applied to a control line 340, the
conductivi~y o~ transistors 342, 3~4, 3~ can be contro~led
to conduct or not conduct from the +15-volt sources, con-
nected at the input of the power switch circuit, to the
transducer section 12, connected to the output of the power
switch circuit.
The schematic circuit diagram of the preferred embodi-
ment of a +15-volt memory power source is sho~7n in FIG~ 17.
This circuit provides a self-oscillating DC-DC converter for
o converting the battery voltage to a ~15-volt level for use,
upon appropriate switchable operation of the power switch
transistors 190, 192 (FIG. lOC) having inputs to which the
memory voltage is supplied, by the memory programming power
supply within the memory portion of the section 14. The
~5 circuit of FIG. 17 includes a transformer 348 having a
center tap 350 to which the battery voltage can be
switchably connected through a transistor 352. A comparator
354 compares the +15-volt memory voltage source with a
sample of the +5-volt reference. When the +15-volt memory
20 power source drops to a lower limit, the comparator 354
turns on the transistor 352 to connect the battery voltage
to the center tap 350 of the transformer 348. When the
+15-volt memory voltage source reaches an upper limit, the
comparator 354 turns the transistor 352 off.
2 ~ The memory portion of the section 14 of the gauge 2
includes the circuits shown in FIGS. 18-20. FIG. 18 shows
the addressing/ interfacing circuit 34. This circui-t inclu-
'~Lf~
-~7-
des latches 356, 358, 360, 362 for retaining the memory
addresses. The memory addresses are entered into the
latches 356~362 over the data bus 178 after being passed
through buffers 364, 366 connected to the inputs of the
5 latches 356-362. This connection is made over a memory data
bus 368 which i5 made bi-directional through output buffers
370, 372. The memory data bus also is connected to a tri-
state latch circuit 374. Control of these circuits is made
through channel selectors, or decoders, 376, 378 and the
related circuits shown in FIG. 18. The circuit shown in
FIG. 18 is used to interface with either the solid state,
semiconductor memory schematically shown in FIGS. l9A-19C or
the magnetic core memory schematically shown in FIG. 20.
The designated VLOGIC power signals are used to energize the
15 memory integrated circuits and the ~ signals are used
to select memory sections~ These signals are shown in FIG.
12A with ending numerals. These numerals indicate usage
with diEferent ones of at least two sections of, for
example, the data recording module 14b. Therefore, these
20 signals are not numbered in FIGS. 18-19 because they could
be any of the numbered signals depending upon how many modu-
les are used.
The semiconductor memory shown in FIGS. l9A-l~C can be
used interchangeably with the magnetic core memory shown in
25 FIG. 20; however, in the preferred embodiment, the semicon-
ductor memory is considered an alternate memory to the
magnetic core memory which is particularly suitable for high
7~
-48-
temperature environments where low average power require-
ments are desirable. FIG. l9A shows that the semiconductor
memory includes 4-line to 16-line channel selectors 380, 3~2
for providing 32 select signals used to select a particular
5 one of the 32 units of semiconductor memory cells. The
channel selectors 380, 382 are controlled by means of infor-
mation provided over the memory data bus and memory address
lines shown in FIG. l9A. The selectors are responsive to
addresses which are selectable by appropriately strapping
I D address selector terminals 383.
FIG. l9B shows four of the possible 32 solid state semi-
conductor programmable read only memory chips which can be
used in the preferred embodiment of the module l~b. The
memory chips shown in FIG. 19B are labeled with the
~5 reference numerals 38~, 38Ç, 388~ 390. The four chips shown
in FIGu l9B represent one circuit board or unit of memory in
the preferred embodiment; thereforel this memory can be
expanded up to eight units of memory in the preferred embo-
diment.
20 FIG. l9C shows a schematic circuit diagram of a power
supply for generating the +21-volt programming voltage, VPP,
for programming the solid state, semiconductor memory. This
power supply draws from the -~15-volt memory power source
illustrated in FIG. 17, as switched through the circuitry of
25 FIG. 10C to become either +15Vl or ~15V2. As with the
VLOGIC and ~RMSEL signals, these ending numerals indicate
different modules 14b; therefore, no ending numerals are
shown in the single circuit illustrated in FIG. l9C.
~L~ 3~
_~9_
The magnetic core memory 40 is schematically illustrated
in FIG. 20. FIG. 20 shows a box 392 labeled "core memory
address and memory control registers." This includes the
same circuit shown in FIG. 18. The magnetic core memory
includes a core memory matrix with drivers identified in
FIG. 20 by the box 394. The memory matrix 394 includes the
actual non-volatile ferrite core elements in which the
information is stored. The construction of these elements
will be more particularly described hereinbelow with
reference to FIGS. 21 and 22. The core matrix 394 has sense
lines which are provided to sense amps and output latches
396. A memory register control circuit 398 is used to
control the writing and reading of the information into and
from the core memory matrix 394. The construction of these
elements shown in FIG. 20 are functionally of types as known
to the art. However, the mechanical structure of the core
memory matrix 394 and its utili~ation are important as will
be described with reference to FIGS. 21-23~
FIG. 21 shows a portion of the core memory matrix 3~4 in
an unfolded, planar configuration wherein the ferrite core
elements are distributed across and mounted on an articu-
lated mat comprised of six rectangular support members,
designated as strips 400, 402, 404, 406, 408, 410, of known
printed circuit board material pivotally interconnected
along their edges by flexible tape hinges. In the preferred
embodiment, the ferrite core elements provide 256K ~262,144)
bits of storage and are mounted on core planes comprising
~50~
s.ixteen .8-inch x 4.25-inch sections with four of these sec-
tions mounted on the strip 402 as designated by the
reference numeral 444, with four oE these sections mounted
on the strip 404 as designated by the re~erence numeral 4~,
5 with four of these sections mounted on the strip 406 as
designated by the reference numerals 448, and with the
remaining four sections mounted on the strip 408 as desig-
nated by the reference numeral 450, whereby the memory ele-
ments lie in different spatial planes when the mat is in a
o folded, stacked configuration as shown in FIG. 22. The
memory elements are mounted so that they lie on one side of
the articulated mat when it is in its unfolded, planar con-
figuration. This one side is defined by the substantially
continuous and aligned planar surfaces of the members
5 400-410. In the preferred embodiment the compact core
memory matrix 394 can store up to 5,000 samples and can be
further expanded.
When installed in the gauge 2, the core memory matrix
394 is folded along the seams connecting each adjacent set
20 of strips 400-410. This construction is illustrated in FIG.
22. When fully folded, the strips 400-410 overlie each
other so that overlying edges of the strips are substan-
tially aligned whereby the strips are confined within a
width and length equal to the width and length of the
25 longest or longer one of the strips 400-410 as is readily
apparent from FIG. 22; in the preferred embodiment this
space is sufficient to fit within the tool housing section
-51-
which includes a longitudinal cavity defined by an inner
cylindrical surface of the housing wall having a diameter of
less than one inch. The length of the folded mat is
approximately twenty-eight inches in the preferred embodi-
S ment. In this folded, stacked configuration, the corememory matrix 394 can be housed between and within the chan-
nels of two elongated, substantially C- or U-shaped housing
strips, or stiffener trays, 412, 414 connected by pins or
other retaining means, such as illustrated in FIG. 22 by
o screw 462, extending through holes 416, 418, 420, 422, 424
defined through the housing strip 412 and matching holes
formed through the strips 400-410 and the other housing
strip 414. Spacers of the type shown at 464 can be used to
separate the strips so that the facing circuits do not touch
each other. The spacers are retained along the pins between
adjacent ones of the members 400-410.
Although this folded array packs the core elements clo-
sely together, there is no temperature problem in the pre-
sent invention because the cores are not continually driven,
20 but rather are actuated only briefly during the write cycles
performed to store the pressure, temperature and time infor-
mation downhole. No reading from the memory or continual
accessing is done downhole.
Mounted on the strips 402, 408 are steering diodes 452,
25 454, respectively. These are of types as known to the art
for use with the X-drive and Y-drive transistors, of types
known to the art, which, along with X-sink and Y-sink tran-
-S2-
sistors, of types known to the art~ define in the preferred
embodiment location selection elements operated in predeter-
mined sets to access each bit or storage location within the
memory array The conductors 456 shown in FIGS. 21-22 are
5 representative of conductors extending from the core mat to
connections with the aforementioned drivers and sinks.
Although these sinks and drivers are actuated in the pre-
ferred embodiment to address the 256K bits as a linear array
of 256K x 1, they are grouped as a 256 x 512 x 2 matrix
~ defined by sixteen X-drive transistors and sixteen X-sink
transistors (256), by sixteen Y-drive -transistors and
thirty-two Y-sink transistors (5123 and by the direction of
current flow (2).
Also mounted on the strips 402, ~0~ are logic circuits
~5 and sense amps 458~ 460 ~orming part o~ the element 396
shown in FIG. 20.
Although a folded configuration wherein each segment
overlies each other i5 shown in the illustrated embodiment,
it is contempla-ted that other folded configurations, such as
20 in a triangular shape, can be used and are within the scope
of the present invention.
To use the compact memory shown in FIG. 22, bit
addressing is used so that the bits of any one word of
information are individually stored in the core matrix. In
25 the preferred embodiment this addressing is done over a 256K
x 1 memory array. For example~ with reference to FIG. 23,
each bit of an 8-bit word of informatlon i5 stored by
L7~
-53-
suitably controlling a respective set of drive and sink ele-
ments associated with the rows Rl-R8 and the columns Cl-C8
where the storage is to occur. If the 8 bits are stored in
rows Rl-R8 of column Cl, for example, each set includes a
5 column driver ~26 and one o~ the row drivers associated with
Rl-R8 and their corresponding sink elements (not shown). By
appropriately controlling the elements of each of these
exemplary sets in a known manner, the 8 bits are indivi-
dually stored in the 8 memory locations designated in FIG.
o 23 by the re~erence numerals 428, 430, 432, 434, 436, 438,
~40, 442.
The gauge 2 is constructed in the preferred embodiment
to ~unction over several days. In the specific embodiment
it is contemplated that the operation life will be 720 hours
~5 or 30 days. These limitations are imposed by the life of
the battery in the battery section 16 and the capacity of
the memory in the memory portion of the section 14. During
the operating time when the gauge 2 i9 downhole, operation
is controlled by the programs contained in the program
20 storage read only memory 152. Flow charts of these programs
are shown in FIGS. 25-32. These programs, described more
particularly hereinbelow, operate automatically or in
response to the various control signals found throughout the
circuits in the previously described drawings. Two of these
25 signals include the TIME signal generated by the real time
clock circuit shown in FIG. llB and the ~P signal generated
by the ~P hardware circuit shown in FIG. 5, whlch signals
are the primary control signals for causing the gauge 2 to
take a new sample or reading of the monitored environmental
condition.
The ~1~ signal of FIG. lls is generated when the count
5 of the counter 216, which has been preset by the micropro-
cessor 148, is extinguished, thereby signaling that a sleep
period has ended. This signal is provided to the primary
power switch circuit comprising the latch 246, the tran-
sistors 254, 256 and the related circuitry shown in FIG.
~ 12B. This signal is inverted and provided to an input of
the OR gate 248. The other input of the OR gate 248 is con-
nected to the inverted logically OR'd ~P and ~ PEN signals.
The output of the gate 248 is fed through the OR gate 250 to
reset the latch 246. The inverted output of the latch 246
~5 controls transistors 254, 256 to provide the +VCPU power
signal. In response to tha GO TO SLEEP signal, the non-
inverted output of the latch 246 causes the SLEEPEN and WAIT
signals to be generated to commence a sleep period; at this
time, the +VCPU signal is deactivated. The output of the OR
20 gate 248 also connects to the transistor 260 to provide the
interrupt signal, INT, also shown in FIG. 12s. The
interrupt signal is provided to the microprocessor 148 to
initiate a wake-up procedure and the taking of another
sample in accordance with the means of the gauge 2 including
25 the programs depicted in FIGS. 25-32.
The ~P interrupt signal (~PINT) is generated in response
to the ~P signal from the ~ P circuit 22 in the transducer
-55-
section 12. It is provided to the central processing unit
as shown in FIG. 10A for use within the means thereof
including the programs depicted in FIGS. 25-32 for
controlling the sampling of the monitored environmental con-
S dition. This interrupt signal i5 specifically generatedfrom the output of the inverter gate connecting the logi-
cally OR'd ~P and ~PEN signals to the gate 248, which output
clocks the latch 258 shown in FIG. 12B.
The specific software controlled times at which samples
are to be taken~ as indicated by the TIME signal, are deter-
mined by in which of two principal modes the preferred embo-
diment of the present invention is operated. One mode is
the fixed interval mode wherein samples are taken at a fixed
interval, such as every one second or one minute, regardless
5 of which parameter is being monitored or the change between
consecutive samples of a parameter. The other mode is the
variable interval mode wherein samples are taken at a sample
rate dependent upon the rate of change of the sampled para-
meter and also dependent upon whether the P circuit 22
20 detects a fast change in the pressure. The various stages
of operation within this variable sample rate mode will be
described with reference to EIG. 24.
FIG. ~4 illustrates a pressure curve plotted over time.
During time period q'l-2l the software controlling the
25 microprocessor 148 determines that the pressure is changing
sufficiently between consecutive samples whereby a relati-
vely fast sample rate is to be used to insure that suf-
-56
ficient samples are taken during this period of significant
change. During the time period T2_3, the software deter-
mines that the change in the pressure is sufficiently linear
so that a longer sample rate can be used without losing
important information. Therefore, to conserve energy and
memory, the software switches to a slower sample rate.
Because an important event (i.e., a rapidly changing
pressure) can occur between the longer sample times during
time period T2_3 (or even between the samples taken at the
faster rate during T1_2), the P hardware circuit 22 is uti-
lized. The circuit 22 detects the rapidly changing pressure
which occurs during time period T3_4 shown in FIG. 24,
which change would otherwise be missed if the gauge 2 were
operating only under software monitoring. The event shown
in FIG. 24 within time period T3_4 illustrates what could
happen when the well is shut in during a drill stem test,
~or example~ This would occur subsequent to the valve open
and flow periods exempli~ied by the graph during time
periods T1_2 and T2-3.
In addition to the foregoing two modes, it is con-
templated that the gauge 2 could operate in any other
suitable mode. For example, the mode could be one wherein a
fixed time interval in effect slides in correspondence with
any rapid pressure changes detected by the P hardware cir-
cuit 22. Or, it could operate in a variable mode dependent
upon various thresholds set for the detected parameters~
Whichever mode or modes are implemented, they are imple-
-57-
mented by preset-ting the gauge 2 at the surface since no
downhole communication is utilized in the preferred embodi-
ment. However, it is contemplated that such surface to well
bore communication can be implemented, such as by acoustic,
5 wire line, pressure pulse or other suitable signals.
The flow chart of the so~tware used to implement the
variable rate sampling mode is shown in FIGS. 25A-25~. As
previously mentioned, this operation is responsive to
changes in the pressure (or other monitored parameter~
~ observed while the gauge 2 is sampling as described hereina-
bove with reference to FIG. 24. The sample rate change is
also dependent upon the P hardware cixcuit 22 as previously
described. When a faster rate (shorter sample interval) is
selected, a lower resolution is also selected because at the
15 faster rate there is not enough time to achieve a higher
count in the counters 292, 294 shown in FIG. 13C. The lower
resolution is selected through the multiplexer 280 under
control of the microprocessor 148 and the variable rate
sampling program shown in FIGS. 25A-25B. In the preferred
20 embodiment each sample rate or interval is stored during
initialization with corresponding resolution control infor-
mation so that when the program of FIGS. 25A-25B causes a
new sample rate or interval to be selected, the
corresponding resolution information is also selected for
25 controlling the microprocessor 148 to properly operate the
multiplexer 280. When a slower sample rate (longer sample
interval) is selected, a higher resolution is used because
L7~
-58-
the counters 292, 294 then have sufEicient time to achieve a
higher count, thereby providing a higher resolution. In the
preferred embodiment, a resolution of 0.01 psi is used when
a sample rate of greater than or equal to four seconds is
5 selected, and a resolution of 0.1 psi is used when a sample
rate of less than four seconds is selected. In the pre-
ferred embodiment, the decision to select a slower sample
rate is based upon whether the pressure ~or other detected
condition) is greater than or less than, by a predetermined
o variance, a predicted pressure (or other monitored
condition). Whenever a rapid pressure change is detected,
the tool returns to full operation regardless oE the present
sample rate or the programmed off time duration when the
tool is operating in the variable rate sampling mode. When
5 such an event occurs, the shortest or fastest sample rate i5
entered by the software.
With reference to FIGS. 25A-25B, the program depicted by
the flow chart shown therein will be more specifically
described. The first operation shown in FIG. 25A includes
20 the initiali~ation of a software maintained sample counter
by setting it to zero and the initialization of the sample
counter limit (i.e., the maximum number of samples to be
read before the interval is lengthened) and the setting-up
of the sample rate table wherein a plurality oE different
25 sample rates, or intervals, and the corresponding resolution
control information are entered in a table maintained in the
random access memory 154, for example. These are steps
7~
_59
which one skilled in the pertinent arts would be able to
readily implement.
After ini~ialization, the program sets the sample rate
to the shortest interval, thereby selecting the fastest
5 sample rate. A first reading, or sample, of the monitored
condition is then taken and recorded. A next reading is
taken and recorded, and a third reading is taken. These
first three samples are taken at the sample rate then being
used, which for the initial three samples is the shortest
o sample interval.
Using the three samples~ prediction values are deter-
mined by first computing a difference, d, as follows:
d = [(S3-Sl)/2 + (S2-Sl)]/2, where Sl equals th~ first
sample, S2 equals the second sample and S3 equals the third
5 sample. To predict the n-th point, the equation Sn = Sl +
(n-l)(d), where n = 2,3,4, etc. is used.
Having initialized the prediction values by the
foregoing equation, the next sample is read. After this
reading, the software determines if the current sample has
20 been taken in response to a rapid pressure change detected
by the ~P circuit 22 as indicated to the microprocessor 148
by the INT and ~PINT signals. If this has occurred, the
sample rate is reset to the shortest interval and a new pre-
diction step is commenced.
25 If the current sample is not triggered by the rapid
pressure change, the previously determined prediction valuefor the current sample is compared with the actual current
17~
-60-
sample. If the absolute value of the difference between
this, the n-th reading, and the predicted n-th reading is
greater than a programmed difference threshold, then the
previous, or tn-l)-th, reading is recorded as having been
S the last point in a linear region of data, the sample
counter is reset to zero, and a new prediction is made (as
indicated by the balloon C). If the difference is less than
the programmed difference threshold, the sample counter i5
incremented and checked against the programmed sample count
~o limit. If the count limit has been reached, the next longer
programmed sample rate is selected and the process returns
to begin a new prediction step as indicated by the balloon C
shown in FIG. 25B. New prediction values are based upon
data commencing with the tn-l)-th point.
~ ny time the sample rate is changed, such as due to a
rapid pressure change or to no readings being recorded for
the programmed number of time intervals, the process causes
a software-controlled status flag to be set to indicate the
change and reinitialization is performedO
20 It is respectfully submitted that the steps shown in
FIGS. 25A-25B are otherwise self-explanatory and can be
implemented readily by those skilled in the pertinent arts.
In addition to being responsive to the software moni-
tored changes in the sampled parameter and to the ~P hard-
25 ware circuit 22, the variable rate sampling program is also
responsive to the remaining battery life and the remaining
memory capacity as shown in the flow chart depicted in FIG.
7~
-61-
26. When the program detects that the remaining battery
life is diminishing (as can be determined by counting the
number, or monitoring the widths, of the pulses output by
the pulse width modulator 330, for example) the software
5 adjusts the sampling rate. One specific technique for
obtaining a signal indicating the state of the battery is to
connect the +BAT signal to the input of a voltage controlled
oscillator, in a manner analogous to the temperature trans-
ducer shown in FIG. 3. The output of the voltage controlled
oscillator would then be connected to a presently unused
input of the multip~exer 278 shown in FIG. 13B so that it
~ould be read by the central processing unit. The central
processing unit would compare the reading with a table of
predetermined entries correlating the voltage controlled
~5 oscillator output with remaining battery life. Once the
reading and comparison showed a sufficient decline in the
battery (such as the detected parameter being below a prede-
termined threshold), a bit designating that the battery is
getting weak would be set in a battery status register to be
20 read by the program as indicated in FIG. 26. This program
also keeps track oE how much memory remains, and it adjusts
the sample rate to prolong the length of time that samples
are taken. Theoretically, the program is to monitor battery
life and rernaining memory and do whatever is necessary so
25 that the last bit of energy or the last memory location is
never used during the programmed test time.
Referring to FIG. 26, once the battery is determined to
- -62-
be weak, such as described hereinabove, the program checks
another software register to determine if a fixed rate bit
has been set. If not, the program sets the bit to enter a
fixed rate sampling mode rather than a variable rate
sampling mode. After this is done, the next longer sample
interval is sel~cted or four times the maximum interval is
selected if the maximum value has been previously used.
Similar adjustments are made in the portion of the program
shown in FIG. 26 performing the full memory check. It is
believed that these steps are self-explanatory; however, in
general, the program detects when the memory has reached
either of two predetermined thresholds t87% and 97% in the
depicted pre~erred embodiment~ and lengthens the sampling
interval when this occurs. All of the steps shown in FIG.
26 could be readily implemented by one skilled in the per-
tinent arts.
The storing function for storing information derived
from the samples is controlled by the data recording
programs shown in FIGS. 27-28. The raw data used by the
microprocessor 148 for storing the information are contained
in the binary bits at the outputs of the counters 292, 294
shown in FIG. 13C. When this information is received by the
microprocessor 148, the microprocessor 148 determines
periods oE linear data in accordance with the steps shown in
FIGS. 25A-25B. When such a period is detected, only the end
points of the linear data period are recorded to minimize
the number oE data bits stored in the memory portion of the
7~
-63-
section 14, thereby conserving memory space. When linear
data periods are not detected, the changes in the infor-
mation from the preceding sample, rather than the raw data,
are stored to again conserve the amount of memory used per
S sample. The particular recording technique implemented uses
variable length records with Huffman encoded identification
fields and an adaptation of the advanced data communication
control procedure (ADCCP) plus a parity bit for data
integrity indication.
~ FIG. 27 discloses a flow chart of a program for
controlling the microprocessor in obtaining information as
well as in conserving energy during the process. The
program commences by first determining whether the pre-
viously selected sample rate interval is less than 1~
~5 seconds. If it is, the transducer power is turned on by
appropriately actuating the XDRSW signal shown in FIGo lOC.
If the sample rate interval is greater than 16 seconds r the
transducer is turned on five seconds (or other suitable
transducer stabilization time) before the sample is needed.
20 Next, it is determined, by monitoring the INT signal,
whether a reading needs to be taken. When a reading is to
be taken, the time is read from the timer chip 198 shown in
FIG. llB. Then the frequency-to-binary conversion means is
energized by turning on the ~VFBC power signal shown in FIG.
25 lOC. This enables the frequency-to-binary conversion cir-
cuits to process the signals from the transducer section 12
and provide the count at the outputs of the counters 292,~
29~ shown in FIG. 13C.
-
-64-
After the pressure and temperature are read from these
conters by the central processing unit, the central pro-
cessing unit turns off ~VFBC to deenergize the frequency-to-
binary conversion means. Vnder control of the program shown
5 in FIG. 27, the central processing means then determines if
the sample rate interval is less than 1~ seconds. If it is
not, the XDRSW signal is deactivated to turn off the trans-
ducer power provided to the circuit shown in FIG. 16.
If a sample needs to be recorded, as determined by the
I D sample rate program shown in FIG. 25, the central processing
unit activates +VDRM and appropriately controls the power
switch chip 234 so that logic circuit power signals VLOGIC
are provided to the da~a recording module. The central pro-
cessing unit then ~ormats the data to be recorded in accor-
~5 dance with any acceptable formatting scheme as would beknown to the art, and then the data recording module
programming power is turned on. For storing data in the
semiconductor memory of the portion 14b, for example, the
data recording module programming power is turned on by
20 appropriately controlling the transistors 190, 192 shown in
FIG. 10C to provide the +15V power signals to the VPP
generating circuit shown in FIG. l9C. With this power, the
digital information is recorded in the semiconductor memory.
The actual writing to the magnetic core memory is
25 accomplished in a suitable manner as known to the art.
Once the data are recorded, the data recording module
programming power is turned off by deactivating the tran-
-65-
sistors 190, 192 shown in FIG. 10C (for the semiconductor
memory), and then the data recording module logic power is
turned off by appropriately controlling the power switch
chip 234 shown in FIG. 12A and the transistor 194 shown in
5 FIG. l~C.
Other power conserving or managing programs of the pre-
ferred embodiment of the present invention are the sleep
mode power control programs having ~low charts shown in
FIGS. 29A-29B. The scheduled sleep time program of FIG. 29A
~ provides selectable initial turn-on delay to conserve the
battery power while the tool is being run into the well bore
4. This program also permits a selectable number of cycles
of selectable tool power on/power off after the gauge is
downhole. This conserves battery power while scheduled
15 changes in surface equipment and configuration are taking
place during long tests, for example. The unscheduled sleep
time program of FIG. 29B provides variable power-down depen-
dent upon the sample interval. This also conserves battery
power by not continually energizing portions of the tool
20 which might not be continually needed. These features are
implemented by controlling the various power sources acti-
vated through the transistors 180-188 shown in FIG. 10C and
the transistor 256 shown in FIG. 12B. One specific time
during which the power-down of selected portions occurs is
25 during the intervals between samples (when the interval is
greater than a predetermined tlme in the preferred
embodiment).
-66-
The scheduled sleep time program shown in FIG. 29A first
compares a preset wake-up time, entered during the ini-tiali-
zation of the gauge 2 with the interface 8 and the computer
system 10, to the current time maintained in the timer chip
5 198 shown in FIG. llB. If the difference is greater than
four hours, then four hours is programmed into the counter
216 and the multiplexer 220 is controlled so that the
counter 216 is clocked by the one-minute timing pulses taken
Erom the timer 198 through the multiplexer 220. IE the dif-
o ference is not greater than four hours, the preset wake-up
time minus the current time minus one minute is entered into
the counter 216, which counter is thereafter pulsed by the
one-minute timing pulses. The program shown in FIG. 29A
then determines whether this scheduled sleep period is the
5 initial turn-on delay (e.g., when the gauge is run in the
hole). If it is the initial delay, then the program
disables the ~PEN signal so that an~ rapid pressure changes
occurring during running in the hole, for example, will not
energize the gauge. If it is not the initial delay, then
20 the program insures that the ~PEN signal shown in FIG. llB
is enabled so that the ~P signal will be detected in the
circuitry shown in FIG. 12B to awaken the gauge 2 should a
sufficiently large change in pressure be detected. After
whichever one of these two decisions is made and the ~PEN
25 signal is either disabled or enabled, the soEtware causes
th~ microprocessor 148 to turn off all the programmable
power signals shown in FIG. lOC and to generate the GO TO
SLEEP signal which clocks the latch 246 shown in FIG. 12B to
turn off the +VCPU power signal. The foregoing routine for
scheduled sleep time is performed at each sample time.
Also occurring at each s~mple time is the process shown
in the unscheduled sleep time program disclosed in FIG. 29B.
This program compares the next sample time to the current
time and if the dlfference is less than 16 seconds, it
returns to the system control program shown in FIGS.
32A-32C. If the difference is not less than 16 seconds, the
program then determines whether the difference is greater
than four minutes. If it is, the program sets the next
sample time minus the current time minus one minute in the
counter 216, sets a snooze mode bit in a software monitored
register and goes to point C in the program shown in FIG.
29A. If the difference is not greater than four minutes,
the next sample time minus the current time minus seven
seconds (or other suitable warm-up period) is entered in the
counter 216, the multiplexer 220 is controlled to clock the
counter 216 with the one-second timing pulses, and then the
snooze mode bit is set. Thereafter, the program goes to
point B in the flow chart shown in FIG. 29A to perform the
subsequent steps shown therein and described hereinabove.
The snooze bit informs the gauge that no reinitialization of
the sample rate program (FIGS. 25A-25s) needs to be per-
formed upon wake-up from an unscheduled sleep period.
The foregoing steps shown in FIGS. 29A-29B can be
readily implemented by those skilled in the pertinent arts.
-68-
When the bits of information are to be stored in the
semiconductor memory shown n FIGS. l9A-19C, each bit is
written to the memory for less than the manufacturer's spe-
cified write time; however, this is repeated several times,
5 then a read is performed to verify that storage has
occurred. This is also done with different voltages than
are specified. This semiconductor programming routine is
shown in the flow chart of FIG. 28, which flow chart is
self-explanatory and which could be readily implemented by
~ those skilled in the pertinent arts.
When the bits are to be stored in the storage locations
of the magnetic core memory shown in FIG. ~0, the storage
program of the preferred embodiment is aware of inoperable
location selection elements, such as bad drive and sink
~5 transistors, so that storage is not attempted in inoperable
locations. Furthermore, when the magnetic core memory is
used, the words of information are stored bit-by-bit.
To determine what memory locations in the magnetic core
are not properly accessible due to bad drive and sink ele-
20 ments prior to the time the gauge 2 is lowered into the wellbore 4, a surface test is performed under control through
the interface 8 but with a program stored in the memory 152.
When the bad locations (more specifically, the inoperable
drive and sink transistors) are determined, a record of that
25 information is stored in an operable portion within the core
memory contained in the gauge ~. During the question and
answer session which is conducted with the interconnected
-69-
gauge 2, inter~ace 8 and computer system 10, these bad
memory locations are read from the core memory and trans-
ferred to the random access memory 154 shown in FIG. lOB.
Inside the random access memory 15~, the information can be
5 accessed by the microprocessor 148 when it is conducting
sample reading and storing operations. This feature of the
present invention permits partially defective memories to be
used. A flow chart of this memory test program is shown in
FIGS. 30-31.
o More particularly, in the preferred embodiment, the
memory test program writes and reads through pairs of drive
and sink transistors to determine whether the transistors in
the pairs are functional. From this information, an address
map locating the non functional me~.ory drive and sink tran-
5 sistors is created.
Referring to FIGS. 30-31, the specific programs
disclosed therein will be described. FIG. 30 shows the
overall memory test procedure~ Generally~ the test address,
defined by a software-maintained count, for the core memory
20 iS initialized to zero and a bit is written to the storage
location accessed by the initially addressed set of location
selection elements. The program senses the addressed cell
to verify if the write was successful. If it was success-
ful, the program determines whether all of the pairs of X-
25 drivers and X-sinks of the preferred embodiment location
selection ele~ents have been checked. If not all have been
checked, the address counter is incremented to the next X-
-70-
sink/ drive pair. To test -the X-sink and X-drive tran-
sistors in the preferred embodiment, the addresses for these
sinks and drives are started from zero and incremented by
one to fifteen since there are sixteen of each in the pre-
S ferred embodiment.
When the pairs of the X-sinks and X-drives have been
tested, the test address is reset to 2ero and a similar test
is performed on the ~-sinks and Y-drives. Because there are
thirty-two Y-sinks, but only sixteen Y-drives, the address
for the drives is set e~ual to the sink value divided by
two.
If in testing either the pairs of X-sinks and X-drives
or the pairs o~ Y-sinks and Y-drives the write step is not
successful, a failure isolation program is run. The failure
isolation program is shown in FIG. 31. Throu~h the opera-
tion of this program shown in ~IG. 31, the inoperable one or
ones of the sink and/or drive transistors being tested are
determined. First, the sink address is decremented to
address the next lower numbered sink that has already passed
20 the test. Another write is attempted whereupon the address
of the sink is restored by being incremented to its previous
value. If this second write fails, this indicates that the
particular driver involved is not functional. This is noted
by the software setting the appropriate drive failure bit in
25 a memory status register. One register is kept for X-drives
and one is kept for Y-drives. If this second write is
accomplished, then the address of the X~drive is decremented
-71-
to a previous valid address. A third write is attempted
whereupon the address of the X-drive is restored by being
incremented to its previous value and the effectiveness of
the write is checked. If this write is not successful, this
5 indicates that the p~ired sink is inoperable and so the
appropriate sink failure bit is set in the respective sink
memory status register. As with the drives, there is one
register dedicated to the X-sinks and one dedicated to the
Y-sinks. If a valid write occurs, a fourth write step is
performed. If this fourth write fails, both the sink and
drive failure bits are set. If this fourth write step
achieves a valid write, the program returns to check the
next pair. The physical writing and sensing are done in
manners known to the art for writing to and sensing magnetic
5 core memories.
In the preferred embodiment, the memory status registers
include two bytes (sixteen bits) each fox the six~een X-
drivers, the sixteen X-sinks and the sixteen Y-drivers, but
four bytes (thirty-two bits) for the 32 Y-sinks. Each bit
20 in these bytes is associated with a respective one of the
associated sinks or drivers. For example, if the fourth X-
drive transistor were inoperable, the fourth least signifi-
cant bit (bit 3, with the first bit being bit 0) within the
two-byte X-driver memory status register would be set.
25 Once the inoperable core memory locations have been
determined and the memory status maps constructed in the
respective registers, this information can be used by the
~ r~ L7i~L
-72
gauge 2 to avoid inoperable core memory locations. For pur-
poses of address incrementing in the preferred embodiment,
the core memory address retained in a suitable memory
address register is treated as an eighteen-bit linear
5 address space for use in bit-addressing the 256K x 1 bits of
memory. However, for purposes of address checking, the
address word is segmented into two sets of four segments.
The two sets are defined as being the two phases or current
flow directions of the Y-select lines as defined by the most
~ significant address bit, bit 17. Each of the four segments
provides the address for a respective one of the X-drive, X-
sink, Y-drive and Y-sink matrices of transistors. In the
preferred embodiment, the segments include the following
address bits:
X-drive A13-A16
X-sink A9-A12
Y-drive A5-A8
Y-sink AO-A4
That is, the four bits needed to address one of the
20 sixteen X-drive transistors is located in bits 13-16 of the
address word. Similarly, the four bits needed to address
one of the sixteen X-sink transistors are found in bits 9-12
of the address word, and the address of one of the sixteen
Y-drive transistors is found in bits 5-8. The five bits
25 needed to address one of the 32 Y-sink transistors are
located in bits 0-4 of the address word.
With the foregoing allocation, the program can look at
each segment to determine if the four or five-bit address
-73-
contained within the segment matches an address Eield pat-
tern derived from the set bit locations of the driver and
sink memory status maps created in accordance with the
program shown in FIG. 31. For example, the X-drive memory
5 status map is checked to see if any of the sixteen bits in
those bytes have been set to a logical 1. If no set bits
are found, there are no bad X-drivers. If there are set
bits found, then the bits are converted into corresponding
address field patterns. In the preferred embodiment~ the
o address field patterns are the binary e~uivalent of the bit
location within the memory status registers. For example,
if the least significant bit of the Y-sink memory status
word has a set bit, thereby indicating that the first Y-sink
transistor is inoperable, the address field pattern is
5 00000. If the fourth least significant bit were set, this
would correspond to an address field pattern of 0011. Each
such field pattern is compared against the address within
the co~responding segment of the address word. Whenever A
match is found between the address in the address word and
20 the address field pattern, the address in the memory address
register is changed until a match no longer occurs. Thus,
for the example of the first Y-sink transistor being ino-
perable, the AO-A4 bits of the memory address word are com-
pared to the field pattern 00000. If bits AO-A4 are 00000,
25 then this address will be changed, such as by being incre-
mented to 00001. This new address is then checked.
The Elow chart for the overall system control program is
shown in FIGS. 32A-32C. When the power is applied to the
~ ,f~,~f.L~'7~
-7~-
gauge 2, all of the registers are initialized in a manner as
known to the art. The program then checks to determine if
the surface readout unit is connected. This is done by
monitoring the SPAC signal. If the surface readout unit is
5 connected, the system control program reads input messages
provided over the DO-D7 lines interconnecting the gauge 2
and the interface 8. The program determines the message
type and executes the command or stoxes the set of values
prior to determining the next message time as shown in FIG.
o 32A. For example, during these steps, any inoperable memory
locations c~n be transferred to the random access memory 154
shown in FIG. lOB, predetermined sleep periods can be
entered, and the various parameters for the sample rate
control program entered. If the message type is a discon-
15 nect message, the program puts the tool to sleep b~generating the GO TO SLEEP signal in the manner as pre-
viously described.
If the surface readout unit is not connected, the system
control program branches to the downhole control portions
shown in FIGS. 32B-32C. FIG. 32B shows that the interrupts
are enabled and the ~P interrupt is checked to see if it has
occurred. If it has, the program checks to see iE the
constant sample rate, or fixed sample rate, bit has been
set. If it has, it clears the interrupt flag and ignores
2 5 the interrupt because the tool is to operate with a fixed
sample rate regardless of any hardware detected rapid
pressure changes. If the constant sample rate has not been
7~
-75-
selected, the sample rate is set to its shortest interval
and the sample rate change program is performed.
If the ~P interrupt has not occurred, the s~stem control
determines if more sleep time is remaining. If there is,
S the circuit goes back to sleep and returns to point A in the
flow chart shown in FIG. 32A. If there is no more sleep
time remaining, the program loads the sample interval in the
counter 216 so that the INT signal will be generated when
the sample interval lS counted and the TIME signal is pro-
~ duced. The system control program then determines whether ascheduled sleep time has ended. If it has, the sample rate
program is implemented. If not, the program checks whether
the INT signal shown in FIG. 12B has been generated. Once
the INT signal is generated, the system control program per-
forms the sample rate control routine if the sample rate
changed. If the sample rate did not change, the system con-
trol program takes time, pressure and temperature readings,
determines whether any data needs storing and stores the
data if storage is to occur. These are performed in accor-
20 dance with the programs depicted by the flow charts shown inFIGS. 27-28. If data are not to be stored, the system
control program checks to see if it is time to run
diagnostic programs and does so if it is time. If not, the
program returns to point C shown at the top of FIG. 32C.
25 It is respectfully submitted that the foregoing programs
can be readily implemented by those having skill in the per-
tinent arts.
~7'~
-76-
The foregoing description shows that the gauge 2 provides
an improved means for detecting physical conditions or para-
meters in a well bore. The tool monitors and detects,
through a selected one of a plurality of transducer sections
S which provide interfacing with diffsrent types of trans-
ducers, all important changes in one or more monitored con-
ditions so that none are missed. This is done through the
combined use of software and hardware monitoring of at least
one selected parameter, such as pressure. The software
13 monitoring occurs at sample intervals and at resolutions
which are selected by the gauge itself from initialized
tables and in response to suitable changes in the monitored
condition. The hardware monitoring detects rapid changes in
a monitored condition and forces the gauge to energize
itself if it is deenergized and to select the shortest
sample interval. It also monitors itself to insure that the
microprocessor is operating within proper limits and that
meaningful da-ta are collected throughout the entire test
period even as the battery life and storage capacity are
20 depleted. The battery life is conserved through selective
power control o~ a variably selectable plurality of portions
of the tool and through scheduled and unscheduled sleep
periods during which the tool is powered downO The storage
capacity is conserved by controlling the sampling so that
25 data during linear regions are generally not stored and by
generally storing the changes in the data and not the raw
data themselves. Furthermore, it provides increased storage
~6~
-77-
in nonvolatile magnetic core memory configured in a folded,
bit-addressing configuration which i5 capable of opexation
in the extreme temperature environments found downhole.
This memory is also utilized even if it is partially defec
S tive through the memory testing and non-functional location
mapping and addressing procedures described hereinabove.
The resistor values shown in the drawings are in ohms
and those for the capacitors are in microfarads unless
otherwise specified; however, it is to be noted that the
:_ 10 specified component values are not to be taken as limiting
the present invention. Additionally, use of the word
"connected" and the like in describing electrical components
throughout the specification and claims primarily connotes
electrical relationships unless the context dictates other-
~5 wise. Furthermore, although the preferred embodiment has
been described with specific reference to sampling pressure
and temperature and to controlling functions in response to
changes in pressure, for example, the present invention is
not limited to sampling and responding to just these parame-
2 o ters. Rather, the present invention broadly contemplatesuse with any environmental condition which can be sensed and
converted into an electrical signal. Other examples of such
conditions besides pressure and temperature within the oil
and gas industry include, but are not limited to, sensing
25 flow, force, vibration, shear, viscosity, density, salinity,
pH, porosity, and resistivity and other logging measure-
ments. Still other examples of uses of the present inven-
-78-
tion include conducting bubble point tests and sampling
fluids.
Thus, the present invention is well adapted to carry out
the objects and attain the ends and advantages mentioned
S above as well as those inherent therein. While preferred
embodiments of the lnvention have been described for the
purpose of this disclosure, numerous changes in the
construction and arrangement of parts can be made by those
skilled in the art, which changes are encompassed within the
o spirit of this invention as defined by the appended claims.
This application is a division of Canadian Application
No. 508,446 filed May 6, 1986.
