Note : Les descriptions sont présentées dans la langue officielle dans laquelle elles ont été soumises.
130~24~
INTEGRATED POLY-PHASE POWER METER
BACKGROUND OF THE INVENTION
Field of the Invention
This invention relates to apparatus for mea-
surinq electrical power consumed by an application or
qupplied by a source. More particularly, the invention
relates to an integrated circuit which provide~ informa-
tion about electric power in a distribution system when
coupled to voltage and current transducers in that dis-
tribution system.
Descri~ion of the Prior Art
Electricity meters are ~Ised for measuring thequantity of electric energy consumed or supplied by a
particular appl:Lcation. In alternating current supply
or distribution systems, electromecl-anical watt-hour
meters typically have been used. Suc}l we].l krlow watt-
hour meters are used throughout the world to measure
,' the consumption and supply of electricity, and are a
common fixture on almost any residential or industrial
structure to which power is supplied. While such meters
are highly reliable, their mechallical construction sharply
limits the range of additional functions they may perform.
For example, charging different rates at different time~
of the day or ~snder different utility load conditions
is difficult, as is using the meter it-self ~o control a
130~2~9
load or a generator. Additionally, such mechanical
meters would be quite expensive to fabricate were th0y
to perform many of these functions.
Completely electronic meters, but not inte-
grated circuits, for the measurement of power are de-
scribed in U.S. Patent Nos. 4,015,140, 4,066,960, and
4,217,546. The techniques therein employ wall-known
"mark-space amplitude" multiplication or "pulse width-
pulse height" multiplication in which the amplitude of
a pulse waveform is proportional to one variable and
the pulse width is proportional to a second variable.
In the case of power metering, if one variable is the
potential supplied to or from a load and the other var-
iable is the current flowing to or from a load, then
the average value of the waveform is proportional to
the power. Generally, the pulse width is determined by
a comparator which receives both a triangle waveform
and the potential supplied to or from the load.
Unfortunately, these techniques suffer from a
number of disadvantages which reduce the precision of
the meter for low measurement. The multiplier described
in these patents injects charge into downstream circuitry
which that circuitry incorrectly interprets as a valid
signal thereby causing significant errors in the power
measurement. The approach shown in the 960 patent
relies upon a resistor-capacitor network to provide a
frequency source. This is disadvantageolts in view of
the cost of a sufficiently hi~h quality capacitor.
Additionally, at low load conditions, the offset voltage
3~ influence of the operational amplifier is not cancelled.
Because of the low cost of manufacture, minimal
size, and high reliability of solid-state circuits,
there have been many attempts to design power meters
using integrated circuits. Integrating all of the func-
tions of a power meter onto one or more integrated cir-
cuit chips lowers manufacturing cost, and enables the
information about power consumption or supply to be
~01249
used in ways not previously possible. For example,
time of day metering wherein a different fee is charged
for electricity consumed during peak hours becomes read-
ily fea ible if the information from the power meter is
used to increment various registers, the particular
register depending upon the time of day. ~urthermore,
the electrical signals from such a meter may be readily
transmitted to remote locations for billing or other
purposes.
One approach to fabricating a power meter
using solid state components is described in PCT Inter-
national Publication Nos. W085/00893 and W085/00894.
The system described thereln also relies on pulse width-
pulse height multiplication performed by a multiplier
circuit which produces a signal current proportional to
the product of the measured current and voltage. A
current-to-frequency converter receives that current
and provides an output signal for driving a display.
The multiplier shown in PCT 893 has two main
disadvantages. The MOSFET switch array associated with
the resistor in series with the current path injects a
parasitic current proportional to the frequency of a
triangular wave signal which has been added to the po-
tential supplied. To reduce this charge injection, the
frequency of the triangular wave signal is decreased,
unfort~nately thereby reducing the multlplier bandwidth.
Furthermore, even at such low frequencies an overall
charge injection minimization trim i3 required.
A~ shown in the 894 publicatioll, the offset
voltage of an operational amplifier in the current-to-
frequency converter is cancelled by opening and closing
switches which load the offset voltage onto a capacitor.
Unfortunately, during the time the switches are in this
configuration, the current-to-frequency converter is
disconnected from the circuit and no power is measured.
If a power spike should occur during thi6 time; it is
not measured. Furthermore, although thi 9 techni~ue
~30i2~9
cancels the offset voltage, it causes charge injection
into the measurement circuitry, thereby creating
measurement errors.
A more significant disadvantage of this
circuitry is that fre~uencies in the power distribution
system may be synchronous with the frequency with which
the offset voltage is cancelled. To minimize charge
injection into the measurement circuit, the lowest
frequency possible is desirable for cancelling the
offset. As the frequency of cancellation is reduced,
however, the frequency of cancellation becomes integrally
divisible into more frequencies appearing in the power
distribution system, resulting in errors of several
percent in measurement of the electric energy consumed or
supplied. Another disadvantage of the circuitry is the
requirement for external voltage reference source.
Other known pertinent art is described in an
accompanying disclosure statement.
SUMMARY OF THE INVENTION
One aspect of the invention includes a system
for measuring electrical energy in a circuit comprising:
apparatus for measuring electrical energy in a
conductor of alternating current comprising:
a) voltage sensing means coupled to a
circuit, said voltage sensing means a first signal
related to potential in the circuit;
b) current sensing means coupled to the
circuit, said current sensing means supplying a second
signal related to current in the circuit;
c) a multiplying means connected to receive
the first signal and the second signal and provide a
third signal having a current representative of the
product of the first and the second signals, said
multiplying means further comprising:
i) signal generator means for generating
a periodically varying signal;
ii) comparison means connected to receive
~30i;;~49
both the periodically varying signal and a selected one
of the first and the second signals, and in response
thereto provide a comparison output signal when the
periodically varying signal is in a predetermined
relationship to the selected one of the first and the
second signals, the comparison output signal determined
by the relative magnitudes of the periodically varying
signal compared to the first signal; and
iii) switchably controlled current source
means connected to operate under control of the
comparison means output signal and connected to receive
the other of the first and the second signals and supply
the third signal;
d) converter means connected to receive the
third signal and provide a fourth signal having a
frequency related to the product of the first and the
second signals; and wherein the converter means includes
sign bit means for supplying a sign bit digital signal to
the multiplier means which digital signal is of a first
state when power in the circuit is flowing in a first
direction and in a second state when the power in the
circuit is flowing in an opposite direction, said sign
bit causing said multiplier means to provide said third
signal with a polarity opposite that of the polarity of a
reference current.
BRIEF DESCRIPI'ION OF THE DRAWINGS
Figure 1 is a schematic of a preferred
embodiment o:E a poly-phase power meter illustrating its
interconnections with one phase of a power distribution
system;
Figure 2 is a block diagram illustrating the
overall pulse width amplitude multiplier circuit of the
power meter;
Figure 3 is a timing diagram illustrating the
operation of the circuitry shown in Figure 2;
Figure 4 is a circuit schematic of the triangle
wave signal generator 35 of Figure 2.
;~,;, ,~
~3~1249
Figure 5 is a timing diagram illustrating the
operation of the generator of Figure 4:
Figure 6 is a schematic of the voltage
comparator circuit 30 of Figure 2;
Figure 7 is a timing diagram illustrating the
operation of the circuit of Figure 6;
Figure 8 is a ~ircuit schematic of the switch
40 shown is Figure 2;
Figure 9 is a block diagram of three current-
voltage multipliers connected to a current-to-frequency
converter;
Figure 10 is a timing diagram illustrating the
operation of Figure 9;
Figure 11 is a blocX diagram of the auto-
zeroing loop employed in the operational amplifier 150 of
Figure 9;
Figure 12 is a block diagram illustrating the
automatic biasing technique employing in Figure 9;
Figure 13 is a timing diagram illustrating the
operation of Figure 12;
Figure 14 is a circuit schematic of the
operational amplifier 150 of Figure 9; and
13~3~L249
,
Figure 15 is a circuit schematic of the ref-
erence voltage source.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Theory of Op ratio
Figure 1 is a block diagram illustrating the
interconnection of a power meter 10 to an electrical
distribution system 5. Power meter 10 measure~ the
amount of electric energy consumed or supplied (or both
consumed and supplied) by a particular application 15.
Application 15 typically will be a customer of a utility
company such as a residence or business, or a supplier
of electrical energy to a utility company, such as an
electricity generating plant. Consumers or generators,
such a9 application 15, are connected to the electrical
distribution system 5 by one, two or three phases. In
Figure 1, only a single phase is shown, which consists
of a pair of conductors of alternating current having a
potential U(t) established between them. In embodiments
of the invention more than one phase, all phases are
connected similarly to meter lO. In other embodlments,
each phase is sampled individually and supplied to meter
10 through a multiplexer.
To determine the power consumed or generated
by the application 15, it is necessary to determine the
product of the current I(t) flowing induced by the volt-
age U(t). The power P(t) consumed or generated by n
phases i 8:
P(t) = ~Uitt) Il(t) (1)
n
Power meter 10 computes the power-related
information by measuring the current I(t) and potential
U(t). The potential of the distribution system at the
metered location is sensed by employing either a voltage
transformer 20, a voltage divider, or mutual transducer.
i24~
In a similar manner, the current flowing to or from the
application 15 i5 detected using a current transformer
24, m~ltual inductance transducer, or other well known
apparatus.
The voltage transformer or divider 20 delivers
a voltage Vv~t) to the power meter 10 which i9 charac-
terized by the voltage constant kv of the transducer
20. Similarly, the current transformer 24 delivers a
voltage proportional to the current in the phase sensed.
The transormer output is characterized by the trans-
former constant kc and shunt resistance RSh. The power
meter 10 is designed with the assumption that the cur-
rent transducer 24 provides current information having
a mean value of zero. (This is not a critical limita-
tion because almost all current transformers and mutualinductance tran~ducers behave in such a manner.) The
voltage transformer provides voltage information Vv(t)
proportional to the voltage difference between the phase
sensed and the neutral line or between the phase sensed
and another phase as given by Equation 2 below, while
the current transformer 24 provides voltage information
Vc~t) proportional to the current in the phase as given
by Equation 3 below.
Vv(~) = kv ' U(t) (~)
Vc(t) = kc Rsh I(t) (3)
Power meter 10 then effectively multiplies Vc(t) by
Vv(t) to obtain an electric signal Vp(t) which is pro-
portional to the power. This relationship is shown in
Equation 4 below.
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Vp(t) = kv ' kc ' Rsh U(t) I(~) (4)
The power information then may be converted to frequency
information Fp(t) by multiplying by a constant kp.
s
Fp(t) = k V (t) t5)
By integrating the frequency information over
time T, the mean value Fm then is:
0J (6)
while the nu~ber of puises N is:
N = F T (7)
Thus the number of pulses, counted over a period of
time T at the output of the power meter, is proportional
to the energy consumed or supplied.
Power Meter 10 Svstem Overview
Figure 2 is a block diagram of the power meter
10. As shown in Figure 2, the power meter receives
potential information Vv(t) on line 27 and current infor-
mation Vc(t) on line 29. The system includes a voltage
comparator 30 for comparing the potential information
on line 27 with a signal from a triangle wave signal
generator 35 on line 32. Although theoretically the
voltage transducers may be reversed with tlle current
transformer coupled to the voltage comparator, it is
preferred to drive line 27 with the voltage information
in view of its dynamic range and the character of the
triangular wave. Furthermore, driving line 29 with the
current transformer is advantageous because the resistor-
switch-resistor system (R2, 40, Rl) is highly linear
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over at least three decades of driving signal range.
This enables accurate measurement over the large dynamic
range ~f the current. Even for small currents the output
from the current transformer i5 sufficient to drive the
frequency converter 50. Additionally, the output signal
Vc(t) is single ended, in contrast with the double-ended
or bridged output of the current transformer of the
U.S. patents mentioned above.
The output signal from voltage comparator 30,
in conjunction with a sign bit signal NP, controls a
CMOS switch 40 via an exclusive OR gate 45. The ~ign
bit indicateR whether application 15 is consuming or
generating power. Switch 40 is connected between re-
sistors R2 and R1. When switch 40 is closed, a current
Ip(t) i~ caused to flow through the switch to a current-
to-frequency converter 50 which employs this signal to
supply power information. The current-to-frequency
converter 50 typically drives a counter or a display on
the exterior of meter 10; however, the information may
also be used for other purposes, such as control of the
power consumption or generation of the application 15,
for transmission to a remote site for calculating rate
information, etc.
The operation of the overall system shown in
Figure 2 may be more readily understood with reference
to the timing diagram of Figure 3. For explanation,
the signals Vv(t) and Vc(t) are assumed to be constant
over the time period depicted in Figure ~. (It should
be understood, however, that the alternating current in
the distribution system 5 means signals Vv(t) and Vc(t)
will be constallt only for very short time periods.)
The triangle wave signal generator 35 gener-
ates a triangular waveform having a rapidly varying
potential Vtw(t) which oscillates between -Vref and
Vref. The triangular wave signal has a frequency sub-
stantially greater than the frequency of the signal in
the distribution system 5. For example, typically the
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\(
triangular waveform will have a frequency about twenty
times higher than the highest expected frequency of the
distribution sy~tem. Furthermore, as mentioned above,
because of the spectral noise of the local oscillator,
S the triangular waveform frequency cannot be phase locked
with the frequency of the signal to be measured. Thus,
for a 60 Hz distribution system a triangle waveform
frequency of l000 Hz might be employed. Additionally,
the maximum potential Vref of the triangular waveform
is set to be higher than the largest potential Vv(t)
from the voltage transformer 20 expected to be measured.
Although only a triangular waveform is described herein,
other equivalent oscillating signal, for example, a
sawtooth waveform, may be employed.
As shown by Figure 2, the triangular waveform
is supplied on line 32 to comparator 30. Comparator 30
compares this potential with the signal Vv(t) from the
voltage transformer or voltage divider 20, and in re-
sponse provides an output signal indicative of the rel-
ative potentials. This output signal, on line 44, drives
one input terminal of an exclusive OR gate 45, while
sign bit NP, used to designate whether the application
is consuming or supplying energy, drives the other input
terminal. The sign bit originates from a circuit within
tlle current to frequency converter 50. If the sign bit
is 0, then when the input voltage Vv(t) is greater than
the triangle wave signal Vtw(t), switch 40 is closed
and voltage Vc(t) induces a current through the two
resistors R1 and R2. When potential Vv(t) is below the
triangle wave signal Vtw(t), then switch 40 is open and
no current Ip(t) flow~ to current-to-frequency converter
50. The interaction of the comparator 30 with switch
40 results in a series of pulses, shown in the lower
portion of Figure 3 as signal 47, having an amplitude
proportional to Vc(t) and a duration proportional to
Vv(t). The shaded area of Figure 3 corresponds to the
mean value Ip of the current Ip(t).
130~249
l~
1~
In Figure 3, time tl corresponds to the time
that Vtw(t) exceeds Vv(t). Time t2 corresponds to the
remaining time during which the triangular waveform is
beneath the lev~l of Vv( t), while time tx corre~ponds
to the time following tl until the triangular waveform
becomes negative. Therefore, the basic relationship of
the cur~rent-voltage multiplier over the period t1 ~ t2
i s :
t - t
tx 4 (8)
Ass~lming the voltage is constant and equal to the peak
amplitude kv Vm, over the period of time tl + t2,
gives:
v Vm Vref [e2 + tl] ( )
Thus,
~ t = l [I + V ] (lO)
1 2 [ Vref] (11)
If Rs is the resistance of the switch 40, in
series with Rl and R2, R = RS+Rl+R2, and the switch is
closed during t2, then the mean value of the power re-
lated current Ip, assumin~ that it is flowing to virtual
ground, i~ given by:
~309L3Z49
tl + t2
- I 2 t l Vc(t)dt (12)
If the switch is closed during tl, the mean
value of the current Ip(t) is
Ip = R el + t2 J VC~t)dt (13)
Assuming the current is constant and equal to the peak
amplitude Im, over the period tl + t2, combining Equa-
tions lO and 12, gives:
R k I k V R k I
R I = sh c m ~ v m sh c m (14)
Combining Equations ll and 13 gives:
R I = ~ kc m v m sh c m (15)
25For sine wave ~ignals over a long period of time T,
much longer than (tl + t~), the mean current ~ is:
= l J I dt (16)
V ~I cos ~
~ = ~ RSh-kv-kc- 2 2~V~e~ R (17)
where Vm and Im are the respective peak amplitudes,
while ~ is the phase shift of the current with respect
to the voltage. The influer.ce of the first term of
13~12~9
Equations 1~ and 15 is zero because the mean voltage
acros~ the shunt at the secondary of a current trans-
former i~ zero.
Thus, for positive power, the mean value of
the current Ip will be positive when the sign bit is 0
and negative when the sign bit is 1. ~or negative power,
the mean value of the current Ip will be negative when
the sign bit i9 0 and positive when the sign bit is 1.
Trianale Wave Siqnal Generator 35
The triangle wave signal generator 35 shown
in block form in Figure 2 is shown in further detail in
Figure 4. Figure 5 is a timing diagram of the signals
used in Figure 4. In Figure 4, the generator includes
a digital-to-analog converter shown generally on the
left side of the figure, and a charge transfer circuit
shown generally on the right side of the figure. The
digital-to-analog converter, under control of the up/down
counter signals Q1, QlB, Q2 . . . ~6, Q6B provides a
pair of voltages, arbitrarily designed MSV and LSV,
which cause charge to be stored on different sized ca-
pacitors Cl and C3, which charges are then combined by
the charge transfer circuit to produce VtW(t)--th~ tri-
angle wave signal.
The converter portion includes a series of
cascaded N type MOS transistors 52-79 connected along a
resistive ladder having resistors 80-86. By being fab-
ricated in integrated circuit form, the resistances of
each of resistors 80-86 may be made almost identical,
and if necessary, may be trimmed usin~ a laser or other
well known techniques. A potential Vref, preferably
-3.6 volts, is applied to one terminal of the uppermost
resistor 80, while the lowermost terminal of the last
resistor in the chain, resistor 86, is connected to
ground.
Two pairs of transistors are connected in
parallel acro s each resistor, one pair on the right,
most significant voltage side, and one pair on the left,
1301249
least significant voltage side. For example, transis-
tors 68 and ~9 are connected in parallel across resistor
82, a~ are transi~tors 60 and 61. Similarly, transistors
61, 62, 69 and 70 are connected in parallel across re-
sistor 83. Alternating transistor~ in a given columnhave gate~ connected to a common source of input signals.
Thus, transistors 5~3, 60, 62 and 64 are connected to
operate under control of a control signal Ql. The remain-
ing transistors in that column, that is, transistors
59, 61, 63 and 65 are connected to be controlled by the
complement to the control signal Q1, that is, QlB.
Each pair of the innermo~t columns of transi~tors, in
t~lrn, is connected in a similar manner to another tran-
sistor. For example, parallel-connected transistors 60
and 61 are serially connected to transistor 55 controlled
by Q2B. Parallel-connected transistors 62 and 63 are
serially connected to transistor 56 controlled by Q2.
This cascaded arrangement of transistors is continued
to a pair of output line~ for the most and least signif-
icant voltages.
The most significant voltage is so named be-
cause capacitor C1 has eight times the capacitance of
capacitor C3, and accordingly, the voltage on line MSV
has more effect on the output signal Vtw(t) than does
the voltage on line LSV. Capacitor C2 has A capacitance
equal to the sum of the capacitances of capacitors C1
and C3. The MSV and LSV output lines, in turn, are
connected to a charge transfer circuit 90, from which
the triangle wave output signal Vtw(t) originates. As
earlier shown by Figure 2, the triangle wave signal is
coupled over line 32 to comparator 30.
The charge transfer network includes three
capacitors C1, C2, and C3 which are connected around an
operational amplifier 94. This network transfers the
weighted electrical charges placed on capacitors C1 and
C3. Clock signals ~ 2, ~3, and ~4 control switches
so labeled which transfer charge from the two output
1301249
lines onto the capacitors C1 and C3 and then onto capac-
itor C2. The switches controlled by -these clock signals
each are formed by a CMOS structure in which a P channel
device is connected in parallel with an N channel device.
The circuit shown in Figure 4 provides a highly
linear triangular wave with consistent peak-to-peak
amplitude. For example, by employing a 6-bit plus sign
bit converter, the current-voltage multiplier has better
than 0.1% voltage linearity. To facilitate testing of
the completed converters and enable uniform quality
through large numbers of integrated circuits, a digital-
to-analog converter, instead of an analog circuit, i3
employed. The clock generator 93 driving the triangle
wave generator is synthesized on the chip. The spectral
noise of that clock guarantees that the triangle wave
frequency is not locked to the power distribution syqtem
frequency.
The up-down counter functions to select a
single tap on the resistive ladder, and therefore one
of the eight different potentials available, to be sup-
plied as the most significant voltage output from the
converter, as well as a single tap and corresponding
potential to be supplied as the least significant volt-
age output of the converter. The most and least sig-
nificant voltage~ are weighted by the relative capaci-
tances of capacitors Cl and C3. Tlle circuit is designed
such that C1/C2 is 8/9 and C3/C2 is 1/9. These ratios
may be achieved with high accuracy by the photolitho-
graphic techniques employed in the formation of capaci-
tors in integrated circuit structures. Once the volt-
ages are presented on the output lines, the clock sig-
nals controlling the switches transfer charge induced
by these potentials onto capacitor~ C1 and C3, and then
in turn, from each of C1 and C3 onto capacitor C2.
Because capacitor Cl has eight times the capacitance of
capacitor C3, the potential on line MSV as it is switched
from tap to tap will define eight large steps in the
130124g
1~
output signal Vtw. Within each one of these large steps,
the smaller effect of the potential on line LSV, because
of the smaller capacitance of C3, will define eight
smaller steps within each large step.
Capacitor C2 acts as a feedback loop for the
operational amplifier 94. After transients pass, the
output current from amplifier 94 will be null. Thus,
all of the charge will be stored on capacitor C2, and
the voltage at the amplifier output will be a linear
combination of the most and least significant voltages.
Figure 5 shows the interrelationship of the
~ignal~ supplied to and from the circuit of Figure 4.
Signals Ql to Q6 are shown but not their complements.
The use of these signals to control the converter sig-
nals may be most readily understood by an example.Notice that at instant A, Q2 i9 high and all other coun-
ter signals Ql, Q3-Q6 are low. This pattern turns on
transistors 53, 56, and 63 (as well as others) on the
least significant side and transistors 73, 77 and 79
(as well as others) on the most significant side. Thus,
the MSV is connected to ground and the LSV to the tap
between resistors 84 and 85. Therefore, the MSV is
ground, and the LSV is two small steps below ground
(Vref is negative). The level of Vtw thereore is the
weighted combination of the MSV and LSV itl COlljUllCtiOn
with the previous step lev~el of Vtw. B~ changing the
phases of clock signals ~3 and ~4 at time tchS as shown
in Figure 5, the waveform Vtw is inverted when it reaches
0 to provide a triangular waveform oscillating between
positive Vref and negative Vref.
For a positive transfer with cloc]~ ~3 equiva-
lent to clock ~1 and cloc~ ~4 e~uivalent to clock ~2,
Vtw is negative, and the charge transfer occurs as fol-
lows:
~30124
~,
Qcl(n) C1 (MSV - Vtw(n))
Qc3(n) C3 (LSV - Vtw(n)) (18)
Qc2(n) C2 (Vtw(n) - V0)
where Qc(n) is the charge on a capacitor during the nth
cycle, Cn i~ the capacitance of capacitor Cn, and V0 is
the offset voltage of the operational amplifier.
As soon as the n+l cycle starts, a charge
transfer on capacitor C2 occurs, then the charges on
capacitor~ Cl, C2, and C3 are given by:
QCI(n+l) = -vocl
QC3(n+l) = -VoC3
(19)
Qc2(n+1) = Qc2(n) + ~Q
~Q = C3(LSV - Vtw(n)) + VoC3 + Cl(MSV - Vtw(n)) + VoCl
If Cl+C3 = C2, then
Vtw(n+l) = C2 + V0
Vtw(n+1) = LSV C2 + MSV C1 + V0 (20)
Equation 20 shows that the step n+l is not influenced
by the step n.
For a negative transfer with clock ~3 equiva-
lent to cloclc ~2 and clock ~4 equivalent to clock ~l,
Vtw is positive, and the charge transfer is computed
similarly, as shown by the equations below.
~301249
Qcl(n) = Cl VtW(n)
QC3(n) = C3 VtW(n) (21)
5CC2(n) - C2(Vtw(n) V0)
Qcl(n+l) = Cl(Vo-~lSV)
10Qc3(n+1) = C3(Vo-LSV) (22)
Qc2(n+l) = C2(vtw(n)-vo) + ~Q
~Q = C3(Vo-LSV) - C3-Vtw(n) + Cl(Vo-MSV) - CI Vtw(n) (23)
Vtw( ) V C2 MSV C2 V0 (24)
The use of phases ~3 and ~4 enables an invert-
ing or noninverting output by controlling the charge
transfer to capacitor C2. Because the offset voltage
VO shifts both the positive and negative phase of the
triangular wave, the offset voltage of the amplifier
does not affect the accuracy of the multiplier. Also,
obtaining the negative values from the converter using
the same resistive network and the same capacitors as
~ 30 the positive values makes the output signal linear through
zero. Thus, although each step in the waveform is related
to the reference voltage and the capacitance of capacitors
Cl, C2 and C3, the steps are not related to the quality
of the operational amplifier 94. For this reason, and
because of the stability of the clock over any given
small number of cycles, the resulting triangular wave-
form is highly linear. The particula~r ratios of
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,o
capacitorq Cl and C3 to C2 are related to the number of
bits n used in the digital-to-analog converter. In
particular:
C3 = /z and C2 = ~ (25)
The triangle wave signal generator 35 is sen-
Ritive to the stability of the voltage reference source.
If this source drifts, error~ will be introduced. In
particular, the peak-to-peak consistency of the trian-
gular wave relies upon the stability of the reference
voltage. To achieve the desired stabiLity, the refer-
ence voltage i9 generated in the manner described in
conjunction with Figure 15. The reference voltage gen-
erator is fabricated on the same integrated circuit as
the other circuitry described herein.
Figure 5 shows the resulting triangular wave
signal Vtw(t). For a 7-bit converter (6-bits plus sign
bit), the wave signal has 252 steps, 63 for each quarter
of a period. The peak to peak amplitude of the trian-
gular wave is twice the reference voltage.
Voltaae ComParator 30
Figure 6 is a more detailed schematic of vol-
tage comparator 30, previou~ly show in block form in
Figure 2, as well as the sub~equent signal path for
generating the switch command signal. Figure 7 is a
timing diagram of the signals used in Figure 6. The
circuit of Figure 6 compares the output voltage Vv(t)
from the voltage transformer 20 with the triangular
wave Vtw(t) and depending upon the comparison issues a
switch command signal to operate the switch 40.
In Figure 6, signal Vv(t) from voltage trans-
former 20 is supplied to node 100 while the trianglewave signal Vtw(t) is supplied to node 102. Nodes 100
and 102 are switchably connectable to a capacitor C4 by
1301249
-~(
switches controlled with clock si~nals ~l and ~2, which
are the same clock signals used in the triangle wave
generator. In this manner, the comparator is synchro-
nized to the triangle wave generator. The other elec-
trode of capacitor C4 is connected to voltage comparator30, while the other node of comparator 30 is connected
to capacitor C4 under control of a clock signal ~21.
The voltage comparator must function on the
full peak-to-peak range of the triangular wave signal.
Because ~tandard voltage comparators built in CMOS tech-
nology do not have a wide common mode input voltage,
comparator 30 i8 driven to have its output controlled
when its input voltage is close to ground.
The additional clock signals shown in Figures
6 and 7, that is, ~21 and ~11, are so designated because
of their relationship to the clock signals ~1 and ~2.
In particular, ~21 is on (high) during a short portion
of the time when ~2 is on, and ~11 is on during a short
portion of the time when ~1 is on. The switches con-
trolled by these signals are closed when the signalsupplied is on.
The output terminal of comparator 30 is con-
nected to one input terminal of XOR gate 45, while the
sign bit signal NP is supplied to the other input ter-
minal. Gate 4S, in turn, drives one input terminal ofa D-type flip-flop 105, while the other input terminal
of flip-flop 105 is connected to receive siynal ~11,
thereby clocking the flip-flop. The output of flip-flop
105 provides the switch command signal M~, and its com-
plement, to drive CMOS switch 40. Because the clocksignal ~ll driving D-type flip-flop 105 always follows
~1 by a predetermined amount of time, a mean delay ts
is introduced in the multiplier.
As shown by Figure 7, Vv(t) is tored on capaci-
tor C4 by closing ~2 and ~21. At a slightly later time,~1 allows signal Vtw(t) to be applied to capacitor C4.
The resulting voltage Vi on capacitor C4 is given by:
130~2A9
Vi = VV(tl) ~ Vtw(t2) (26)
Thus, the comparator output will be determined by the
greater of Vtw and Vv. Thus, if Vi is less than zero
(the triangle wave amplitude exceeds the input voltage)
and the negative power bit NP i 0, then the switch
command will be 0. In contrast, if Vi is greater than
zero while NP is 0, then the switch command is 1.
CMOS Switch 40
Figure 8 is a more detailed schematic of the
CMOS switch 40 previously shown in block form in Figure 2.
The switch includes a pair of complementary MOS devices
110 and 120 connected to receive the switch command
signal and its complement from the D-type flip-flop
outputs in Figure 6. The N and P channel devices 110,
120, are connected in parallel to control the supply of
potential from the current transformer 24 to the current
to frequency converter 50 (shown in Figure 2). The
CMOS devices are designed with geometries such that the
equivalent conductance of the switch is symmetrical
around zero. The complementary devices make the switch
highly linear, that is, having ~Iniform characteristics
regardless of the polarity of the applied potential
Vc(t). The CMOS switch 40 provides no OlltpUt signal
when open and yet provides a current Ip(t) related to
the applied potential Vc(t) when the switch is closed.
In Figure 8 resistors R1 and R2 are show n,
as are the parasitic gate/source and gate/drain capaci-
tances associated with each of the N and P channel de-
vices. Three major sources of parasitic current have
been minimized in the switch 40 depicted. These are
currents in the parasitic capacitors generated by the
clocked switch command signal applied to the transistor
1~0~249
~3
gates, current due to the change in the gate-channel
capacitance and current from the reverse biased diodes
of the P and N channel transistors.
The equivalent resistance of the switch in
series with the polysilicon resistors R1 and R2 is de-
signed to be collstant over the dynamic range of the
input voltage Vc(t). Charge injection is minimized and
the linearity of the equivalent resistance around zero
optimized when the geometry factor W/L of the P and N
channel MOS transistors satisfy the equation below,
where w is the width, L is the length, ~ is the mobility
and Cox i~ t~e capacitance per unit area of the dielec-
tric.
(w) ~ C0x = (L)n ~n ox (27)
In the preferred embodiment Rl and R2 each will be about
5000 ohms, while the series resistance Rs of the switch
will be about lOO ohms. Charge injection caused by
capacitive coupling between the pulsed signal driving
switch 40 and the output of the switch is eliminated
and current injection minimized by evenly dividing the
resistance between resistors Rl and R2. Without this
care in the design of the switch 40 power measurement
errors would be considerably greater than permissible.
The current Ip(t) from the switch is related
to the power consumed or generated in the distribution
system. How this current is converted to a signal which
varies in frequency according to the power measured is
described below.
1;~0~9
. ~
~S
Charqe-Balanced Converter 50
One voltage-current multiplier circuit de-
scribed above is used for each phase in the distribu-
tion system. Figure 9 i8 a schematic of the charge-
balanced converter 50 for converting current from oneor more of the multipliers to a frequency signal. For
illustration the system shown in Figure 9 assumes a
three-phase system with three multipliers; however, it
will be apparent that as many or as few phases as desired
may be metered. Figure 10 is a timing diagram of the
signals used in Figure 9. In Figure 9, tlle converter
50 is shown as receiving signals from three phases.
The output voltage~ Vc(t) from the current transformers
for each of the three phases are applied to nodes 141,
14~, and 143. The switch command signals M~l, M~2, and
M~3 are supplied to terminals 144, 145, and 146. As
previously explained, the switch command signals are
exclusively ORed with the negative power signal NP by
gates 45 to control switches 40 associated with corre-
sponding phases. The output signals from the switchesthen are summed at a node NIN. A fourth switch 177
coupled to a reference potential -Vref through resis-
tance Rr is connected in parallel with the three phase
switches. As will be explained further below, current
from the reference switch 177 is used to balance current
from the phase switches.
The three switcheq 40 for the currellts from
the pha3es, and one switch 177 or the reference poten-
tial, are all matched by being fabricated ~Ising ratioed
geometries. By fabricating all the CMOS switches and
associated resistors in close proximity on the inte-
grated circuit die, the temperature effect are compen-
sated, because temperature will have the same effect on
the resistance Rr associated with switch 177 as on the
other resistors. Additionally, drift due to long-term
temperature instability of all of the resistors will
~01249
..
~6
vary in the same manner, again effectively cancelling
each other.
For the phase current inputs the resistances
are Rl+R2+Rs while for the reference voltage the resis-
tances are resistor Rr and switch resistance RrS where:
R R
r = r~ (28)
Rl+R2 Rs
Only a single resistor Rr is used with switch 177 in-
stead of the pair of resistors used with the other
switches. This allows all of the switcheq to operate
at around zero volts and minimizes the CMOS "body" ef-
fect. The charge injection influence of qwitch 177 is
proportional to the load. At full load this charge
injection, about S nanoamps, is much lower than the
re9et current Vref/(Rr+Rrs), about 200 microamps-
Summing node NIN is connected to the invert-
ing input of a special purpose operational amplifier
15~, while the noninverting input of amplifier 150 is
grounded. A capacitor C5 is coupled across the ampli-
fier 150, as is a switch 152 which operates under con-
trol of a reset capacitor signal RCAP. The output ter-
minal INT of amplifier 150 is connected to an input
terminal of voltage comparator 160 which in turn con-
trols a D-type flip-flop 162. The other input terminal
of flip-flop 162 is connected to receive a very stable
highly precise clock signal F1 from a crystal controlled
oscillator. The output terminal INT of the operational
amplifier 150 also i~ connected through level detectors
164 and 165 to one input terminal of the XOR gate 170.
The output of XOR gate, together with signal F2, also
derived from the crystal controlled oscillator, control
another D-type flip-flop 175 to deliver the negative
power sign bit signal NP.
The circuit in Figure 9 operates as follows.
The voltage controlled current from each of the measured
130~249
.- ~
phases is delivered to summing node NIN, where it is
integrated by the capacitor C5 (switch 152 is open).
As charge accumulates on capacitor CS, the output signal
from the operational amplifier 150 decreases. At about
S zero volts, comparator 160 will drive flip-flop 162,
which at the next clock signal F1, provides signal IMPRC
to close switch 177. Switch 177 connects reference
voltage -Vref to summing node NIN, thereby supplying a
calibrated negative current which balances the effect
of the positive currents from the phases on capacitor
C5. Therefore, charge is removed from the capacitor
C5. As the potential on node INT increases, the compar-
ator 160 i~ deactivated and the reference potential is
disconnected. Current from the phase switches, then
causes charge to be again stored on capacitor C5 to
repeat the process. The pulses in the IMPRC signal in
Figure 10 show how this process is repeated whenever
the potential of the summing node NIN reaches the ap-
propriate level.
The above process functions satisfactorily
unless the sign of the current from the phases being
measured and the sign of the current from -Vref are the
same. In this case the charge supplied to node NIN
will not balance, and more and more charc3e will be ac-
cumulated by capacitor CS. Eventually, the operational
amplifier 150 output voltage will reach Vth (see Fig-
ure 10) which i9 about 3 volt~. This thLeshold voltage
is sensed by the level detectors 164, 165, and causes
XOR gate 170 at the next clock pulse F2 to drive flip-
flop 175 and chancJe the sign of the negative power bitNP. At the same time, other logic, not shown, turns on
signal RCAP to reset capacitor CS and restart the process.
Because the sign of bit NP is fed back to the gates 45
controlling the switches 40 associated with the three
phases, operation of the comparator 160 will resume
with the polarity of the reference currellt being oppo-
site the polarity of the current from the multipliers.
1.30~249
~?
Over a given period of time, the amount of
time signal IMPRC is active is a measure of the energy
consumed or supplied. This period of activity is mea-
sured with great accuracy by a crystal controlled clock
which provides signal F1. If the period of time is T
and the number of pulses is N, then:
T ~ = 1l . ~ ) N ( 2 9 )
Solving for N, with Rref = Rr+Rrs = k(R1~R2+R5) = k~R
N = ~ ref (30)
Substituting from Equation 17:
T Fl Rsh~kv~Vm kc Im Cs~ Rref
(3l)
2 5N = -- s h v m c m ~ k
Using K = the product of the constants and F1 = t
K(V I cos~)
30N = T t ' V 2 (32)
ref ref
Therefore, the frequency is
~30~2A9
~2
K-V I cos~
r = t V 2 (33)
ref r~f
The output signal IMPRC from the circuit shown
in Figure 9 is a signal having a pulse rate proportional
to the sum of the products of the input voltage and
current for each of the phases. Thus, for n phases,
where i is the phase:
F = t l ~Kl Vmi Imi (3 )
ref re~ n
This output signal can directly drive a single coil
stepping motor for a mechanical digital or analog display
of the power consumed by the application. For conven-
tional analog display residential power meters such as
employed in the United States, the output pulses will
drive an analog mechanism to display the power consump-
tion on a series of dials or drive a digital cyclometer
register. If the output pulses are used with an elec-
tronic display, the stepping motor output is not used,
and the power sign NP indication allows power consumed
and supplied to be measured using separate registers,
or for the consumption and supply of power to be summed.
Additionally, the output signal may be employed in a
varie~y of other applications, for example, by being
used to provide feedback into the application consuming
or supplying power to regulate it in a desired manner.
Figure 11 is a block diagram illustrating the
function of operational amplifier 150 shown in block
form in Figure 9. In the block diagram of Figure ll,
the operational amplifier 150 includes an input node
Vin, an inherent offset voltage Voffset, and an output
node from which the output voltage V0ut is supplied.
The feedback loop includes feedback of the main opera-
tional amplifier 183 having a gain G3, a self-biasing
130i24~
~9
amplifier 181 having a gain G1, and a coupling amplifier
182 having a gain G2 If the self-biasing and coupling
ampli~iers have different polarization levels by an
amount ~V (mismatching of bias voltages), then when the
output voltage on VOut is zero, the input voltage on
Vin is the residual voltage
10~V G2 + Vin Gl G2 + (Vin + Voffset) out
for VOUt = 0, Vin = VresiduAl
15Vresidu~l= Gl G2 + G3 (36)
If Gl snd G2 '> G3, then
V = V G3 + ~V _ ~V (37)
20residual offset Gl G2 Gl Gl
With ~V ~ 50 mV and G1 ~ 50,000, the residual voltage
will be less than l~V
To reduce the effect of the offset voltage
2 Voff of Gl when G1 i8 amplifying the residual voltage
on NIN, an autobiasing technique is employed, which is
shown in more detail in Figure 12 Figure 13 is a tim-
ing diagram for the signals used in Figure 12 The
circuit of Figure 12 includes a representation of the
gain G3 of the main operational amplifier 183, the gain
G2 of the coupling amplifier 182, and the gain G1 of
the self-biasing amplifier 181 Gain G4 represents the
gain of the coupling amplifier in the slave amplifier
Amplifier 181 is connected to BIAS switch 187, zeroing
switch 188, and summing node 191 Amplifier 183 is
connected to both the zeroing switch 188 and the input
~01249
~o
terminal NIN, as well as to a second summing node 193,
in turn connected to the output terminal INT. Ampli-
fier 182 is connected between the autozeroing switch
186, capacitor C7, and a summing node 193, while ampli-
fier lB4 is connected to the ABIAS switch 185, capacitorC6, and summing node 191.
The operation of the circuit shown in ~igure
12 may be understood with reference to Figure 13. When
the BIAS signal (high) closes switch 187, the input to
amplifier 181 will be grounded. A waiting time tw after
closing switch 187 allows discharge of all parasitic
capacitances and avoids transferring the wrong bias
information to amplifier 184. After the waiting time
tw, the ABIAS ~ignal (high), closes switch 185. The
loop gains G1 and G4 stabilize the potential VABIAs on
capacitor C6 in such a way that amplifier 181 remains
in its linear zone of operation to compensate for Voff2.
Switch 187 is opened when BIAS goes low. At
the same time the ZERO switch 188 closes to allow the
input voltage on node NIN to be suppliad to amplifier
181. A short time later, signal AZ closes switch 186
completing the feedback loop. The time between the
bias signal going low and the closing of switch 186 by
signal AZ assures that the voltage held by capacitor C7
i~ related to the residual ofset on node NIN alone and
not related to switching noise. During the time signal
ABIAS is high, capacitor C6 is loaded with voltage VABIAs.
Input NIN then is amplified by Gl to feed capacitor C7
with a voltage VAz which is amplified by amplifier G2
to provide a correction to node 193 to correct output
INT. VAz is the voltage required on capacitor C7 to
ce Voff to Vresidual through summing node 193.
By fabricating amplifiers G2 and G4 in the
same manner with the same geometries and polarization,
the ~V effect (see Equation 34) is reduced, and an off-
set-free system is provided for the main amplifier G3.
~30~249
`~-
The structure also compensates for short-term and long-
term temperat~re drift.
Fiqure 14 is a detailed circuit schematic of
the autozeroing operational amplifier 150 shown in bloc]~
form in ~igure 9. Amplifier 150 includes a master oper-
ational amplifier 200 and a slave operational amplifier
210. The circuit is connected to receive the BIAS,
ZERO, ABIAS, and AZ signals described in conjunction
with Figure 13. Transistor 185 is the ABIAS switch,
transistor 186 is the AZ switch, while transistors 187
provide the BIAS switch and transistors 188 the ZERO
switch. The extra transistors 216 and 217 are dummy
transistors to balance charge injection into the capac-
itors C6 and C7, thereby avoiding any dependence on the
frequency of the BIAS signal, approximately 256 Hz.
In the master operational amplifier 200, the
transistors have been assigned reference numerals ending
with "a", while corresponding transistors in the slave
amplifier have reference numerals ending with "b." In
the master amplifier transistors 304a and 306a provide
a cascode stage, transistors 300a and 301a form the
load, while transistor 303a controls the load. Transis-
tors 305a and 307a are a differential pair. Transistor
302a is the output stage with transistor 311 acting as
a current source. Transistor 312 provides a current
source for biasing the buffer transistor 308. Capacitor
C8 provides open loop stabilization.
The master amplifier 200 uses the voltage
across capacitor C7 to control the polarization level
of transistor 303a, a p-channel MOS device. A p-channel
device is employed rather than an n-channel device be-
cause of its reduced drift characteristic. In contrast,
because o their superior gain, n-channel devices are
employed for the differential pair 305a and 307a. Chang-
ing the polarization level of transistor 303a change~the behavior of the differential pair 305a, 307a, thereby
changing the master amplifier s input offset voltage.
~301249
To compensate for long term drift, as well as
for changes in temperature, it is desirable to change
the voltage across capacitor C7 appropriately. This is
the function of the slave amplifier 210. The operation
of the slave amplifier 210 is similar to the master
amplifier 200 in that transistor 303b controls the load
300b, 3.01b in response to the potential across capacitor
C6. The resulting changes in operation of the differ-
ential pair 305b, 307b, drive the output stage 302b,
which as will be explained, through AZ switch 186 allow
changing the potential on capacitor C7 as appropriate.
When the bias switch 187 is closed, the gates
of transistors 305b and 307b are shorted together through
the switch, and therefore both are connected to receive
the potential on node NIN. With the BIAS switch 187
held closed, the autobias (ABIAS) switch 185 is closed
(see Figure 13 for the timing diagram). When this oc-
curs, capacitor C6 is connected to node B, and therefore
biased with VBIA5. In effect, the potential on capacitor
C6 is refreshed periodically.
Switch 185 is then opened, the zero switch
188 is closed and the BIAS switch 187 opened. This
connects the gate of transistor 305b to both the gates
of transistors 306a and 307a to sense any potential
difference with respect to transistor 305b. In effect,
transistor 307a drives transistor 305b. Wherl the auto-
zeroing switch 186 is closed, node B is connected to
capacitor C7 to refresh the voltage Oll it. Thus, the
offset voltage of the master amplifier is reduced to
the residual voltage Vresidual.
Figure 15 is a schematic of the circuit for
generating the reference voltage. As described above,
the accuracy of the power meter is strongly dependent
upon the accuracy of the voltage reference source, e.g.,
see equation 32. The circuitry depicted is a band-gap
voltage source which relies upon the different tempera-
ture sensitivity of base-emitter voltage V~ and change
I3012A9
in base-emitter voltage ~VBE of bipolar transistors.
In particular, transistors 245 and 246 are fabricated
with a different geometry than transistors 240, 241,
242 and 244. Transistors 240-242 and 244 are one-half
the size of transistor 245 and one-quarter the size of
transistor 246. Transistor 244 opera-tes on one-eighth
the current, transistor 245 on one-~uarter the current,
and transistor 246 on one-half the current of transis-
tors 240-242. A voltage divider consisting of resis-
tances R3 and R4, but which may also includin~ trimmingre~istances (not shown), is connected between the emit-
ter of transistor 246 and Vss through transistor 250.
An operational amplifier 260 has one input terminal
connected between resistors R3 and R4, and the other
input terminal connected to the emitter of transistor
240. The output of the operational amplifier 260 is
connected to control transistors 250, 251, 252, 253,
254, 255.
The band-gap reference voltage generator shown
in Figure 15 includes stacked transistors 244, 245, and
246 to generate a band-gap which is triple that of a
single device. The higher band-yap minimizes the effect
of any offset voltage error introduced by the opera-
tional amplifier 260. A series of cascode stages 255
and 25~, 254 and 257, etc., provide calibrated current
sources for the transistors 240, 241, etc.
It i9 well known that the base-emitter voltage
tVBE) of a transistor varies substantially with temper-
ature. For example, a typical bipolar device will have
a VBE which falls with temperature at about -2 millivolts
per degree centigrade. Obviously, over the full operat-
ing temperature range of the power meter, which encom-
passes both very cold and very warm ambient temperatures
(-40C to ~85C), this variation would produce such
large variations in the reference voltage as to destroy
the accuracy of the power meter. It is also well known
that the change in base-emitter voltage AVBE of two
~0~249
,
transistors operating at different current densities
can have a positive temperature coefficient. The cir-
cuit shown cQmbines the two effects to provide a refer-
ence voltage which is substantially independent of tem-
perature. The output voltage at terminal Vref may thenbe buffered and used to provide Vref in Figures 4 and 9.
The V8E of transistors 240, 241, 242 is:
10VBE240 2 = 3 q Ln I1 A (38)
where Is is the saturation current, Il the emitter cur-
15 rent, and A1 the areas of 240, 241 and 242. The VBE of
transistors 244, 245 and 246 is:
VBE244 6 = 3 q Ln I 8-A
20s
Therefore the difference is:
25left rlght
Vre~ VBE ~ R3 (~V~E - V()) (41)
The influence of temperature on kqT is about 85 ~V/C
and on VBE is about - 2 mV/C, (R3+R4)/R3 is about 11.3.
As has been described, the power meter of my
invention provides a highly accurable measure of power
consumed or supplied by a distribution system. Although
a preferred embodiment of the invention has been explained
~301249
, ~6
with reference to specific circuitry, the scope of the
invention may be ascertained from the following claims.
