Note : Les descriptions sont présentées dans la langue officielle dans laquelle elles ont été soumises.
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TITLE OF THE INVENTION
Level Determining Circuit Generating Output Signal at
First or Second Output Terminal according to Level of
Input Signal
BACKGROUND OF THE INVENTIOM
Field of the Invention
The present invention relates generally to level
determining circuits, and more particularly, to a general
purpose type of level determining circuit suitable for
being implemented as a semiconductor integrated circuit.
Description of the Background Art
General purpose level determining circuits with wide
range of applicability have been implemented so far as
semiconductor integrated circuits. As an example of such
level determining circuits, there exists one which
comprises an input terminal and first and second output
terminals for generating an output signal at the first or
second output terminal according to the le~el of an input
signal. Such a level determining circuit is used, for
example, to perform balance control by determining the
respective levels of L and R signals in a balance
adjusting circuit of a stereo system.
BRIEF DESCRIPTION OF THE DRAWINGS
Fig. 1 is a circuit diagram showing an example of the
conventional level determining circuits.
Fig. 2 is a circuit diagram showing a level
determining circuit according to an embodiment of the
present invention.
Fig. 3 is a diagram showing the characteristics of
the embodiment shown in Fig. 2.
Fig. 4 is a circuit diagram showing a level
determining circuit according to another embodiment of the
present invention.
Fig. 5 is a circuit diagram showing a level
determining circuit according to still another embodiment
of the present invention.
Fig. 6 is a circuit diagram showing a modified
version of the circuit shown in Fig. 2.
Fig. 1 is a circuit diagram showing an e~ample of
such conventional level determining circuits. Basically,
the illustrated circuit determines the level of an input
signal for operating in such a manner that it generates a
first output signal at a first output terminal if the
level is higher than a predetermined reference value, or
generates a second output signal at a second output
terminal if the level is lower than the predetermined
reference value.
~eferring to Fig. 1, input signal is applied to a
non-inverted input terminal of a comparing portion 1
through a terminal 19 and a predetermined reference
voltage is applied to an inverted input terminal thereof.
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When an input signal at a higher level than the
reference voltage applied to the inverted input terminal
is applied to the non-inverted input terminal of the
comparing portion l, a positive output signal is generated
from the comparing portion 1. This positive output signal
is supplied to a first output terminal 11 through a diode
2, a resistance 5 and a switch 1~.
~eanwhile, when an input signal at a lower level than
the preceding reference voltage is applied to the
non-inverted input terminal of the comparing portion 1, a
negative output signal is generated from the comparing
portion l. This negative output signal is supplied to a
second output terminal 12 through a diode 3 and a
resistance 8.
lS Operation of the level determining circuit shown in
Fig. l will be described in more detail below. Now,
assuming that input slgnal VIN is greater than reference
voltage VREF, with VIN as an input signal and VREF as a
reference voltage of a reference voltage source 13, the
level V1 of the positive output signal generated at the
first output terminal 11 is defined by the following
expression:
1 (VIN VREF) (R R R ) + VREF .-- ~1)
where R1 through R6 represent resistance values o~
the resistances 4 through 9, respectively.
On the other hand, assuming that input signal VIN is
smaller than reference voltage VREF, the level V2 of the
= 3 =
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negative output signal generated at the second output
terminal 12 is defined by the following expression:
V = (V V ) . 6( 4 1 2 3) ~ V (2)
Therefore, the circuit shown in Fig. 1 operates as a
level determining circuit which generates an output signal
at the first output terminal ll or the second output
terminal 12 according to the level of an input signal.
In addition, the following relation should be
established in order to ensure equal bias voltages of the
diodes 2 and 3.
R2 + R3 = R5 6
In such a level determining circuit as described in
the above, it may be required that either one of the
output signals supplied at the first and second output
terminals should be disconnected by means of a switch for
various reasons. For example, the conventional level
determining circuit shown in Fig. 1 is constructed in such
a manner that supply of the first output signal to the
first output terminal 11 can be disconnected if required.
However, in a conventional example as shown in Fig.
l, if the switch 10 disconnects supply of the first output
signal, impedance on ~he side of the switch 10 with
respect to the node between resistances 5 and 6 will
change corresponding to the opening of the switch lO which
results in fluctuation of the reference voltag2 applied to
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the negative input terminal of the comparing portion l.
Thus, there has been a problem that such switching of the
switch l0 prevents precise determination about the level
of an input signal.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a
level determining circuit capable of determining precisely
the level of an input signal even where one of the output
signals from the comparing portion is disconnected.
Another object of the present invention is to provide
a level determining circuit capable of preventiny
fluctuation in the reference voltage which is applied to
the input terminal of the comparing portion, even where
one of the output signals from the comparing portion is
disconnected.
Briefly stated, a level determining circuit according
to the present invention comprises a reference voltage
source, a comparing circuit for outputting a siynal of one
polarity in accordance with the relation of magnitude
between two inputs, an input terminal for supplyiny an
input signal to one input of the comparing circuit
therethrough~ first and second diodes connected to the
output of the comparing portion to have the opposite
polarities to each other, first and second feedback
resistances each for feeding back the output of the
comparing circui~ which has been rectified b~ the first or
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second diode to the other input of the comparing circul-t,
resistances for applying a reference voltage from the
reference voltage source to each of the first node between
the first diode and the first feedback resistance and the
second node between the second diode and the second
feedback resistance, a first output terminal for supplying
a signal obtained at the first node therethroucJh, a second
output terminal for supplying a signal obtainecl at the
second node therethrough, a buffer amplifier interposed in
at least either one of the first signal path between the
first node and the first output terminal and the second
signal path between the second node and the second output
terminal and a switch for disconnecting the output of the
buffer amplifier.
The primary advantage of the present invention,
therefore, is to be able to prevent the reference voltage
for level comparison from being influenced by the
fluctuation in impedance which is caused by switching a
switch, with the use of a buffer amplifier of high input
impedance disposed in the preceding stage of the switch.
The foreqoing and other objects, features, aspects
and advantages of the present invention will become more
apparent from the following detailed description of the
present invention when taken in conjunction with the
accompanying drawings.
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DESCRIPTION OF THE PREFERRED EMBODIMENTS
Referring to Fig. 2, a level determining circuit
according to an embodiment of the present invention will
be described.
The circuit shown in Fig. 2 is the same as the
conventional level determining circuit shown in Fig. l
except for the following point. That is, the cathode of
the diode 2 is connected to a buffer amplifier portion 14
having a high input impedance and a gain of unity, and a
switch lS is interposed between the output of the buffer
amplifier portion 14 and the first output terminal ll.
Meanwhile, voltage of an output signal outputted through
the switch 15 will be divided by a resistance 16 of
resistance value R2 and a resistance 17 of resistance
value R3. Furthel~ore, a reference voltage VREF from the
reference voltage source 13 is applied to the cathode of
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the diode 2 through a resistance 18 of re~istance value
R7.
Referring to Fig. 2, the inverted input terminal of
the comparing portion 1 receives the reference volta.ge
VREF from the reference voltage source 13 in the initia].
state. Now, when an input signal at a higher level than
the aforementioned reference voltage is applied -to the
non-inverted input terminal of the comparing portion 1
through the terminal 19, a positive output signal will be
generated from the comparing portion 1 (solid line a in
Fig. 3). The output signal then appears at the cathode of
the diode 2. The output signal which has appeared at this
cathode will be fed back to the inverted input terminal of
the comparing portion 1 through the resistance 4 which
functions as a feedback resistance. As a result, a
negative feedback operation will be performed to make the
voltages at the non-inverted and inverted input te.rminals
of the comparing portion 1 equal to the aforementioned
input signal voltage. Therefore, the level V3 of the
output signal obtained at the cathode of the diode 2 (b in
Fig. 3) is defined by the following expression.
Rl+R4+R5+R6
R4 R5 R6
This output signal V3 is passed through the buffer
amplifier portion 14 having a high input impedance and a
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gain of unity and the switch 15, and then divided in
voltage by the resistances 16 and 17 before outputted from
the fixst output terminal 11. Therefore, if the
resistance values of the resistances 16 and 17 are set to
the same values R2 and R3 of the resistances 5 and 6 in
the conventional circuit shown in Fig. 1, the level of Vl
of the output signal obtained at the first output tenminal
11 in the embodiment of Fig. 2 will be given by the same
expression (1) which defines V1 in the conventional
cixcuit shown in Fig. 1.
Meanwhile, an output signal V2' which will be
obtained at the second output terminal 12 in Fig. 2 is
given by the following expression:
V2 = (VIN ~ VREF) .~ ~ REF ( )
where if a relationship defined by the following
expression can be seen between the resistance values R4,
R5 and R6 of the resistances 7, 8 and 9, i.e., if:
R4 + Rs >> R6
the output signal V2' which is obtained at ~he second
output terminal 12 of the embodiment in Fig. 2 will be as
follows:
V2 ' `-- V
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Consequently, it can be said that the output signal at the
second output terminal 12 is held approximately at a fixed
level.
On the other hand, if an input signal at a lower
level than the aforementioned reference voltage is applied
to the non-inverted input terminal of the comparing
portion 1, a negative output signal is generated from the
comparing portion 1 (solid line a in Fig. 3). The output
signal then appears at the anode of the diode 3. The
output signal which has appeared a~ this anode will be fed
back to the inverted input terminal of the comparing
portion 1 through the resistance 7 which functions as a
feedback resistance. The level V4 of the output signal
thus obtained (c in Fig. 3) at the anode of the diode 3 is
given by the following expression.
4 (VIN VREF) -R R + VR~F ... (5)
This output signal V4 is divided in voltage ~y the
resistances 8 and 9 and then outputted from -the second
output terminal 12. Therefore~ if a relationship defined
by the following expression can be seen between the
resistance values R2, R3 and R7 of the resistances 16, 17
and 18, i.e., if:
R7 = R~ ~ R3
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the level V2 of the output slgnal obtained at the second
output terminal 12 of the embodiment in Fig. 2 will be
equal to the V2 as shown by the expression (2) of the
example in Fig. 1.
In this case, the output signal V1' which is obtained
at the first output terminal ll of Fig. 2 will be defined
as follows:
R7 R3
1 7 R2 R3
where a relationship defined by the following
expression can be seen between the resistance values R
and R7 of the resistances 4 and 18, i.e., if:
Rl >> R7
the output signal V1~ which is obtained at the fir~t
output terminal 11 of the embodiment shown in Fig. 2 will
be as follows:
Vl ' '- V
Consequently, it can be said that the level of the output
signal at the first output terminal 11 is held
approximately at a fixed level.
In the embodiment shown in Fig. 2, if there is no
need for the output signal obtained at the first output
terminal 11, the switch 15 may be opened as illustrated.
In this case, since the buffer amplifier portion 14 of
high input impedance is disposed in the preceding stage of
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the switch 15, impedance change due to the opening of the
switch 15 can not exert any in~luence on the preceding
stage of the buffer amplifier portion. Therefore, the
output signal obtained at the second output terminal 12
will not make any change even if the switch 15 is operated
to be opened.
~ hough, in the above described second embodiment, a
description has been made on a case where switch 15 is
interposed in the path of the first output signal, the
present invention is also applicable to the cases where a
switch is interposed in the path of the second output
signal, or switches are interposed in the both paths of
the first and second output signals. Fig. 4 shows another
embodiment of the present invention in which a buffer
amplifier portion 21 and a switch 22 are interposed in the
path of the second output signal, and Fi~. 5 shows still
another embodiment of the present invention where the
buffer amplifier portion 14 and the switch 15 are
interposed in the path of the first output signal, and
further the buffer amplifier portion 21 and the s~itch 22
are interposed in the path of the second output signal.
Also in these embodiments, a buffer amplifier portion is
provided in the preceding stage of each switch so that a
level determining circuit can be provided which is not
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influenced by the change in impedance caused by opening of
a switch.
Furthermore, Fig. 6 is a circuit diagram showing a
circuit equivalent to the portion 30 comprising the buffer
amplifier portion 14 and the switch 15 shown in Fig. ~.
If the buffer amplifier 14 and the switch 15 are
integrated as shown in fig. 6, the number of the elements
can be reduced in implementing the circuit as an
integrated circuit.
Although the present invention has been described and
illustrated in detail, it is clearly understood that the
same is by way of illustration and example only and is not
to be taken by way of limitation, the spirit and scope of
the present invention being limited only by the terms of
the appended claims.
