Note : Les descriptions sont présentées dans la langue officielle dans laquelle elles ont été soumises.
l3nql7l
-1- RCA 84, 021A
ON/OFF CONTROL CIRCUITRY FOR TELEVISION
The invention relates to an arrangement for
reducing the power consumption in a television circuit
during a period when such cixcuit is not required to
perform at least some of i~s functions.
A television receiver, for example, may include a
pulse-width modula~or or voltage regulator that generates a
pulse-width modulated cont.rol signal at a horizontal
related frequency. The control signal c~ntrols a run power
supply that supplies run supply voltage such as a regulated
B+ supply voltage. The B~ supply voltage energizes a
horizontal output stage during a power-up mode. The
~~ voltage regulator circuitry may be combined with a
horizontal deflectlon circuitry and incorporated in an
lS integrated circuit (IC) that is referred to herein as the
deflection IC. The horizontal drive circuitry generates a
horizontal drive signal that is coupled to a horizontal
output stage. The deflection IC may be reguixed to operate
selectively in a power-up mode and in a standby mode in
accordance with an on/off control signal provided by a
remote receiver in the power-up mode. Such pulse-width
volkage regulator may be required to supply the pulse width
modulated control signal for controlling the run power
supply thak generates the regulated 8~ supply voltage used
for operating deflection circuitry of a horizontal OlltpUt
stage of the receiver. When operation in a standby mode is
required, such control signal may be required to prevent
the power supply from energizing the deflection circuitry
until such time as a user initiates a power~up command via
the remote receiver that causes a start-up interval to
begin.
A first portion of the deflection IC that
includes, for example, ~he main voltage regulator and the
horizontal deflection circuitry may be required to ~e
energized during the power-up mode and during a start-up
interval but may not need to be energized during the
standby mode. On the other hand, the deflection IC may
include a second portion, such as a shunt regulator
. .
,
130ql71
-2~ RCA 84,021A
internal to the IC, for example, that is required to be
energiæed during both the power-up and the standby modes.
In one prior art circuit, a shunt switch is
coupled between ground and a supply voltage receiving
terminal of the deflection IC that receives an energizing
voltage that supplies the entire power requirements of the
deflection IC. During operation in the standby mode, the
shunt swltch that .is controlled by the on~off control
signal develops a low impedance between the terminal and a
common conductor such as ground that reduces the energizi~g
voltage to, approximately zero volts that disables the
deflection IC Disadvantageously, such shunt switch, when
conductive, causes a substantial power dissipation.
The .remote receivex, for example, may be
energized, during both the power-up mode and the standby
mode, by a separate standby power supply. The standby
power supply may include a standby transformer having a
primary winding that is coupled to an alternating current
(AC) mains supply source. A voltage that is developed at a
secondary winding of the transformer may be rectified to
produce a DC standby energizing voltage.
The standby energizing voltage and a run supply
voltage of ~he run power supply may ~e selectively applied
to a supply voltage receiving terminal of the deflection IC
to form an energizing voltage at such terminal that
energizes the deflection IC. The standby energizing
voltage energizes those portions of the deflectio~ IC that
are re~uired to be energized during the standby mode and
during the start-up interval; whereas during the power-up
mode, the run~mode power supply provides the entire or
principal energi~ing voltage to the terminal of the
deflection IC.
It may be desirable to reduce the supply currPnt
that is re~uired from ~he standby transformer so as to
reduce the cost of such tra~sformer. To this end, it may
be deslrable to reduce the current consumption of the
deflection IC during the standby mode.
1 309 1 7 1 _3_ RCA 84,021A
In accordance with an aspect of the invention,
during the standby mode, the on/off control signal provided
by the rernot~ receiver is coupled to the deflection IC to
cause a reduction of energizing current consumption that is
supplied by the standby po~er supply. Without the operation
of the on/of control signal, current that is supplied by
the standby power supply would flow in the first portion of
the deflection IC that need not be energiæed during the
standby mode.
In carrying out a feature of the invention, the
deflection IC receives its energizing voltage at the same
terminal during both the power-up mode and the standby
mode. Such arrangement advantageously simplifies the
construction and design of ~he deflection IC, for example,
by reducing the number of external connections, and also,
interconnection between the deflection IC and other
television circuitry within the television receiver.
In carrying out another aspect of the invention,
reducing the energizing or supply current of the deflection
IC is accomplished by applying the on/off control signal
during the standby mode to corresponding control electrodes
of predetermined selected stages of the defl~ction IC.
Such selected stages are required to be active only during
the normal operation power-llp mode~ In this way, the
energizing current in the deflection IC during the standby
mode is reduced. The energizing current consumption i6
reduced, advantageously, by reducing during the standby
mode the quiescent current in each corresponding stage in
accordance with the on/off control signal.
In accordance with a further aspect of the
invention, the quiescent current in a given stage of the
deflection IC is temperature compensated in accordance with
` ` a temperature compensated control signal, during the
power-up mode. However, during the standby ~ode, the
temperature compensated control signal is at a second level
that switches off the guiescent current in the given stage.
A deflection circuit of a television apparatus
embodying the invention produces a deflection current in a
`
~. . . .
,
1309171
4 RCA 84,021A
deflection winding during operation in a power-up mode. A
source of a first supply voltage is developed during
operation of the television apparatus in each of the
power-up and in a standby mode. A con~rol circuit is
coupled to the deflection circuit for controlling the
operation of the deflection circui-t during operation in the
power-up mode and for preventing the production of the
deflection current during operation in the standby mode.
The control circuit includes at least a first circuit stage
that is coupled, during operation in each of the power-up
and standby modes, to the source of the first supply
voltage to form a current path. A first portion of a
supply current flows in the current path from the source of
the firs~ supply voltage during operation in the power-up
mode. A source of an on/off control signal that is
selectively indicati~e of operation of said television
apparatus in the power-up mode and in the standby mode is
used for generating a second control signal during
television apparatus operation in the power-up mode. The
second control signal is applied to the first circuit stage
to control the first poxtion of the supply current. During
operation of the television apparatus in the standby mode,
the second control signal causes the first portion of the
supply current that flows in the first circuit stage to be
reduced.
In the Drawing:
FIGURE l, that includes portions lA and lB,
illustrates a television power supply including a
deflection IC embodying the invention; and
FIGURES 2a-2b illustrate waveforms useful for
explaining the operation of the deflection IC of FIGURE 1
during the start-up inte~Jal.
FIGURE 1 illustrates a portion of a television
re~eiver incorporating a deflection IC 100, embodying the
invention. Such portion of the television receiver
includes a bridge rectifier 101 that rectifies a mains
supply voltage V~c to produce a DC, unregulated voltage
VuR. A conventional power supply output stage or switch
1 30q 1 7 1 5 RCA 84,021A
regulator 102, that may include a silicon controlled
rectifier (SCR) produces during a normal operation power-up
mode a regulated voltage B~ that is coupled to a flyback
transformer Tl. An input supply terminal 102c of regulator
102 is coupled to unregulated voltage VuR. Regula~ed
voltage B+ is developed at an output terminal 102d of
switch requlator 102. Transformer T1 is coupled to a
collector electrode of a deflection switching transistor Ql
of a hori20ntal circuit output stage 99 operating at a
horizontal rate fH. A control signal Hr, at the horizontal
rate f~, that is produced in a corresponding por~ion of
deflection IC 100, referred to herein as a horizontal
~- processor lOOa (Fig. lB~, is coupled via a horizontal
driver 666 to the base electrode of transistor Ql. The
frequency of signal Hr is determined by a horizontal
oscillator, not shown in the FIGURES, that may be included
in IC 100. Si~lal Hr controls the switching of transistor
Q1 to generate a deflection curxent iy in a deflection
winding ~ af output stage 99. A retrace voltage Vw2 is
produced in a conventional manner across a wlnding W2 of
transformer Tl in each retrace interval of each horiæontal
period H. A second retrace voltage Hin in a winding W3 of
transformer Tl that is coupled to horiæontal proces~or lOOa
is used in synchronizing deflection current iy to a
s~nchronizing signal H9. Signal Hs is generated in a sync
separator, not shown in the FIGURES.
A run supply voltage V-~ is produced by rectifying
voltage Vw2 in a rectifier arrangement 104 that is coupled
to winding W2. DC Voltage V+ is coupled to a corresponding
portion of deflection IC 100, that is referred to herein as
switch mode r~gulator processor lOOb, to pxovide a feedback
signal VIN. Processar lOOb generates a pulse width
modulated signal Sc that controls the duxation, in each
`~ horiæontal interval H, in which switch regulator 102 is
conductive. The duty cycle of signal Sc varies, in
accordance with a difference between the feedback signal,
~ that is proportional to voltage V~, and a reference voltage
~ VNIN that may be produced in a conventional manner. Signal
1309171
6 RCA 84,021A
Sc causes regulated voltage B+ to be at a predetermined DC
voltage level such as, illustratively, +125 volts. Signal
Sc, voltage B+ and voltage V+ are produced, illustratively,
when deflection IC lO0 operates in the power-up mode but
are not produced during television receiver standby mode
operation.
Voltaye V+ is coupled to a voltaye divider 605
that includes series coupled resistors 601, 604 and 602.
Resistor 604 includes a wiper k for developing a voltage
that is representatiYe of, for example, voltage B+. The
voltage at wiper k, that is adjustable by varying the
; position of wiper k, is coupled to an inverting input
:: terminal 608 of an error amplifier 610 via a resistor 607.
An integrating lowpass filter, not shown in
FIGURE 1, is coupled between inYerting input terminal 608
and an output terminal 610a of amplifier 610 to provide the
loop filter of regulator processor lOOb. A filtered exror
voltage V0, developed at terminal 610a, is coupled to a
pulse width modulator lOOb(l~, that produces pulse width
modulated signal Sc. Signal Sc is coupled to a control
terminal 102a of switch regulator 102 to turn on a pass
: switch 102b for a duration, in each period H, that varies
in accordance with the duty cycle of signal Sc. The
duration, during each horizontal period H, in which switch
102b conducts, that is controlled by signal Sc is
determined by the level of error voltage V0 of error
amplifier 610. Thus, the level of each of regulated
voltages B+ and V+ is determined by a reference voltage
VNIN that is produced in a conventional manner, not shown
in the FI~URES.
A standby transformer T0 steps down voltage VAc.
The stepped down voltage is rectified in a rectifier
arrangement 106 to produce a standby voltage VsB. Standby
voltaye VsB is coupled to an energizing voltage receiving
; 35 terminal 120 of deflec~ion IC 100 through a resistor Rl
that char~es a capacitor 66, duriny, for example, the
standby mode operation, to produce in capacitor 66 an
enerqizing voltage Vcc at terminal 120 of deflection IC
: :
1 3 0 q 1 7 l _7_
- RCA 84,02lA
100. Regulated voltage V+ is coupled to terminal 120 via a
diode D2 and resistor 150 to supply voltage Vcc from
voltage V+ when deflection IC 100 operat~s in the power-up
mode but not when the standby mode operation occurs.
standby voltage VsB is coupled to a remote
receiver 107 to pro~ide the operating voltage of remote
receiver 107. Remote receiver 107 is coupled via an MOS
transistor 108 to IC 100. When transistor 108 is
conductive, a low impedance is formed between a junction
terminal 109 of a resistor R734 and ground. The low
im~edance occurs after, for example, a user initiates a
power-on command via an infra-red communication link that
causes a start-up interval to occur, as described later on.
In the power-up mode that follows the start-up
interval, the television receiver is fully operative.
Conversely, after a power-o~ command is initiated by the
user, transistor 10a becomes nonconductive and forms a high
impedance circuit at terminal 109 that causes a standby
mode to occur. In the standby mode the raster scanning on a
display device of the television receiver is turned-off.
A transistor Q705, operating as a constant
current source, has its collector coupled to junction
te~minal 109. As a result of the operation of transistors
Q705 and 108, an on/off signal 110 is developed. Signal 110
is at a high level, or a second state, when transistor 108
is noncoductive, that corresponds to operation in the
standby off~mode, and at a low level, or a first state,
when it is conductive, that corresponds with operation in
the power-up on-mode.
An input supply current ips is coupled through
terminal 120 to deflection IC 100 for providing the
energizing current of deflection IC 100. During operation
in the power-up mode, current ips is supplied mainly by
rectifier arrangement 104 through diodes D2 and D4;
whereas, during operation in the standby mode, curre~t ips
is supplied from standby transformer 106 via rectifier
arrangement 106 and resistor Rl.
::
. ~ .
1 3091 71 -8- RCA 84,021A
Voltage V~c is regulated in deflection IC 100 by
a shunt regulator 131 that may be required to regulate
voltage Vcc during operation in both the standby mode and
the power~up mode. Regulation of voltage Vcc during the
standby mode may be desirable for protecting deflection IC
100 rom an overvoltage condition at terminal 120 that may
occur should voltage Vcc exceed the voltage rating of
deflection IC lO0. If permitted to occur, such overvoltage
condition may damage deflection IC 100. Also regulation of
voltage Vcc during the standby mode may be desirable for
operating circuitry in deflection IC 100 that may be
required to operate during the standby mode such as, for
example, transistor Q705. Shunt regulator 131 regulates
voltage Vcc in accordance with a reference voltage VBG2
that is generated during both the power-up and standby
modes. Voltage VBG2 is generated in, for example, a bandgap
type voltage source 105 that is, there~ore, re~lired to
operate during both the standby and the power-up modes.
Deflection IC 100 includes various circuit
portions that, unlike shunt regulator 131 and bandgap
voltage source 105, need not be energized during operation
in the standby mode. For example, each of horizontal
processor lOOa and regulator processor lOOb need not be
energi~ed during operation in th~ standby mode.
Reducing the level of current ips that is
supplied from standby transformer T0 during the standby
mode and the start-up interval is desirable in order to
relax the specifications of transformer T0 so as to reduce
its cost. Such cost is related to the current requirement
imposed on transformer T0 that is directly related to
current ips. By coupling standby voltage VsB to capacitor
66 via resistor R1, that is relatively large, the current
supplied by transformer T0 is maintained low during both
standby and start~up.
A circuit portion of deflection IC lQ0, that do~s
not have to be energized during the standby mode, may
include a first plurality of transistors. Such arrangement
is depicted by transistors 90a-9On of the P-N-P type. Each
:`
.:
1 309 1 71 9 RCA 84,021A
such transistor may be arranged in a common base
configuration to form at the collector of such transistor a
current source having a high output impedance. Each of
transistors 90a-9On has its base electrode coupled to a
common conductor that is referred to as PNP bus 11. It
should be understood that some of transistors 90a-9On may
be included in, for example, horizontal driver lOOa and
some others in regulator processor lOOb.
Transistor 90f, for example, illustrates one
typical example of a circuit stage that is formed by a
corresponding one of transistors 90a-9On. ~n such stage, a
collector current i90f is coupled to circuitry that is
- symbolically referred to as load circuit 90fl. A second
typical example is shown in the arrangement of amplifier
610 that is included in regulator processor lOOb.
Amplifier 610 of FIG~RE 1 forms a differential a~plifier in
which transistor 90n provides a current i90n that is
coupled to the emitters of transistors 90n2 and 90n3 of
di$ferential amplifier 610. Output voltage VO of FIGURES 1
and 2 is developed at the collector of transistor 90n3 of
FIGURE 1.
; The collector current in each of transistors
90a~90n is controlled by a voltage VBR that is coupled, via
PNP bus 11, to the corresponding base electrode o each of
transistor~ 90a-90n and that is generated by a temperature
compensated current control arrangement 300. The emitter
electrodes of the above-mentioned transistors 90a-90n are
coupled through corresponding resistors to supply voltage
Vcc that is, as described before, a fixed DC voltage.
Because of such arrangement, the collector currents in each
of transistors 90a-9On track each other over a wide range
of temperature to form a current mirror arrangement.
Current control arrangement 300 controls voltage VBR in
such a way that the collector current in each of
transistors 90a-9On stays substantially constant when the
temperature changes.
Current control arrangement 300 includes
transistors 90a, 90b, 73, 76, 77 and 80. The collector of
, ~
1 3 09 1 7 1 lo RCA 84,021A
transistor 73 is grounded. The collector of transistor 90a
is coupled to the base of transistor 73 and, at a terminal
300c, to the collectors of transiskors 76 and 77. The
emitter of transistor 77 is coupled to a terminal 300a via
a resistor R61. The emitt~r of transistor 76 is coupled to
the base of transistor 77, to the base of transistor 80
and, via a resistor R60, to terminal 300a. Transistor 80
i5 arranged in a common emitter configuration. The base of
transistor 76 is coupled, at a terminal 300b, to the
collectors of bo~h transistox 80 and 90b. The emitter of
transistor 80 is coupled to terminal 300a. Transistors 76,
77 and 80 form a temperature compensating feedback network
that controls via transistor 73 voltage VBR and maintains
constant currents i90a and i90b in respective transistor
90a and 90b.
Transistor 76 forms, with transistor 80, a
feedback arrangement that causes a collector current i90b
of transistor 90b to flow also as a collector current in
tran~iskor 80, by developing the corresponding base-emitter
voltage in transistor ~0 and across re~istor R60. As
described lat~r on, current i90b is maintained constant
over a wide range of temperatures.
When the temperature is constant, this feedback
action tends to maintain a substantially constant current
flow through resistor R60 and thus a corresponding constant
currerlt through the collector-emitter junctions of each of
transistors 76 and 80. As the temperature varies, the
base-emitter ~orward voltage of txansistor 80 also varies.
In order to compensate for the variation of the
base-emitter forward voltage of transistor 8a SO as to
insure corresponding constan~ cuxrents through each of
terminals 300c and 300a, transistor 77 is coupled with its
base to sensing rPsistor R60. The current i~ resistor R60
is proportio~al to the volta~e across the base-emitter
junction of transistor 80 ~ha~ varies inversely wi~h
temperature. Whereas, for a given voltage across resistor
R60, the voltage across resistor R61 that determines the
collector current in transistor 77 varies directly with the
1 30q 1 7 1
~ RCA 84,021A
temperature. Thus, variations of the base-emitter forward
voltages of transistors 77 and 80 have opposite effects on
the sum of the currents in resistors R60 and R61 that
causes, via a feedback arrangement, a collector current
i90a in transistor 90a to be substantially constant when
the temperature varies.
An example of an arrangement that provides
temperature compensation similar to current control
arrangement 300 is described in detail in U.S. Patent No.
3,886,435, in the name of S. A. Steckler, entitled VBE
VOLTAGE SOURCE TEMPERATURE COMPENSATION NETWO~K.
By selecting a predetenmined ratio between
resistors R60 and R61, collector current i90a flowing
through tenminal 300c, that is approximately e~ual to the
sum of the currents in the collectors of transistors 76 and
77 or in resistors R60 and R61, is maintained constant
throughout a wide range of opexating temperatures. Because
of the feedback arrangement of transistor 73, voltage VBR
causes the corresponding collector current in each of the
other ones of transistors 90a-9On to be also temperature
independent.
Terminal 300a i5 coupled to an I L injector line
12 that provides a temperature compensated injection
current that is equal to the sum of currents i90a and i90b
; 25 to a portion of deflection IC 100 that utiliz~s the well
known I L t~chnology. Transistors 290a-290j, that are
coupled to line 12, represent the injector transistors of
such portion of deflection I~ 100.
Another example of an arrangement that is similar
to that of transistors 90a-9On is depicted by transistors
l90a~190m of the N-P-N t~pe that may be utilized in various
stages of deflection IC 100. Æach of transistors l90a~190m
has its base electrode coupled to a common conductor, or
rail line, that is referred to as NPN bus 10 and has its
e~itter electrode coupled via a corresponding resistor to
ground.
Voltage Vcc at tenminal 120 is coupled to the
collector of a transistor 81 which has its base coupled to
.
~ '
, ~
1 30q 1 7 1
-12- RCA 84,021A
the collector of transistor 90i. The emitter of transistor
81 is coupled to the base of a transistor 82 which is
coupled back via its collector to the collector of
transistor 90i. Transistors 81 and 82 produce a temperature
S compensated voltage VB~l on bus 10 that performs a function
analogous to voltage VBR of bus 11 and that is controlled
by voltage VBR. Thus, voltage VBR1 enables the collector
currents in transistors 190a-1sOm to flow only when voltage
VBR enables the flow of the collector currents in
txansistors 90a-9Qn. '~ransistors 81 and 82 that are coupled
to transistor 90i cause the collector current in each of
transistors l90a-19Om to be the current mirror of the
collector current in transistor 90i that is controlled by
voltage VBR, and therefore, temperature independent.
Each of horizontal processor lOOa and regulator
processor lOOb of FIGURE 1 that produce signals ~r and Sc,
respectively, may include transistors from each of the
groups 90a-9On, l90a-19Om and 290a~290j. Thus, voltage VBR
controls the operation of processor lOOa and of regulator
processor lOOb. An examplë'of a manner by which, during
normal operation, ~ransistors such as transistors 90a-9On
and l90a-190m of FIGURE 1 may be used for generating
control si~nals such as, for example, signals Sc and Hr is
depicted in a data sheet ~or linear integrated circuits
CA3210E and CA3223E of the RCA Corporation, published May,
1982, and entitled TV Horizontal/Vertical Countdown Diqital
Sync System.
When the coll~ctor currents in each of
transistors 90a~90n of FIGURE 1 is zero, signal Sc, for
example, is in an inactive state. The result is that,
during the standby mode, a pass switch 102b of regulator
102 remains nonconductive; conseguently, voltage B~ is not
generated and horizontal output stage 99 remains
unenergized.
In carrying out an aspect of the invention,
on/off signal 110 is coupled via an arrangement, operating
as a ~ic~nal inverter, that includes transistors Q700, Q701
and Q703, to a junction terminal 200a of an on/off
1 30~ 1 7 1 -13- RCA 84,021A
switching arrangement 200. During operation in -the
power-up mode, a second on/off control signal V200a that is
developed at junction terminal 200a is at a high level as a
result of signal 110 being at the low level; conversely,
during operation in the standby mode signal V200a is at a
low level.
On/off switching arrangement 200 includes a zener
diode 83 that has its cathode coupled to voltage Vcc and
its anode coupled via a resistor R202 to junction terminal
200a that is coupled to the bases of two switching
transistors 84 and 85. Junction terminal 200a is coupled
via a resistor 86 to ground.
- The emitter of switching transistor 84, that is
conductive only during a short interval following a user
initiated power-up command, referred to herein as the
start-up interval, is coupled to bus 10 at a junction
between the base o~ transi~tor 82 and the emittex of
transistor 81. The collector of transistor 84 is coupled
back to both collectors of transistors 76 and 77 of current
control arrangement 300 at terminal 300c.
The collector of switching transistor 85 is
coupled to the bases of transistors 87 and 90 and to
voltage Vcc via a resistor ~8 to turn-on transistors 87 and
90 wh~n switching transistor 85 is nonconductive. The-
collec~or of transistor 87 is coupled back at terminal 300b
to the base o transistor 76, to the collector of
transistor 80 and to the collector of transistor 90b.
During the standby mode, control signal V200a,
that is at the low level as a result of signal 110 being at
the high level, causes transistor 87 to be in saturation.
Consequently, a collector current i90b of transistor 90b
that flows into terminal 300b is shunted away from
transistor 80 by transistor 87 that is conductive.
Therefore, the collector current in each of transi tors 76,
77 and 80 is forced to be zero. It follows that when
on/off control signal 110 is at the high level, as a result
of the user initiated power-olf command, no base current
'
:
1309171
-14- RCA 84,021A
flows in transistor 73 of arrangement 3GO. The emitter
curr~nt in transistor 73 is, therefore, also zero.
Voltage VBR is, during normal operation power-up
mode, a temperature compensated voltage that causes the
corresponding collector curren-ts in transistors 90a-9On to
be temperature compensated, as described before.
Thus, in accordance with an aspect of the
i~vention, in the standby mode, voltage VBR causes the base
current and, hence, the emitter current, in each of
transistDrs 90a-9On, to be æero. Thus, temperature
~ compensated arrangement 3dO that generates temperature
compensated voltage VBR couples on/off signal 110 to bus 11
to turn off transistors 90a-9On. Because the collector
current in transistor 90i is zero, the emitter current in
each of transistors 190a~190m is also zero. Also, because
the emitter current in each o transistors 76, 77 and 80 is
zero, I2L injector transistors 290a-290j become also
nonconductive. The result is that control signal Sc remains
at an inactive state that prevents conduction of switch
102b so as to prevent the generation of voltage B+. It
follows ~lat during the standby mode, supply current ips
that flows in deflection IC 100 and ~hat is proportional to
the sum of the emitter currents in transistors 90a-90n, for
example, is reduced relative to its value during the
power-up mode. The result is t~lat current loading of
standby transformer TO is, advantageously, reduced during
the standby mode.
As described before, when a user initiates the
power up mode, transistor 108, that is coupled to remote
receiver 107, become conductive that causes signal 110 to
be at th~ low level . When transistor Q703 becomes
nonconductive, due to signal 110 being at the low level,
conductive zener diode 83 generates signal V200a. Zener
diode 83 is conductive as long as voltage Vcc exceeds a
predetermined minim~m, or threshold, first level. Zener
diode 83 prevents ini~iation of the start-up operation if
capacitor 66 is not fully charged above the first level.
On/off control signal V200~ at terminal 200a that is pulled
.' . ' '
, ~
130ql71
-15- RCA 84,021A
up to a sufficiently high level by conductive zener 83
causes transistors 85 and 84 to become turned-on. With
transistor 85 conducting, transistors 87 and 90 are turned
off.
During the start-up interval and immediately
after signal V200a causes transistors 84 and 85 to turn on,
transistor 84 draws current from the ~ase of transistor 73,
which begins to conduct simultaneously with transistor 84.
Transistor 85 shun~s the base currents of transistors 87
and 90, causing ~hem to turn off. The conduction of
transistor 73 causes transistors 90a, 90b and 90i to
conduct the corresponding collector currents. Transistor
~7 ~eing turned off, allows the conduction of transistor
90b to turn on the eedback network comprising transistors
76, 77 and 80. Conduction of transistor 90i turns on
transistors 81 and 82 that cause voltage VBRl at the
emitter of transistor 84 to increase. The increase in
voltage VBRl causes transistor 84 to become nonconductive.
Transistor 73 base current is now supplied by conduction of
trans.istors 76 and 77. In this way, current control
arrangement 300 enables the emitter currents in each of
transi~tors 90a-90n and l90a-19Om to flow; thereby,
deflec~ion IC 100 that may include a horizontal oscillatox,
not shown in the FIGURES, becomes fully operation l. The
result is that signals Hr and Sc are generated and
deflection switch.ing transistor Ql is switched on and off
at ~le deflection rate fH, that initiates the generation of
voltage V+. As described before, voltage Vcc of deflection
IC lOO is obtained during the power-up mode from voltage
Y+-
FIGURES 2a and ~b illustrate schematicallywaveforms useful for explaining the operation of deflection
IC 100 of FIGURE 1 during the start-up interval. Similar
n~unbers and symbols in FIGURES 1, 2a and 2b depict similar
it~ms or functions.
During portion to-tl of the start-up inter~al of
FIGURES 2a and 2b, that immediately follow~ the user
initiated power-up comnand, IC 100 of FIGURE 1 is powered
..
,
1 3~9 1 7 1
-16- RCA 84,021A
primaril~ from the charge already stored in capacitor 66.
Because of the loading caused by, for example, transistors
90a-9On, capacitor 66 may discharge prior to voltage V+
attainin~ its normal operational level. The result is that
voltage Vcc of FIGURE 2b may be reduced at, for example,
time t1 to a level so low that voltage Vcc is insu~ficient
to sustain operation in the power-up mode. The discharge
of capacitor 66 of FIGURE 1 may occur since deflection IC
100 may draw more current than can be provided by standby
voltage VsB via resistor Rl, that is relati~ely larye
valued. Resistor Rl is designed to be a large resistor so
as to reduce loading of transformer TO during the standby
mode and start-up interval.
Should capacitor 66 be discharged during the
lS start-up interval by, for example, current ips, zener diode
83 will turn off when capacitor 66 voltage falls below the
breakdown zener voltaye of diode 83. Transistor 85
remains, however, conductive, due to a supply of current
~hrough resistors 91 and 92. Deflection IC 100 will
continue to operate to gen~rate signals Hr an~ Sc until,
for example, time tl of FIGURE ~b when voltage Vcc in
capaci~or 66 o FIGURE 1 ~alls below a second predetermined
level VL2 of FIGURE 2b. The second predetermined level VL2
is a lower holdin~ level of, for example, 4 volts, which is
sufficiellt to supply enough current through resistors 91
and 92 of FIGURE 1 to maintain conduction of transistor 85.
Below the lower holding level that occurs at time tl of
FIGURE 2b, transistor 85 of FIGURE 1 turns o~f. Whe~
transistor 85 turns of, however, transistors 87 and 90
will again saturate, thus turning off transistor 76 which
will cause the emitter currents in tran~istors 90a 90n and
l90a-19Om to become zero, 50 as to terminate the start-up
operation after time tl of FIGURE ~b. With transistors 87
and 90 of FIGURE 1 again satura~ed, supply current ips from
capacitor 66 will be reduced and the previously described
start-up process will b2 repeated.
Capacitor 66 may, therefore, be recharged as many
times as are necessary until power-up operation is --
1 3 Oq 1 7 1 -17- RCA 84,021A
obtained, to cause voltage V+ to be operative so as to
supply voltage Vcc. Thus, during such portions of the
start-up interval, such as, for example, during interval
tl-t2 of FIGURE 2b, deflection IC lOO of FIGURE 1 is
essentially in an off condition with the load current
sources disabled until capacitor ~6 recharges ko the first
predetermined voltage such as level VLl that occurs at time
t2 of FIGURE 2b.
During intexval t2-t3, a second start-up attempt
occurs that is similar to that occurring during interval
to t~. In the example shown, at time t3 voltage V+ of
FIGURE 1 becomes suf~iciently large so as to begin charging
- capacitor 66 via diode D2. During interval t3-t4 of FI~URE
2b, capacitor 66 of FIGURE 1 is charged up to a level that
is controlled by shunt regulator 131 that occurs at time t4
of FIGURE 2b. Henceforth, start up operation ceases and
normal operation in a power-up mode begins. It should be
understood that a successful start~up attempt that is not
terminat~d may occur immediately after time to of FIGURE 2b
when, for example, the amplitude of voltage VAc is
suf~iciently high.
During the power-up mode that immediately follows
the star~-up interval, signal 110 is maintained at the low
level, thereby maintaining signal V200a at a hiyh level~
~ransi~tors 87 and 84 are maintained nonconducti~e, and
transistors 73, 76, 77 and 80 conductive. Consequently,
normal operation emitter currents in transistors 90a-9On
and l90a~190m, that are controlled by voltage VBR, and
normal operation level of supply current ips are
maintained.
Thus, in accordance with a feature of the
invention, voltage VB~ on PNP bus 11 that is temperature
compen~ated duriny the power-up mode, operates as a
switchin~ signal, during the s~andby mode. In this way the
emitter cuxrents in transistors 90a-90n are,
advantageously, switched off, during the standby mode.
