Note : Les descriptions sont présentées dans la langue officielle dans laquelle elles ont été soumises.
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OUT-o~ P BLOCRIN ~NI$
BACR¢ROUND OF T~ I~V~NTION
The present invention relates to relay systems
for use in protecting ~c power distribution ~ystems and
more particularly to out-of-step blocking units for
preventing circuit breaker operation as a result of load
swings.
B~ F DE~3ClRIPTION OF ~I15 O~WI~G~:
Figure 1 is an R-X diagram depicting
characteristics of overreaching and ~irst zone relays in a
protective relaying system for AC power transmission
lines.
Figure 2 is a R-X diagram depicting
characteristics o~ out-of-step blocking, overreaching and
~irst ~one relays in a protecti.ve relaying system for an
AC power transmission line.
Figure 3 is a one line, block diagram of a
current and voltage processing portion of the preferred
embodiment of the out-o~-step blocking unit of the present
invention.
Figure 4 is a block diagram of a reach adjustment
and polar1zing portion of the preferred em~odiment of ~he
out-of-step blocking unit of the present invention.
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Figure 5 is a block diagram of an out-of-step
blocking circuit in accordance with a preferred embodiment
of the present invention.
Sometimes, as a result of anomalous operation of
the power system, for example when the system is not
operating in synchronization, the impedance
characteristics will change andt in some cases, change to
the extent that the protective relay system treats such a
change as a fault condition thereby generating a trip
signal to the circuit breaker protecting the line. Since
it may be undesirable to trip the circuit breakers under
these conditions, out-of-step blocking units have been
incorporated into protective relay systems to provide a
blocking signal which prevents circuit breaker tripping as
a result of load swings.
Load swing conditions can be visualized by
referring to the R-X diagram shown in Figure 1. The path of
the impedance point Z caused by a load swing ls represented
by the line lo. As can be seen, the path of the impedance
point enters the characteristic of an overreaching relay,
represented by:circle 12, as well a the characteristic of a
first æone relay, represented by the circle 14. As is known
in the art of protective relaying, once the load impedance
comes within the characteristic of a protective relay,
the relay will yenerate a trip signal. For the condition
depicted in Figure 1, the overreaching relay will
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generate a trip ~ignal o~ce t~e load point co~es wit~in its
characteri5tic 12; and t~e first zone relay will gener~te a trip
signal once the loa~ poin~ enters its charact~ristiC 14.
As indicated above, it is undesirable that the circuit
breakers trip on an impedence change caused by a load ~wing.
Consequently, it is de~irable to be able to discriminate between a
load swing and a fault condition. ~hi~ has been accompli~hed by
addinq an out-of-s~ep blocking unit, which is essentially an
overreaching relay, to the ~ystem. ~ferring to Figure 2, there
is shown a R-X diagram on whic~ is depic~ed the ch~racteristic of
the out-of-step blocking unit, represented by circle 16, as well
as t~e characteristics of the overre~ching relay, represented by
the circle 12 and the first zone relay, r~presented by the circle
14.
It has been found that a change in i~p~dence due t~ a
swing causes t~e impedence to cha~ge at a rate ~hich is slower
than that which occ~rs as the result of a fault. As a result,
load swings, for which tripping is not desired, are detected by
~easuring the time fro~ whîch t~e impedence enters t~e
characteristic of the out-o~-step blocking relay, circle lÇ in
Figure 2, and the time the impedence comes within the
characteristic of the overreaching relay, circle 12 in Figure ~,
or the first zone relay, circle 14 in Figure 2~ If t~is time
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difference exceeds a predetermined li~it, t~e system treats the
change in impPdence ~s a load swing ~nd therefore causes the
out of-step blockiny unit to generate a blocking 6ignal thereby
preventing thP tripping of the circuit breakers.
One problem with pri~r out-o~ ep blockins units is that
they can generate bloc~ing signalr- under cer~ain fault co~ditions
in which tripping ~hould be allowed ~o occur. For instance, a
high resis~ance ground ~aul~ may cause the i~pedance ~een by a
relay at one end of the protec~ed line to fall between the
trippling charac~eristic and the out-of-s~ep blocking
characteristic, t~us ~using the out-of-step circuit to block
tripping~ ~hîs adversely a~fects the reliability of the system by
preventing the operation of the circuit ~reakers when ~hey should
be tripped to isalate a fault.
Another problem experienced in the past ~as been a lack
of coordination betw~en ~he out-of-s~ep blocking unit and the
tripping units on internal faults. Ill ~ome instances, the
blocking unit will operate prematurely with respect to t~e
tripping units once again causing circuit breaker operation to be
erroneously blocked.
Accordingly, it is an object of the present invention to
provide a protective rel~y system ~or protecting AC power
transmission lines incorpora~ing an out-o~-step blocking unitr
which syst~m ha~ enhanced reliability.
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It is another object o~ the present invention to providea protective relay sy~te~ for an ~C pow~r ~ransmission line in
which the coordination of the oUt-0~-5tep blocking unit and the
tripping units is enhanced.
It is ~till another object of th~ present invention to
provide a protectiYe relay sy~tem for an AC po~er transmi~sion
line ln which coordination be~we~n blocking units and tripping
units is enhanced by preve~ing o~ ~ubstantially delaying the
operation of t~e ou~-of~step blocking unit on internal faults. --
These and other objects of the present invention will
beGome apparent to those skilled in the art upon consideration of
the following description of the inYention.
SUMMARY _F~T~E INVENTIO~
The present inventio~ comprises an ou~-of-step blocking
unit for use in a protective relaying gystem for an AC power
trans~ission line in wh c~ addi~ion of restraining signals are
utilized to ensure coordination of the. out-o~-step ~ocking unit .
and tripping units of the p~o~ective relay system up~m occurrence
of internal faults. The added restraint signals are preferablY
t~e negative sequence and ze~o sequen~e comp~nents of the current
as well as a ~ (IZ~V) quan~ity w~ich is the difference in the
(IZ-V) quanti~y between the post fault and pre-~ault values; in
other words, ~ ~IZ-V) is in ef~ect tha change in the (IZ-V)
quantity due to the fault.
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The addition of these restraint signals
simplifies the application since the timer in the
out-of-step blocking logic, which in the past has
been the only setting which discriminates between a
swing and a ~ault, may now be set without a riyorous
determination of the impedance-time characteristic of
the swing locus while assuring that the fastest swing
will be detected. Except for series compensated line
applications, the setting can be determined knowing
only the impedance of the protected line section.
Absolute values of equivalent source impedance or
sourcejline impedance ratios, the knowledge of which
was necessary in the past, are no longer required.
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DETAILED D~CRIPTION OF T~B PREFERRED BMBODIM~NT
Referring to Figure 3, there is shown a one-line,
block diagram of a preferred embodiment of the current and
voltage processing portion of the out-of-step blocking
units of the present invention. A three phase alternating
current electric power transmission line, generally
designated 10, has an A phase (A), a B phase (B), a c
phase (C) and ground (G). Each oP the three phases have
associated with it means 20 for sensing current in that
particular phase as well as means 32 for sensing voltage
on that phase. As is well known to those skilled in the
protective relaying and power transmission art, cuxrent
sensing means 20 may be a current transformer and voltage
sensing means 32 may be a step down potential transformer.
As shown in Figure 1, a current sensing means is
associated with each phase; means 2Oa being associated
with phase a, means 20b b~ing associated with phase B and
means 20c being associated with phase C. Likewise, there
is a separate vo1tage sensing means 32a associated with
phase a, means 32b associated with phase B and means 32c
associated with phase C. However, it is to be understood
that although a specific type of current and voltage
sensing scheme i5 depicted in Figure 1, other schemes
known in the art may be substituted for that depicted; the
purpose being to obtain signals which axe xelated to each
phasa voltage and each phase current.
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The output fro~ the current 6ensing means 20a is coupled
to a first transactor 21a; the outpu~ from the current ~ensing
means 20b is coupled t~ a ~econd transac~or 21b; and the output
from the current sensing means 20c is coupled to a third
transactor 21c. ~s is known in the ~r~, the ~econdary voltage
output of a transactor i~ related to the input current by a
complex proporti~nality c~ns~ant or a vector operator known as the
transfer impedence of the transactor. For transactors 21a, 21b
and 21c shown in Figure 3, the transfer impedence of each is
selected to be egual to a fixed transfer ratio and a fixed angle,
~or example ~5. Consequently, the output of ~ransactor 21a is
a signal IAT which ~as, for exa~ple, a fixed 85 phase shift
with respect to the input IA~ The output signals IBT and
ICT from transactors 21b and 21c respectively, are similarly
related to their respective inputs IB and Ic. Further
detailed de~criptions of transactors may be had by reference to
U.S. Patent N~. 3,374,399, i~sued to Dewey which patent is
assigned to the assignee of the present invention.
The output of transact~rs 21a, 21~ and 21c are coupled to
the inputs of a first positive sequence network 22, a second
positive sequence networ~ 24, a negative sequence network 26, and
a first three-input summing amplifier 28. The summing amplifier
28 produces an output signal having a magnitude which is equal to
the sum of the magnitude of t~e signals applied t~ the inputs,
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multiplied by a predetermined gain which, in the preferred
embodiment, is -1/3. Consequently, the output of the ~umming
amplifier 16 is egual ~o MIo w~ere Io is the zero sequence
componen~ of the phase curren~ in the ~ransmission line; and M
indicates, in t~e convention uged in this detailed description,
that the ~ignal is lnver~ed. The output of the irst thr~e-input
~umming amplifier 28 is coupled to the input of a phase ~hift
network 30. The output o~ the phase shift network 30 is the input
signal which has been ~hifted in phase by a predetermined amount
which, in the preferred embodiment, is 25 lagging.
Consequently, the output of ~he phase ~hift network 30 is the
~ignal MIoF where F, in the co~vention used herein, indicatas
that the ~ignal has been phase ~hifted.
The output of voltage sensin~ means 32a is couplad to the
primary of a first transformer 33a; the output of the voltage
~ensing means 32b is coupled to the pximary of a second
transformer 33b; and the output of the voltage sensing means 32c
is coupled to the primary of a third transformer 33c. The signals
from the secondaries of the transformers 33a, 33b and 33c are
coupled to the inputs of a third positive sequence network 34. It
is well understood to those skilled in the art of electrical power
transmission protective relaying that phase currents in a
three-phase alternating current circuit can be resolved into three
sets of symmetrical, balanced voltage and current vectors known as
positive sequence, negative sequence and zero sequence components.
It is also well known that certain circuits called "symmetrical
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component networks" can be ~onnected to a three-phase electrical
power system to provide an output signal ~hat is proportional to
the magnitude of the selected one of the three saguence components
of voltage or current. The negative 2~ and postiYe 22, 24 and 34,
6eguence networks are ~uch networks. Sequence networks nf this
type are disclosed in U.SO Patent No. 4,342,062. Further d tailed
descripti~ns ~f symmetrical c~mponent networks can be had ~y
reference to U.SO Patent No. 3,992,651 issued to Hodges: and
4,034,269 issued to Wilkinson, bot~ of which pat~nts, as well as
U.S. Patent No. 4,342,062, are as~igned to the assignee herein.
The output of the first po~itive ~equence network 22 is a
signal, 3I~l, representative of three times the positive
sequence component I~l of the current flowing in A phase of the
transmission line. The ou~pu~ o~ the second posi~ive sequence
networ~ 24 is a sign~l, IAl, representative of the positive
sequence component of the current flowing in the A phase of the
transmis~ion line. The output of the negative ~equen~e network 26
is a signal, IA2, representative of the negative sequence
component o~ the curren~ flowing in tha A phase o~network 34 is a
signal, VAl, representative of the positive ~equence component
of the voltage in the A phase of the transmission line.
The output signal 3IA1 from the firs~ positive sequence
network 22 is coupled to a ~irst AC couple circuit 36 which has a
gain of approximately 1 for non-DC signals and zero for the DC
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component. T~e ~utpu~ of ~ C couple circuit 36, which is the
same as the input signal except tha~ the DC co~ponent has been
removed, is coupled to the input of a fir~t level detector 38.
The outpu~ of the ~ir~t level detector 38 is a signal, IlSA
which is generated when the magnitude o ~he input signal exceeds
a predetermined ~alue. I~ the preferred embodL~ent, the
predetermined value is 0.05 per unit of rated current~
The output signal IA1 from the second positive ~equence
network 24 is coupled to the input of a positi~e sequenc~ angle
adjust circuit 40. The output of the positive ~equence angle
adjust circuit 40 is a signal IAlS, which is equal to the input
signal, IAl, ha~ing a preselected angle. In ~he preferred
e~bodiment, the preselected angle is in the range of ~rom
approximately 70 to 85. The S in tlle expression IAlS
indicates that, in the convention used herein, t~e positive
sequence component of the phase A current has been adjusted to a
predetermined angle. This phase shiet is used ~o adjust the angle
of the positive sequence replica impledance to ~atch the angle of
the protected line.
The output signal, IA2, from the negative sequence
network 22 is coupled to t~e input of a negati~e sequence angle
adjust circuit 42. The output of t~e negative sequence angle
adjust circuit 42 is a signal, IA2S, which is equal to ~he input
signal, IA2, having a preselected angle. In the preferred
e~bodiment, the preselected angle is the range of from
approximately 70 to 8S. T~is phase shift is used to adjust
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the angle of ~he negative 6equence replica i~pedance to match the
angle of the protected line.
Referring now to Figure 4, t~ere is shown a preferred
embodiment of ~he rearh adjustment and polari2ing portion of the
out~of ~tep blocking uni~ of the pre~ent invention. The positive
6equence component of the phase A voltage (VA~)1 which has been
obtained i~ accordance with the descripti~n ~et forth with respect
to Figure 3, ic coupled to a no~-inverting input o~ a first
two-input ~ummin~ a~pl~ier 50, one input of a ~econd two-input
summing amplifier S2 and t~e input of a first ~bs~lute value
circuit 54. In the preferred em~odiment, the first 50 and second
52 two-input su~ming amplifier~ each comprise an operational
a~plifier which generates an output signal having a ~agnitude
which is equal o the algebraic sum of the magnitudes of t~e
signals applied to t~e inver~ing and non-inverting inputs. The
absolute value circuit 54 i~ preferrably a full wave precision
rectifier of the type shown and described on pages 206 and 207 of
the publication ~ntitled "IC Op-Amp Cookbookn, Second Edition,
W.G. Jung, Howard Sa~s & Co., IncO,
The output vf the first absolute value circuit 54, which
is a signal having a magnitude which is substan~ially equal to the
absolute value of the magnitude o~ the input signal, is coupled to
the input of a first gain srlect circuit 5~. The output of the
first gain selPct circuit 56 is a signal, the ~agnitude of which
is a function of gains which are selectable b~ nhighn or ~low"
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signals ~pplled t~ a gain 6elect lnput. In the preferred
embodiment~ the ~ain i~ ~il;her one, ~;elec:table by application Gf a
"high" sig~al to the gain ~ela~t input: or, a galn of 0. 4,
~electable by application of a ~low~ ~ignal, Conse~ently, the
magnitude of t~e output ~ignal is either equal to the ~agnitude of
the input ~;ignal or is equal ~o O . ~ times the maqnitude of the
input signal depending upon the state o~ t~e signal applied to the
gain select control lnput.
The IAlS ~ignal, which was generated in accordance with
the description set forth with respect to Figure 3, is coupled to
the input of a first positive sequence reach adjust circuit 58 and
a ~econd positive reach adjust circuit 60. ~he fir~t 58 and
second 60 posi~iVe ~equence reach adjus~ cir~uits are adjustable
gain op amp circuits. The output of the first positi~e sequence
reach adjust circuit 5B, which has a ~agnitude set to be
representative of the reach of the protective relay systems, is
coupled ~o the input of a second AC couple cir~uit 6~. The output
of the second positive reach adjust circuit 60 is coupled to the
input of a third AC couple circuit 640 In the pr~ferred
embodiment, the second 62 and third ~4 AC couple circuits are the
same type as the previously described first AC couple circuit 36.
The output of the second AC couple circuit, which is the
same as the input signal except that any ~C componen~ has been
removed is coupled to the input of a second a~solute value circuit
66 and the other input of the second two-input summing amp~ifier
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52. The output of the 6econd absolu~e value cirouit 66, which is
a signal having a magnitude equal ~o ~he absolute value of the
magnitude of the input signal f is coupled to a second gain select
circuit S8. In the pre~erred e~bodi~ent, the second ~elect
circuit 68 is the same type a~ the previously described first qain
~elect circui~ 56. In the preferred em~odiment, th~ 6econd gain
select circuit 68 al~o has a ~electable gain of one when a "high"
signal is applied to the gain ~elect input and a gain of 0~4 when
a "low" signal is applied to the gain select input.
The output of the ~econd gain ~elect circuit 6B is a
signal which is coupled ~o th~ input of a first electronic switch
70 and a second ele~tronic ~witch 72. The preferred embodiment,
the electronic switches 70 ~nd 72 are each controlled by a signal
applied to a control input. ~pplication of a control signal to
the control input will operate ~he switch thereby connecting the
signal applied to the input o~ ~e switch directly to its output.
With rèspect to the first electronic switch 70, a "hiqh" signal
applied to the control input will connect the signal a~ the input
of the switch t~ its output. ~ith respect to ~e second
electronic switch 72~ a "low" signal applied to ~he con~rol input
will cause the signal appearing at the switch input to ~e
connected to the switch output.
The output of the first electronic switch 70 is coupled
to the input of a first inverter 7~. The first inverter 74 is
preferably an operational amplifier having an inverting input and
which generates an output signal which is substantially equal to
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the inverted input ~ignal. Consequently the output of the fir~t
inverter 74 is a ~ignal MIZT which i~ the inverse o~ the output of
the second gain select circuit 68 which is sPlectively coupled to
the input of the first inverter ~4 through the second electronic
~witch 70. The output of t~e ~econd electronic ~witch 72 i~ the
IZT signal.
The output of the ~econd AC couple circuit 64 is coupled
to the input of a 6econd inverter 76. The second inverter 76 is
preferably the ~ame type as tbe previously described first
inverter 74, having an inverting input and generating an output
signal which is ~ubs~antially equal to the in~rted input ~ignal.
The output of the second in~erter 76 is coupled to t~e input of a
forward offset circuit 78 and one input of a t~o-input coincid~nce
logic circuit ~0. I~ the preferred embodiment, the forward offset
circuit 70 is a variable gain op amp circuit with a gain
adjustable between 0.0 and O.4 ti~es the forward reach. The
output of the forward offset circuit: 78, w~ich is proportional to
the desired forward offset, is coupled to the input of a clip
circuit 82.
In the preferred embodiment, the clip circuit 82
comprises a zero suppression circuit which passes that portion of
the input signal which is greater than a pre-set level, and a
differential amplifier which s~btracts the output of t~e zero
suppression network from the input signal. Consequently, the
clipping network 52 passes only that portion of the input signal
that is less than the pre-set level. In thP preferred embodiment,
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the clip circuit ~2 i~ o~ the type 6hown an~ descri~d under theheading nBoUNDSn of a publication en~itled ~Nonli~ear Circuits
Handbook~, edited by Daniel H. Sheingold, pu~lished 1974 by ~nalog
Devices Inc., Norword, ~assjQ The output of the clip circuit 82,
which is that portion of the input signal whose ~lagnitude
is less than the pre-set level, is coupled to an inverting
input of the first two-input summing amplifi~r 50.
The output of t~e first two-input sum~ing ~mplifisr 50,
which as previously s~ated is a si~nal whose magni~ude is t~e
algebraic sum of t~e magnitudes o~ the signals at the inverting
and non-inverting inputs, is coupled ~o the inpu~ of a first band
pass filter 84. In the preferred embodiment, the first band pass
~ilter 84 is a multiple feeback band pass filter with ~ center
frequency selected egual to the rated fr~quen~ of the power
system, which is typically 50~z or 60~z. The first band pass
filter 84 preferably has a Q approximately equ~l to 3.8 and a gain
of -1. The output of the first band pass filter ~4 is coupled to
the input o~ a third absolute value circuit ~6 and the second
input of the tw~-input coincidence logic circuit 80. In khe
preferred embo~imenty the third absolute value circuit 86 is the
same type as the previously described first absolute value circuit
54.
The output of the third absolute value circuit 86, which
is a signal whose magnitude is t~e absolute value of the magnitude
of the input signal, is coupled to t~e input of a second level
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detector 88. ~he 6econd level de~eckor 88 is the same type as the
previously described first level detector 38. The output o~ the
second level detector 88, which is a signal generat~d when the
input exceeds a predetermined level (O.35 per unit in the
preferred e~bodiment~, is coupled to t~e gain control inputs of
the first 56 and second 68 ~ain ~elect circuits. With no output
frsm the ~Pcond level detec~or 8~, the magnitudes of the output
~ignals from the first and ~econd gain select networks will be
egual to the magnitudes of their respective input signals
~ultiplied by the low gain.
The output (IZ-V) of the ~econd tw~-input su~ming
amplifier 52 is applied to ths input of a second band pass filter
90 a~d t~e non-inverting input of a ~hird two-input ~umming
amplifier 92. ~n the preferred em~odiment, the second band pass
filter 9~ i5 a multiple feedback ban~ pass filter with a center
~requency selected equal to the rated frequency of the power
system, which is typically 50Hz or 60Hz. The second b~nd pass
filter 90 preferably has a Q approxi~ately equal ~o 3.8 and a gain
of one. Wit~ a Q of 3.8, a c~ange in t~e input ~ignal from the
band pass filter 90 lags the corresponding chage ~o the input
thereby providing a short term ~emory of the pre-change signal.
Although a higher Q would provide a longer time constant and a
longer term memory, it would create greater phase variation upon
occurrence of a change in frequency, which could cause generation
of a signal from the third ~wo-input summing amplifier 92 to which
the output of the second band pass filter 90 is coupled. Such a
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signal could create er~oneous operation of the out-of-step
bloc~ing unit 6ince it could be generated as a result of a
expected vari.ation in frequency and not a5 ~ result of a fault.
The output of the third two-input summing amplifier ~2 is
a signal ~ V) having 2 ~agnitude which is the algebraic sum
of the magnitude of t~e signal~ applied to the inverting and
~on-inverting inputs of the amplifier 92. Due to the short term
memory of the band pass filter 90, as previously described,
im~ediately following occurrence of a fault, the output
signal ~ (IZ~-~) from the amplifier 92 is initially equal to the
post-fault magnitude of the quantity (IZ-V) minus the prefault
magnitude of that quantity.
The signal ~ (IZ-V) is coupled to the input of a fourth
AC couple circuit 94. The fourth AC couple circuit 94 is the same
type as the previously described first ~C couple circuit 36. The
output of the fourth AC couple circuit 94, which is the same as
the input signal except that any DC component haæ been remo~ed, is
coupled to the input of a fourth absolute value circuit 96, which
is the same type as the pre~iously descri~ed first absolute value
circuit 54. The output of the fourth a~solute value circuit 96,
which is a signal whose magnitude is t~e absolute value of the
magnitude of the input signal, i~ coupled to the input of a zero
suppression circuit 98.
In the preferred embodiment, the zero suppression circuit
98 comprises a circuit which removes that portion of the input
signal t~at is less tha~ a pre-set level. Consequently, the zero
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suppression circuit 98 passe5 only ~hat portion of the input
signal which is grea~er th~n the pre-~e~ level. In the preferred
embodiment, the zero ~uppres~ion ~ircuit 98 is of t~e type shown
and described under the heading ~DEAD ZONE" on page 25-2Ç of the
aforemention~d ~No~linear Clrcuits H~ndbook", whose
output is a signal ~ (IZ-V) having a ~agnitude which is
su~stantially equal to ~hat portion of the magnitude oP the input
signal which exceeds a predetermined level. In the preferred
e~odiment t~is predeter~ined l~vel is 0.25 per unit of rated
volage.
The I~2S signal, which was generated as described with
respect t~ Figure 3, is coupled to the input o~ a negative
sequence reach adjust circuit 102 and the input of a first fixed
reach circui~ 104. In the preferred embodiment, the negative
sequence reach adjust circuit 102 is an operational amplifier
circuit with adjustable gain. The first fixed reach circuit~104
is pre~erably a fixed gain equivalent to a reach of 6 ohms on a SA
rated relay. The output of ~he negati~e sequence reach adjust
circuit 102, which has a magnitude determined ~y the desired reach
of the protective relay, is coupled to the input of a fifth AC
couple circuit 106. The fifth AC couple circui~ 106 is of the same
type as the previously described first AC couple circuit 36.
The output of the fifth AC couple circuit 106, which.is
the ~ame as the input except t~at any DC component has been
removedl is coupled to an input of a fourth two-input summing
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amplifier 10~ t~e pre~err~d em~odiment, ~he f~urth two-input
~umming ampli~ier 10~ i~ an operational amplifier whiçh generates
an output signa~ having magnitude which is equal to the algebraic
~um of the magnitudes of ~he input signalsO The output of the
first fixed reach circuit 10~, which is proportional to a fixed
reach of 6 ohms on a 5A rated relay, is coupled to the second
input of t~e fourth two-input ~umming amplifier 108. The output
of the fourth two--inpu~ summing amplifier 108 is coupled to the
input of a sixth AC couple circuit 110. The sixth AC couple
circuit 110 is of the ~ame type as the previously described first
AC couple circuit 36.
T~e output of the sixth AC couple circuit 110, which is
the I2Z signal representa~ive of the overreaching zone with any
DC component re~oved, is coupled ~o the input of a fourth
electronic swi~ch 112 and a non-invert:ing input of a fifth
two-input summing amplifier 114. ~he ~hird electronic switch 112
is of the same type as the previou~ly described second electronic
switch 72 in that a ~'low~ signal appliled to the ~ontrol input will
cause t~e ~ignal appearing at the switch input to be connected to
t~e switch output. The output of the ~hird electronic switch 112
is connected to the input ~ a third band pass filter 116. In the
preferred embodiment, the third band pass filter 116 is the same
type as the previously described second band pass filter 90,
having a Q substantially equal ~o 3.8, a gain of one and a center
re~uency which is equal to the rated ~re~uency o~ the power
system; t~at is, 50~z or 60Hz.
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~ 3 ~ llRC04716
The outp~t o~ the thi~d ~and pass filt~r 116 is coupled
to the inver~ing input of ~he ~ifth tw~-input su~min~ amplifier
114. In the preferxed emb~diment, the output signal I2 from
the fifth two-input summing ampli~ier ll~, iS a ~;ignal whose
magnitude is equal to the ~lgebraic ~um of the magnitu~es o the
signals applied to the inver~ing and non-inverting inputs. Due to
the short term memory o~ ~he third band pass filter 116, the
output ~ignal ~ I2 from ~he a~pli~ier 114, iEmediately the
following occurrence o a fau~t, is initially equal to the
postfault negative ~equence component of ~h~ curre~t ~inus the
prefault negatiYe sequence component of the current; or that
portion of the negative ~equ~nce co~ponent current which is
attributable to the fault when the ~witch 112 is gated~ When
switch 112 is not ga~ed, it is equal to the negative sequence
component o~ the current. The si~nal I2 is coupled to the
input of a ~ifSh absolute value cirauit 118 which is the sa~ type
as .the previously descri~ed ~irst a~solute value circuit 54. The
output o~ the fifth absolute value circuit 118 i5 a signal ~ I2
whose ~agnitude is the a~solu~e val~e of the ~agnitude of the
input signal.
The MIoF signal, which was generated as described with
respect to Fiqure 3, is c~upled to the input of a zero sequence
reach adjust circuit 120 and the input o~ a second fixed reach
circuit 122. In the p~e~erred embodiment, the 7.ero seguence reach
adjust circuit 120 is an op amp wit~ adjustable gain. The output
i of the zero sequence reach adjust circuit 120, which has a
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~ llRC04716
magnitudP de~ermined by the desired reach o~ the protective relay,
i~ coupled to one input of a ~ix~h ~wo-input summing amplifier
124. The second fixed reach circuit 122 is the same type as the
previousl~ described first fixed reach circui~ 104. The output of
the second fixed reach circuit 122, which is also proportional t~
a reach of 6 ohms on a 5 amp rated rel~y, is coupled to the ~econd
input of the ~ixth two-input ~u~ming amplifier 124. In the
preferred e~bodiment, the sixth two-input summing amplifier 124 is
an operational ~mplifier which generates an output signal having a
magnitude which i equal to the algebraic su~ of the magnitudes of
the signals applied at the inputs.
The output of the si~th two-input ~umming amplifier 124
is coupled to the input of a ~ixth AC couple circuit 126. T~e
sixth AC couple circuit 126 is the same type as the previously
described first AC couple circuit 36. The output of the sixth AC
couple circuit 126, which is the IoZ ~ignal representative of
the overreaching zone wit~ any DC co~ponent removed, is coupled to
the input of a ~ourth electronic switch 128 and ~he non-inverting
input of a seven~h two-input ~umming a~plifer 130. T~e ~ourtb
electronic switch 128 is the same type as the previously described
second electronic switch 72 i~ ~hat a ~low~ signal applied to the
control signal input causes the signal appearing at the switch
input to be connected tn the switch output.
The output of the ~our~h electronic swi~ch 128 is coupled
to the input of a fourth band pass filter 132. The fourth band
pass filter 132 is the same type as the previously described third
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~4~9 llRC04716
band pass filter 116, having a Q preferrably equal to 3.8, a gain
of one and a center frequency which is ~gual to the rated
frequency of the power ~ys~em; ~hat is 50Hz or 60Hz. The output
of the seventh two-input su~ming amplifier 132 is a signal having
a magnitude which i~ the ~lgebraic 6um of the magnitudes of the
signals applied to the inverting and ~on-inverting inputs of the
a~plifier 130. Due to ~he ~hort term memory of the ban~ pass
filter 132, t~e output signal from the ampiiier 130 is,
immediately following t~e currents of a ~ault1 initially equal to
the postfault zero sequence component of the current minus the
prefault zaro sequence co~ponent of the current; or the zero
~equence component of the current which is attributable to the
fault when swit~h 128 i~ gated. When ~witch 128 is not gaked, it
is equal to the zero sequence component of the current. The
tO signal is coupled to the input of a sixth absolute value
circuit 134 which is the ~ame type ,as the previously descri~ed
first absolute value circuit 5i.
The output A Io of ~e sixth absolute value circuit
134 which is the ~ame type as the previously described absolute
value circuit 54 is the absolute value of the input signal. A NOR
signal, which is in a low state during the period that a p~le is
open on the transmission line, is coupled to ~he control inputs o~
the third 112 and fourth 128 electronic switches.
Referring now to Figure 5, there is shown a block diagram
of an out-of-step blocking circuit, generally designated 200. The
MIZT signal, which was generated as described wi~h respect to
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13~4~9 llRCo4716
Fi~ure 4, is coupled ~o a non-inverting input of a five-input
6umming amplifier 2021 In the pref~rred emb~diment~ the
five-input summing amplifier ~02 i~ an operational amplifier which
produces an output signal having a magnitude which is equal to the
algebraic sum of the magnitudes o~ t~e siqnals applied to its
five-inputs. The I2T, ~ Io~ Z-V) and ~I2 signals,
which wexe generated as de~cribed wi~h respect to Figure 4, are
each coupled to an inverting input of the five-input su~ing
amplifier 202.
The output of the five-input summing amplifier 202 is
coupled to the input of a reach adjust circuit 204. In the
pr~ferred smbodiment, t~e reach adjust circuit 204 i~ an op amp
with adjustable gain. The output of the reach adjust circuit 204,
wbich has a gain selected to provide t~e desired reach for the
out-of-step protection, is coupled t:o a non-inverting input of a
~our-i~put sum~ing amplifier 206. In the preferred embodi~e~t,
the four-input su~ming amplifier 20~; is an operati~nal amplifier
which produces an output signal having a magnitude which is equal
to the albebraic 8Um ~f the magnitudes oP t~e signals applied to
the inverting and non-inverting inputs.
A first bias sig~al is applied to a non-inverting input
of ~he four-input summing amplifier 206~ The Vl signal, which
is generated as described with respect to Figure 4, is coupled to
an inverting input of the four-input summing a~plifier 206. A
second bias i~ coupled to an inverting input of the four-inpUt
summing amplifier 206 through a fifth electronic switch 208. The
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~ 3 ~ llRC04716
fifth electronic switch 208 i6 the ~ame type as the previously
described ~econd electronic ~witch 72 in that a "low" ~ignal
applied to the ~ignal control input causes ~he signal appearing at
the switch input to be connec~ed ~o the switch o~tput.
The IlSA signal, which i6 generated as described with
respec~ to Figure 3, is coupled to th~ control input of the fifth
electronic switch 208. The output of the four-input summing amp-
lifier 206 is connected to the input o~ an "integrator" circuit
210. In t~e preferred embodi~ent, ~he "integra~or" circuit 210
~omprises an operational amplifier having a feedback circuit
connected ~e~ween it~ output and i~s inpu~ TAe faedback circuit
comprises a resistor and a capacitor connected in parallel. The
inp~t to ~he ~lntegrator" circuit 210 is ~he input to the
operational amplifier and the outpu~ of the nint~grator" circuit
210 is the output of the operational amplifier. The output of the
integrator circuit 210 is coupled to the input of a second level
detector 212 and the input of a half wave rectifier 214. The
second level detector 212 is the same type as the previously
described first level detector 88 and produces an output signal
POSB when the magnitude of the input signal exceeds a
predetermined level. In the preferred embodiment this
predetermined level is approximately 3Omv to provide a threshold
to overcome extraneous signals. The output POSBR of the half wave
rectifier is the half wave rec~ified input signal which produces
an output when the integrator 210 ou~put i5 in the trip direction.
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1 3149~9 llRC04716
The out-of-step blocking unit of the present in~ention
operates as follows. Ass~ming a normal situation where there are
no faults or impedence ~winys, the IA2S, MIoF, A I2
and ~ X~ ~ignals will be essentially equal to zero becaus
under normal load conditions the tran~missis~ system will produce
only positive sequence quantities. The ~ (IZ-V~ ~ignal will be
e~sentially equal to zero because there is no c~ange in the
positive sequence current or voltage during ~teady ~tate load
conditions. The IlSA ~ig~al will be a logic one i~ the load
current is gre~ter than the level detector sensitivity. The NOR
~ignal is a logic one. The Vl and IAlS signals will be
approximately 90 out of phase causing switch 70 to be off and
~witch 72 to be on for 90. Thus ths MIZT signal will be
essentially equal to t~e IZT signal, and both will be proportional
to the product of the load current and the relay reach. During
normal load conditions, the output of integrator 210 will be in
the restraint polarity and there will be no output at POSB or
POSBR.
Ass~ing now a fault within the protected zone the
IA2S, MIoF, ~I2, ~ Io~ and ~ ~IZ-V) signals assume
values which are essentially established by the fault type and the
fault location. The IlSA and NOR signals are both logic one.
The Vl and IA1S signals will be approximately in phase thus
switch 70 will be on and switch 72 will be off. Therefore, the
restraint signal IZT will be nearly zero while the operate signal
MIZT will proportional to the product of the faul~ current times
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~ 3~ 9 llRC04716
the reach. The effects of the restraint signals ~ Io
and ~ (IZ-V) will be tn 610W or block the operation of the POSB
unit thus ensuring coordina~ion between the operation of POSB and
the tripping elements of the protective ~cheme.
Assuming now there i5 an i~pedence swing which is not
considered a fault, the syste~ currents and voltages will be
varying more slowly ~han during a ~ault condi~ion and will be
positive sequence guantities ~o that ~he IA2S, ~IoF,
~I2~ o and ~(IZ-V) ~ignals will all be essentially
equal to Yero. In this condition the net inpu~ to the ~umming amp
206 due to MIZT and Vl will be in ~he operate direction when the
wing impedance ~nters the out of-step blocking characteristic~
The non-switched bias ~ignal ~dds to ~he net operate ensuring that
the out-of-step unit will have a largler operating signal magn~tude
than the associated tripping units. ~hen the output of integrator
210 is of the tripping polarity, a ~ignal is produced at POSBR
which is used as a restraint fiignal in some of the associated
tripping units. T~us the out-of-step blocking unit will always
produce an output before the trip units on a swing co~dition.
T~e out-of-step blocking unit of the present invention
has a num~er of advan~ages over the prior art out-of-step blocking
units. ~mong these advantages are coordination of the out-of-step
blocking unit and the ~ripping units on internal faults afforded
by the addition of restraining signals to the out-of-step blocking
unit. As described above, these added signalS are ~I2,
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3 ~ llRC04716
~ Io and ~(IZ-V) which prevent or ~ubstantially delay
t~e operation of the out-of-~tep blo~king unit on internal
faults. This permit~ a ~ubstantially ~implified application of
the out-of-step blocki~g unit compared to the prior art designs.
As previously described, the ~(IZ-V~ signal is egual
to the difference in the (IZ-V~ quantity betw~en the fault and
prefault values. The ~se of these additional restraint ~ignals to
prevent or ~ubstantially delay the oper~tion of ~e out-o~-step
bloc~ing unit on internal faul*s simpli~ies th~ appli~a~ion since
the timer in the ou~-of-s~ep ~locking logic, which is
traditionally the only ~etting ~hat discriminates b~tween a ~wing
and a ~ault, may now be get without a rigorous determination o~
the i~pedence-time charac~eristic of the swing locus while
assuring ~hat the fastes~ swing will be detected. Consequently,
not only does the ou~-of-step blocking unit of the present
invention increase the reliability a,f the protecti~e relay system,
it also ~implifies i~s applicatio~ in the use enYiroment.
Whil~ the pr~sent invention has been des~ribed with
referenc~ to a speci~ic embodiment thereof, it will be obvious to
thos~ skilled in the art that various changes and modifications
may be made without departing fro~ t~e invention in its broader
aspects. It is contemplated in the appended cl~i~s to cover all
variations and modifications of the invention that come within the
true spirit and scope of my invention.
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