Note : Les descriptions sont présentées dans la langue officielle dans laquelle elles ont été soumises.
1 333~27
DISPLAY APPARATUS
FIELD OF THE INVENTION AND RELATED ART
The present invention relates to a display
apparatus, particularly a ferroelectric liquid crystal
display apparatus suitable for moving display using a
cursor, mouse, etc.
For a CRT (cathode ray tube) wherein an image
is formed by utilizing persistence on a fluorescent
screen and a TN-type LCD (twisted nematic-type liquid
crystal device) wherein an image is formed by utilizing
a transmittance change depending on an effective value
of driving voltage, it is necessary to use a
sufficiently high frame frequency which is a frequency
required for forming one picture based on their display
principle. The required frame frequency is generally
considered to be 30 Hz or higher. The frame frequency
is expressed as the reciprocal of the product of a
number of scanning lines and a horizontal scanning time
for scanning each scanning line. The scanning
processes or modes known at present include the
interlaced scanning process (with skipping of one or
more lines apart) and the non-interlaced scanning
process. Other practical scanning processes may
include the pairing process and a process comprising
simultaneous and parallel scanning of divided portlons
of a picture screen, while the latter process is
2- 1333~27
--2
restricted to LCD. The NTSC standard system has
adopted an interlaced scanning process comprising a 2
fields/frame and a frame frequency of 30 Hz, wherein
the horizontal scanning time is about 63.5 ~sec and
the number of scanning lines is about 480 (for
constituting effective display area). The TN-type LCD
has generally adopted a non-interlaced system including
200 - 400 scanning lines and a frame frequency of 30 Hz
or higher. Further, for CRT, there has been also
adapted a non-interlaced scanning system using a frame
frequency of 40 - 60 Hz and 200 - 1000 scanning lines.
Now, it is assumed to drive a CRT or TN-type
LCD comprising 1920 (number of scanning lines) x 2560
pixels. In the case of an interlaced system using a
frame frequency of 30 Hz, the horizontal scanning time
is about 17.5 ,usec and the horizontal dot clock
frequency is about 147 MHz (without consideration of
horizontal flyback for CRT). In the case of CRT, the
horizontal dot clock frequency of 147 MHz leads to a
very high beam scanning speed which exceeds by far
the maximum electron beam modulation frequency of a
beam gun used in picture tubes available at present, so
that accurate image formation cannot be effected even
by scanning at 17.5 ~sec. In the case of TN-type LCD,
driving of 1920 scanning lines corresponds to a duty
factor of 1/1920 which is much lower than the minimum
duty factor of about 1/400 available at present, so
1333~27
--3--
that displaying is failed. On the other hand, if
driving at a practical horizontal scanning time is
considered, the frame frequency becomes lower than 30
Hz so that the scanning state is visually observed and
flickering is caused to remarkably impair the display
quality. In this way, the enlargement and
densification of a picture for CRT and TN-type LCD has
been restricted so far because the number of scanning
lines cannot be sufficiently increased because of
restriction by the display principles and driving
elements.
On the other hand, in recent years, Clark and
Lagerwall have proposed a ferroelectric liquid crystal
device having both a high-speed responsive
characteristic and a memory characteristic
(bistability).
The ferroelectric liquid crystal device shows
a chiral smectic C phase (SmC*) or H phase (SmH*) in a
specific temperature range, and in this state, shows a
bistability, i.e., property of assuming either a first
optically stable state or a second optically stable
state depending on an applied electric field and
retaining the resultant state in the absence of an
electric field applied thereto. Further, the
ferroelectric liquid crystal device shows a quick
response to a change in electric field and is therefore
expected to be widely used as a display device of a
1333427
--4--
high speed and memory-type.
However, it is generally difficult for such a
ferroelectric liquid crystal device to show an ideal
bistability as proposed by Clark et al but it is liable
to show a monostability. Clark et al used an alignment
control method, such as application of a shearing force
by relative movement or application of a magnetic field
in order to realize a permanent bistability. From the
viewpoint of production technique, however, it is
advantageous to apply uniaxial orientation treatment,
such as rubbing or oblique vapor deposition to a
substrate. Such a uniaxial orientation treatment
applied to a substrate for alignment control has
sometimes failed to provide a permanent bistability.
In the resultant alignment state failing to provide a
permanent bistability, i.e., a so-called monostable
alignment state, a biaxial orientation state formed
under application of electric fields tends to be
transformed into a uniaxial orientation state under no
electric field in a period ranging from several
milliseconds to several hours. For this reason, a
display apparatus using such a ferroelectric liquid
crystal device showing monostability has involved a
problem that an image formed under application of
electric fields is lost in accordance with the removal
of the electric fields. Particularly in a multiplexing
drive, there has been observed a problem that written
1333427
states in pixels on non-addressed scanning lines are
gradually lost.
In order to solve such a problem, there has
been proposed a driving scheme (refreshing drive
scheme) wherein pixels on a selected scanning line are
selectively supplied with a voltage for providing
"black" or a voltage for providing "white", the
scanning lines are sequentially selected in a cycle of
one frame or one field, and the cycle is repeated for
writing. Such a refreshing drive scheme provides very
little fluctuation in transmittance and has obviated
difficulties, such as visual recognition of a writing
scanning line (where a higher luminance than the other
lines can be easily recognized) and occurrence of
flickering under a frame frequency lower than 30 Hz.
According to our study, a similar effect has been
confirmed even under a low frequency as low as about 5
Hz.
The above facts can be effectively utilized to
solve altogether the problems against enlargement and
densification of picture arising from the above-
mentioned essential requirement of CRT and TN-type LCD
that a frame frequency of 30 Hz or higher is required
for driving.
However, such a low-frequency refreshing drive
as described above is too slow for so-called motion
picture display, such as smooth scrolling or cursor
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movement in character compiling or on a graphic
display, thus resulting in deterioration of display
performances. In recent years, there have been
remarkable developments in computers, peripheral
circuits thereof and softwares therefor. For example,
for a large picture and high density display, there has
been spread a display scheme called a multi-window
display scheme, wherein a plurality of pictures are
displayed in superposition in a display area. A
display apparatus incorporating a ferroelectric liquid
crystal device is one which can afford to provide
enlargement and densification of a picture area which
exceeds by far those realized by conventional display
apparatus, such as CRT and TN-type LCD. In accordance
with such enlargement and densification, there arise
problems that the frame frequency is lowered, and the
velocity of smooth scrolling and cursor movement is
lowered even further.
SUMMARY OF THE INVENTION
An object of the present invention is to
provide a display apparatus having solved the above-
described problems, particularly to provide a display
apparatus capable of a high-speed cursor movement and
mouse movement under scanning drive at a low frame
frequency as low as 30 Hz or below.
According to a principal aspect of the present
1333427
--7--
invention, there is provided a display
apparatus, comprising:
(a) a display panel having a display picture
area formed by scanning electrodes and data electrodes
arranged in a matrix;
(b) drive means including a first means for
driving the scanning electrodes and a second means for
driving the data electrodes; and
(c) control means for controlling the drive
means so as to perform a partial rewriting scanning
signal to only a part of the scanning electrodes forming
the display picture area and then repeat the partial
rewriting scanning operation by applying the scanning
selection signal to only the same or a different part of
the scanning electrodes.
According to a second aspect of the present
invention, there is provided a display apparatus,
comprising:
(a) a display panel having a display picture
area formed by scanning electrodes and data electrodes
arranged in a matrix;
(b) drive means including a first drive means
for driving the scanning electrodes and a second means
for driving the data electrodes; and
(c) control means for controlling the drive
means so as to scan-select the scanning electrodes with
skipping of one or more scanning electrodes apart for
one vertical scanning drive of the scanning electrodes
constituting the whole picture area and scan-select the
-8- 1333427
scanning electrodes without skipping for sc~nni~g drive
of only a part of the scanning electrodes constituting
the whole picture area.
According to a third aspect of the present
invention, there is provided a display apparatus
comprising:
(a) a display panel having a display picture
area formed by scanning electrodes and data electrodes
arranged in a matrix;
(b) drive means including a first means for
driving the sc~n;ng electrodes and a second means for
driving the data electrodes; and
(c) control means for controlling the drive
means so as to scan-select the scanning electrodes with
jumping of two or more scanning electrodes apart in one
vertical scanning and scan-select non-adjacent scanning
electrodes in at least two consecutive times of
vertical scanning for scanning drive of the scanning
electrodes constituting the whole picture area, and
scan-select the sc~n~ing electrodes without skipping
scanning drive of only a part of the scanning
electrodes constituting the whole picture area.
These and other objects, features and
advantages of the present invention will become more
apparent upon a consideration of the following
description of the preferred embodiments of the present
invention taken in conjunction with the accompanying
-9- 1333427
drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 is a block diagram of a display
apparatus according to the invention;
Figure 2 is a time chart showing time
correlation between signal transfer and driving;
Figures 3A - 3D and Figures 4A - 4C
respectively show a set of driving signal waveforms
used in the invention;
Figure 5 is a block diagram of an apparatus
body;
Figure 6 is a flow chart showing an operation
routine for whole display picture scanning drive and
partial rewriting scanning drive; Figure 7 is a flow
chart showing an operation routine for partial
rewriting scAnn;ng drive; Figure 8 is a flow chart
showing one frame scanning drive;
Figure 9 is a flow chart showing a partial
rewriting routine; Figure 10 is a whole display picture
scAnn;~g drive routine;
Figure 11A is a time table for a case where
the number of scAnn;ng electrodes for partial rewriting
scA~n;ng < the number of whole picture scanning
electrodes; Figure 11B is a time chart for a case where
the number of scanning electrodes for partial rewriting
scAnn;ng > the number of whole picture scanning
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electrodes;
Figure 12 is an illustration of an example of
display image used in the invention;
Figure 13 is a schematic perspective view for
illustrating a ferroelectric liquid crystal device used
in the invention;
Figure 14A is a plan view of a device used in
the invention; and Figure 14B is a sectional view taken
along the line A-A in Figure 14A.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
A. Signal Transfer Scheme
Figure 1 is a block diagram of a display
apparatus according to the present invention showing an
arrangement of a liquid crystal display apparatus and
an apparatus body for supplying display data signals.
A displav panel 11 comprises a matrix
electrode structure composed of 400 scanning electrodeS
12C and 800 data electrodes 13D between which a
ferroelectric liquid crystal is disposed. The scanning
electrodes 12C are connected to a scanning electrode
drive circuit 12 and the data electrode 13D'are
connected to a data electrode drive circuit 13. The
scanning electrode drive circuit 12 is provided with a
decoder 12A and an output stage 12B. The data
electrode drive circuit 13 is provided with a shift
register 13A, a line memory 13B and an output stage
-"- 13~427
13C.
First of all, scanning electrode address data
for addressing scanning electrodes 12C and image data
are supplied from an apparatus body 14 to a control
circuit through four signal lines PDO, PD1, PD2 and
PD3. In this embodiment, scanning electrode address
data (AO, A1, A2, ..., A11) and image data (DO, D1, D2,
D3, ..., D798, D799) are transferred respectively
through the same transmission signal lines PDO - PD4,
so that it is necessary to differentiate the scanning
electrode address data and the image data. In this
embodiment, a discriminating signal A/D- is used. The
A/D- signal at a high level means scanning electrode
address data, and the A/D- signal at a low level means
image data. The A/D- signal also contains a meaning of
a transfer-initiation signal for transfer of display
data.
When scanning electrode address data are
supplied to the scanning electrode drive circuit 12 and
image data are supplied to the data electrode drive
circuit 13, the scanning electrode address data A0 -
A11 and the image data DO - D799 are serially supplied
through the signal lines PDO - PD3. It is necessary to
provide a circuit for distributing the scanning
electrode address data AO - A11 and the image data DO -
D799 or extracting the scanning electrode address data
A0 - A11. This operation is performed by the control
-12- 1333~27
circuit 15. The control circuit 15 extracts the
scanning electrode address data A0 - A11 supplied
through the signal lines PD0 - PD3, temporarily stores
the data and supplies the data to the scanning
electrode drive circuit 12 in a horizontal scAnning
period for driving a designated scanning electrode 12C.
The sc~nn;ng electrode address data A0 - A11 are
supplied to the decoder 12A in the scanning electrode
drive circuit 12 and select a scanning electrode 12C
through the decoder 12A.
On the other hand, the image data D0 - D799
are supplied to the shift register 13A in the data
electrode drive circuit 13 and separated into image
data D0 - D799 for pixels corresponding to the data
electrodes 13D (800 lines) while being shifted for 4
pixels each by transfer clock signals CLK. When a
shifting operation of the data for one horizontal
scanning line is completed by the shift register 13,
800 bits of the image data D0 - D799 in the shift
register 13 are transferred to the line memory 13B and
memorized therein in a horizontal scanning period.
Further, in this embodiment, the drive of the display
panel 11 and the generation of the scanning electrode
address data A0 - A11 and image data D0 - D799 in the
apparatus body 14 are not synchronized, so that it is
necessary to synchronize the control circuit 15 and the
apparatus body 14 at the time of display data transfer.
_13_ 1~33427
For this purpose, a synchronizing signal Sync is
generated in the control circuit for each horizontal
scanning.
The signal Sync is associated with the signal
A/D-. The apparatus body 14 always watches the signal
Sync to transfer display data when the signal Sync is
LOW and does not effect transfer after transfer of data
for one horizontal scanning when the signal Sync is
HIGH. More specifically, referring to Figure 2, at an
instant when the signal Sync is turned LOW, the A/D-
signal is turned HIGH at a point A and then the control
circuit 15 returns the Sync signal to HIGH during the
display data transfer period. Then, at a point B which
is one horizontal scanning period counted from the
point A, the Sync signal is returned to LOW. If the
apparatus body 14 successively transfers display data
at the point B, i.e., if a subsequent scanning
electrode is driven, the A/D- signal is again turned
HIGH to start the transfer. Refresh drive or whole
display picture (area) scanning drive is performed in
this embodiment, so that the drive is continuously
effected line-sequentially.
The above-mentioned one horizontal scanning
period (corresponding to one scanning selection period)
is prescribed depending on the characteristic of the
ferroelectric liquid crystal and the driving method in
consideration also of optimum driving conditions. In
_14_ 1333 127
this embodiment, the one horizontal scanning period was
set to about 250 ~sec at room temperature so that the
frame frequency was about 10 Hz. Further, the transfer
clock CLK frequency was 5 MHz, and the transfer time of
the sc~nni ng electrode address data and image data was
about 40.8 ,usec, and the waiting time shown in Figure 2
was 209.2 ~sec. The control signal CNT is a control
signal for generating a desired driving waveform. This
is supplied from the control circuit 15 to the
respective drive circuits 12 and 13. The time for
outputting CNT is the same as the time for outputting
the scanning electrode address data A0 - A11 from the
control circuit 15 to the scanning electrode drive
circuit 12 and also the same as the time for
transferring the image data in the shift register 13A
to the line memory 13B.
The time for outputting the CNT signal is
switched at a point which is after the completion of
the transfer time (40.8 ~sec) from the low level-
starting point (A point) of the Sync signal and onehorizontal scanning period counted from the access
starting point for the previous line. In this
embodiment, a C period set between the termination of
the transfer time and the point (B) of a subsequent
signal turning low is determined at constant.
The above communication is effect between the
drive circuits 12 and 13, and also between the
_ -15- 133~7
apparatus body 14 and the control circuit 15, and the
display panel is driven according to the above time-
sequence.
B. Display Scanning Scheme
In the present invention, refreshing drive is
performed by an interlaced scanning (jump-scanning)
scheme as described below and partial rewriting drive
is performed by a non-interlaced scanning (non-jump-
sc~nn;ng) scheme.
1. Refreshing or Whole Display (Area) Scanning Drive
A scanning selection signal is sequentially
applied to the scanning electrodes with jumping of N
lines apart (N 2 1, preferably 4 < N < 20), in one
vertical sc~nn;ng period (corresponding to one field
period), and one picture scanning (corresponding to one
frame scanning) is effected by N+1 times of field
sc~n;ng. In the present invention, it is particularly
preferred that one vertical scanning is effected two or
more scanning electrodes apart and scanning electrodes
not adjacent to each other are selected (scanned) in at
least two consecutive times of vertical scanning.
Figure 3A shows a scanning selecti~n signal
Ss, a scanning non-selection signal SN~ a white data
signal IW and a black data signal IB. Figure 3B shows
a voltage waveform applied to a selected pixel among
the pixels on a selected scanning electrode receiving a
scanning selection signal (a voltage (IW-Ss) applied to
-16- 1 3 3 3~ 2 7
a pixel receiving a white data signal Iw), a voltage
waveform applied to a non-selected pixel on the same
selected sc~nning electrode (a voltage (IB-SS) applied
to a pixel receiving a black data signal IB), and
voltage waveforms applied to two types of pixels on a
non-selected sc~nn;ng electrode receiving a sC~nn;ng
non-selection signal. According to Figures 3A and 3B,
the pixels on a selected sc~nning electrode are
simultaneously supplied with a voltage providing one
orientation state of a ferroelectric liquid crystal to
be erased into a black state based on such one
orientation state of the ferroelectric liquid crystal
(a pair of cross nicol polarizers are so arranged as to
effect erasure into a black state in this embodiment,
but it is also possible to arrange polarizers so as to
cause erasure into a white state) in phase t1
regardless of the kind of a data signal supplied. in a
subsequent phase t2, a selected pixel on the selected
scanning electrode (Iw-Ss) is supplied with a voltage
(V2+V3) providing a white state based on the other
orientation state of the ferroelectric liquid crystal,
and the other pixels on the selected scanning electrode
(IB-SS) are supplied with a voltage (V2 - V3 = V3) not
changing the black state formed in the phase t1. On
the other hand, the pixels on a scanning electrode
receiving the scanning non-selection signal are
supplied with voltages +V3 below the threshold voltage
~_ -17- 1333~27
of the ferroelectric liquid crystal. As a result, in
this embodiment, the pixels on the selected scanning
electrode are written into either black or white
through phases t1 and t2 and retain their states even
when they are subsequently supplied with a scanning
non-selection signal SN.
Further, in this embodiment, in a phase t3, a
voltage of a polarity opposite to that of the data
signal in the writing phase t2 is supplied from a data
electrode. As a result, a pixel at the time of
scanning non-selection is supplied with an AC voltage
to improve the threshold characteristic of the
ferroelectric liquid crystal. Such a signal applied
through a data electrode is called an auxiliary signal
and is explained in detail in U.S. Patent No.
4,655,561.
Figure 3C is a time chart of voltage waveforms
for providing a certain display state. In this
embodiment, a scanning selection signal is applied to
the scanning electrodes three lines apart in one field,
and one frame sc~nn; ng (one picture scanning) is
effected by 4 consecutive times of field scanning so
that no adjacent pair of scanning electrodes are
supplied with a scanning selection signal together in 4
consecutive fields. As a result, a scanning selection
period (t1 + t2 + t3) can be set longer as required at
a low temperature, so that occurrence of flickering
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attributable to sc~nn; ng drive at a low frame frequency
can be remarkably suppressed even at such a low frame
frequency as 5 - 10 Hz, for example. Further, by
applying a sc~nn;ng selection signal so that non-
S adjacent sc~nn;ng electrodes are selected inconsecutive four field sc~nnings, an image flow can be
effectively solved.
Figure 3D shows an e~ho~iment using driving
waveforms shown in Figure 3A. In this embodiment, the
scAnning electrodes are selected 5 lines (scanning
electrodes) apart so that non-adjacent scanning
electrodes are selected in 6 times of consecutive field
sc~nn1ng.
Figures 4A and 4B show another driving
embodiment used in the present invention.
According to Figures 4A and 4B, on a scanning
electrode receiving a sc~nning selection signal Ss, all
or a prescribed part of the pixels are simultaneously
supplied with a voltage for erasure into a black state
in phase T1 (= t1+t2) regardless of the types of data
signals, and in phase t3, a selected pixel (IW-Ss) is
supplied with a voltage (V2+V3) for inversion writing
into a white state and the other pixels (IB-SS) are
supplied with a voltage (V2-V3 = V3) not changing the
black state formed in the phase T1. Further, phases t2
and t4 are provided for applying auxiliary signals so
as to apply an AC voltage to the pixels at the time of
1333~27
-
non-selection, similarly as in the previous embodiment.
Figure 4C is a time chart of voltage waveforms
for providing a certain display state. According to
the ~mho~iment shown in Figure 4C, a scAnn;ng selection
signal is applied to the sc~nn;ng electrodes with
jumping of 4 lines apart in one field so as to complete
one frame scAnn;ng in 5 fields. Also in this
embodiment, non-adjacent sc~nn;ng electrodes are
supplied with a sc~nn;ng selection signal in
consecutive 5 times of field sc~nning
The present invention is not restricted to the
above-described embodiments but can be effected
generally in such a manner that a scanning selection
signal is applied to the scAnn;ng electrodes with
jumping of one or more lines apart, preferably 4 - 20
lines apart. Further, in the present invention, the
peak values of-the voltages V1, -V2 and +V3 may be set
to satisfy the relation of IV1~ V2¦ > ¦+V3 J,
preferably JV1¦ = ¦-V2¦ > 2¦+V3¦- Further, the pulse
durations of these voltage signals may be set to
generally 1 psec - 1 msec, preferably 10 ~sec - 100
~sec, and may preferably be set to be longer at a lower
temperature and shorter at a higher temperature.
2. Partial Rewriting Drive
Partial rewriting may be performed by
intermitting the above-mentioned whole display area
sc~nn;ng by refreshing drive in the present invention.
1333~27
~~ -20-
Accordingly, some operational relationships between
partial sc~nning of sc~nning electrodes used in the
partial rewriting drive and the whole display picture
sc~nn;ng are set forth hereinbelow.
(1) When a demand of rewriting a part of a display
picture occurs during a whole display picture sc~nn;ng
by refreshing drive, the field scanning at the time of
the occurrence is finished and then a partial sCAnn;ng
of sc~nning electrodes is performed.
(2) The partial rewriting drive by partial
sc~nning of sc~nn;ng electrodes is performed by a non-
interlaced sc~nn;ng mode.
(3) The maximum number of sc~nn;ng lines for the
partial sc~nn;ng of scAnn;ng electrodes is set equal to
the number of the total sc~nn;ng lines constituting the
whole display picture area (the number of scanning
lines for one frame sc~nn;ng). In other words, at a
point of time when the number of scanning lines for
partial sc~nning exceeds the number of scanning lines
for the whole display picture scanning, the partial
sc~nning of sc~nning lines is interrupted to resume the
whole display picture scAnn;ng.
(4) When a partial sc~nn;ng of sc~nning lines is
terminated while the number of scanning lines for the
partial sc~nning is fewer than the maximum number of
scAn~ing lines for the partial scanning defined in the
above paragraph (3), the field sc~nn;ng drive is
1~33427
- -21-
resumed from a first scanning line for a field scanning
which is subsequent to the field scanning effected
immediately before the partial Sc~nn; ng of sc~nn;ng
lines.
(5) Image data rewriting for the VRAM (memory for
image data storage) does not depend on the rewriting
speed of the display panel.
(6) Image data transferred to the display panel
during the whole display picture scanning are those at
the time of being transferred.
Figure 5 shows a circuit structure for
conducting a series of operations defined in the above
paragraphs (1) - (6). More specifically, Figure 5
shows a detailed structure of the apparatus body 14
shown in Figure 1, which is functionally provided with
a CPU unit 51, a VRAM unit 52 and a sequencer unit 53.
The CPU unit constitutes a control center of
the apparatus body 14 and functions as the instruction
source of image data generation.
The VRAM unit 52 comprises a VRAM 521 and a
VRAM timing signal generator 522 and functions as a
memory for storing image data.
The sequencer unit 53 comprises a first
address switch 531, a second address switch 532, a 400-
line counter 533, a scanning counter (8-line counter)
534, a 50-line counter 535, a flag memory 536, a
sequencer 537, an input/output port 538, and a 800-dot
l333~27
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--22--
counter 539. The sequencer unit 53 controls the access
of the CPU unit 51 to the VRAM unit 52 and also the
VRAM unit 52 with respect to image data transfer to the
display panel 11.
A VA signal for access to an address in the
VRAM 521 is an address signal selected from a BA
signal, an ADR signal and an RA signal as follows:
(1) BA signal: A VRAM address signal for access to a
partial rewriting drive of the display panel 11.
(2) ADR signal: A VRAM address signal at the time of
image data generation from CPU 51.
(3) RA signal: A VRAM address signal for access to a
whole display picture sc~nn;ng drive of the display
panel.
The above-mentioned BA signal, ADR signal and
RA signal are subjected to selection by the first
address switch 531 to be outputted as a VRAM address VA
signal. The first address switch 531 is controlled by
the sequencer circuit 537.
The sc~nning counter 534 is a counter for
defining a sc~nn;ng scheme and counts the number of
scAnning lines in jump-sc~nning for the refreshing
drive. In this embodiment, the scanning lines are
jump-sc~nneA 7 lines apart.
The 50-line counter 535 defines the number of
sc~nning lines in one field of the refreshing drive.
In this embodiment, 400 scanning lines are jump-scanned
I333~27
--23--
7 lines apart and are frame-scanned in 8 fields, so
that 50 scanning lines are counted to make one field.
The 400-line counter 533 counts a prescribed number of
sc~nning lines (set to 400 lines in this emhorlim~nt)
5 and functions as a frame counter in the whole display
picture sc~nni~g. In the partial rewriting drive, the
400-line counter 533 generates sc~nn;ng line address
data for the partial scAnn;ng of scanning lines and
causes an access to the VRAM address.
The second address switch 532 is a circuit for
selecting either one of the BA signal and ADR signal
for access (FA) to the flag memory 536. The two kinds
of the flag memory address signals are selected by the
sequencer circuit 537.
The flag memory 536 is a memory for allocating
one bit of data for each sc~nn;ng electrode. The one
bit of data is hereinafter called a "flag". Flags are
generated by writing an image data from the CPU 51 into
the VRAM 521. VRAM address signals (ADR) generated at
the time of rewriting by the CPU 51 into the VRAM 521
are sampled and converted into address signals (FA)
each corresponding to one sc;~nrling electrode, based on
which a flag of "0" or "1" is written in the flag
memory 536. Thus, the location of scanning electrodes
is detected based on the writing of image data by the
CPU 51, and the detected data are written in the flag
memory 536 as flags. Then, in the partial rewriting
1333127
-Z4-
drive of the display panel 11, the flag data in the
flat memory 536 and the BA signals from the 400-line
counter 533 are compared, and the flag of "0" (= "OFF")
or "1" (= "ON") is examined to designate only the
scanning lines for the partial rewriting drive.
The 200-dot counter 539 is a circuit for
counting the amount of image data to be transferred in
one horizontal scanning and controlling the
input/output port 538. In this embodiment, 800 dots of
data are transferred in 4 bits (PD0, PD1, PD2, PD3), so
that 200 (= 800/4) counts is set.
The input/output port 538 transfers the image
data PD0, PD1, PD2, PD3, CLK and A/D- comprising
scanning electrode address data and image data to the
control circuit 15 and receives the Sync signal from
the control circuit.
C. Operational Relationship among the Display data
Generation, Transfer Timing and Display Panel
Figure 6 is a flow chart showing an
operational relationship between the whole display
picture sc~nn;ng drive and the partial rewriting
sc~nning drive. Figure 7 is a flow chart of the
partial rewriting sc~nn;ng drive. Figure 8 is a flow
chart of the whole display picture scanning drive.
Referring to Figures 5 and 6, first of all, as
indicated by "1st ADDRESS SWITCH, RA SELECTION", a VRAM
address signal (RA) from the scAnn;ng counter 534 which
1333~27
-25-
is a counter for the whole display picture sc~nning
drive and the 50-line counter 535 is supplied to the
VRAM 521 as a sc~nn;ng electrode address data VA.
Then, on receiving the "L" level of the Sync signal,
the sc~nn;ng electrode address data VA and image data
in the VRAM designated by the VA signal are read out
and transferred to the display panel 11. Then, one
increment is given to the 50-line counter 53S. If the
count is 49 at the time of the increment, the partial
rewriting routine is started, and if the count is not
49, the "L" level of the Sync signal is again awaited.
Up to now, the operation of a so-called one-field
scanning drive has been explained.
Then, when the count reaches 49, the partial
rewriting routine is started and operated in the
following manner.
The count of 49 means that the display data to
be subsequently sent are for a 49th-scanning electrode
in one field, whereby the partial rewriting routine is
started from terminal ~ shown in Figure 7. Further,
even while the partial rewriting routine is operated,
one field scanning drive is operated on the~display
panel, so that the time relation between the partial
rewriting routine and the one-field scanning drive is
shown by the notes of 49th LINE TRANSFER and 50th LINE
TRANSFER in Figure 7. The transfer in the 49th LINE
TRANSFER and 50th LINE TRANSFER refers to transfer of
133~3~27
--26--
sc;~nni ng electrode address data and image data from
VRAM 521 in the one-field scanning drive.
As shown by "2nd ADDRESS SWITCH, BA-
SELECTION", a flag memory address signal (FA) from the
400-line counter 533 is supplied to the flag memory
536, and according to 400 times of counting, 400 bits
of data in the flag memory 536 are read out. If a data
with a flat "1" (= "ON") is present among the data thus
read out, the partial rewriting routine is started
thereafter. If the flag is "0" (= "OFF"), the
operation proceeds to a terminal ~3, i.e., returns to
the whole display picture scAnn;ng drive. After the
completion of the partial rewriting routine, one
increment is given to the scanning counter 534, and
another RA signal is set to again perform a one-field
sc~nn;~g drive.
Herein, the flag "1" means that rewriting is
caused on a sc~nn;ng electrode shown by a flat memory
address (FA). In contrast thereto, no rewriting is
indicated by the flag "0". The operation from the
terminal (~) up to now is performed during the 49th-
line transfer.
Then, the operation in case where a bit with a
flag "1" is present, will now be explained. When the
50th line transfer is started on receiving Sync = "L",
the 400-line counter is first cleared (into "0"), one
bit is read out from the flag memory 536. The readout
133~427
-27-
is effected from the first sc~nning electrode. Here,
again the flag memory is checked whether "1" or "0".
If "0", one increment is given to the 400-line counter,
and another address signal (FA) is set for a subsequent
1-bit readout. At this time, when the count does not
reach 400 as a result of the increment, one bit is read
out from the flag memory 536. The operation up to now
is repeated until a bit with a flag "1" is encountered.
When a bit with a flag "1" is read out, the
operation of the 400-line counter 533 is interrupted,
the address of the flag "1" bit is retained. Under the
condition of the operation of the 400-line counter 533
being interrupted; the completion of one field ScAnn i ng
drive is waited for by awaiting a Sync signal at "L"
level.
On the other hand, the first address switch
531 is set to the position of BA-selection, and
subsequent to the one-field scanning drive, the flag
address held by the flag memory 536 is made the
scanning electrode address for the partial rewriting
scAnning and image data in VRAM designated by the
scAnn;ng electrode address are transferred. Further,
simultaneously with the transfer, the above-mentioned
operation after "400-LINE COUNTER ONE INCREMENT" is
performed.
The above operation with a flag "1" bit is
repeated 400 times. Then, at the 400 times of
1333~27
-28-
repetition, i.e., after evaluating the value due to the
increment, and then it is judged whether the 400 is
given by the number of scanning for the partial
rewriting sc~nning. When 400 is not reached, the
operation goes to a terminal ~ to return to the
partial rewriting routine, and when 400 is reached, the
operation goes to a terminal ~ so as to proceed to
the whole display picture scanning routine.
Next, the operation in the whole display
picture sc~nn;ng is explained.
Referring to Figure 8, the operation is
started from a terminal ~ , and the RA signal is
selected by the first address switch 531. Then, a Sync
signal at "L" level is awaited, and when it is
satisfied, the sc~n~;ng electrode address data defined
by the scanning counter 534 and the 50-line counter 535
and image data designated thereby in VRAM are
transferred. Then, one increment is given to the 50-
line counter 535. Then, the count given by the
increment is judged to be whether it has reached 50,
and if it is not 50, a subsequent transfer is
performed. If the counter is 50, the one-field
sc~nn;ng drive is judged to be completed and one
increment is given to the scanning counter 534 to set a
next field. Then, the count in the counter 534 is
judged whether it has reached 8. If it is not 8,
another one-field scanning drive is started from the
1333127
-29-
beginning of the next field. If the count in the
sr~nn;ng counter 534 is 8, one frame scanning
comprising 8-field sc~nn;ng drives is judged to be
completed, and the operation proceeds to a terminal
~ . Then, the whole display picture sc~nning routine
and the partial rewriting routine are repeated as shown
in Figure 6.
The above operation corresponds to the driving
of the display panel as follows. Thus, while the
display panel is not rewritten, the whole display
picture sc~nning drive is always repeated. Search for
image rewriting is effected for each one-field sc~nn;ng
drive. In case of rewriting, partial rewriting is
performed after the completion of one-field scanning
drive. The scanning drive in the partial rewriting is
performed according to a non-interlaced mode. When the
number of partial rewriting exceeds 400 times before a
subsequent one-field sc~nn;ng, the system is
automatically moved to one-field scanning drive
according to an interlaced scanning mode. The display
panel 11 is subjected to repetition of a series of
operations as described above based on image data from
the apparatus body.
As shown in Figures 6 - 8, while image data
are generated, the BA signal and the RA signal are only
temporarily selected by the first address switch 531,
and otherwise the ADR signal from the CPU 51 is
I333~7
-30-
selected. In other words, the data in VRAM 521 are in
a condition that the access thereto is-always possible
by the CPU 51.
Figure 9 is a flow chart showing another
partial rewriting routine used in the present
invention, and Figure 10 is a flow chart showing a
display operation including the partial rewriting. In
the operation, it is judged whether new data have came
from CPU, and if not, this operation is repeated. When
new data appear, the previous data in VRAM are
rewritten. Thus, the apparatus body 14 adds scAnn;ng
electrode address data to the image data from CPU and
transfer the sum to the control circuit 15.
On the other hand, the whole display scAnning
drive is executed at definite intervals. For this
purpose, the main program is interrupted on demand for
the whole display picture scanning drive, and the
apparatus body 14 executes the routine shown in Figure
10 at definite intervals according to the interruption
demand. In the operation shown in Figure 10, if the
partial rewriting is under operation, it is interrupted
to refuse new data from CPU. Then, image da-ta for the
whole picture are transferred to the control circuit
15. Then, a time until the subsequent whole display
picture scanning drive is set (to 1 second in this
embodiment). Then, new data from CPU are received.
The operation of the apparatus body 14 is
1333~27
defined in the above described r~nner to effect the
driving method according to the present invention.
Figures 11A and 118 show time charts for
showing the display operation principle according to
the present invention, wherein the first frame is a
period for the whole display picture scAnn;ng drive.
If rewriting data are generated during this period, the
apparatus body 14 prepares rewriting data (generates
scanning electrode address data and image data
serially) in the above described manner. Then, at the
beginning of the second frame, the partial rewriting is
started according to the routine shown in Figures 9 and
10. After the completion of the partial rewriting and
on reaching a prescribed definite time, the whole
display picture sc~nn;ng drive is resumed.
Herein, if the rewriting data does not span
the whole picture, i.e., in case of the number of
scAnn;ng electrodes for the partial scanning < the
number of sc~nn;~g electrodes constituting the whole
picture, the whole display picture scAnning drive is
started as soon as the partial rewriting is completed
and a definite time is reached as shown in Figure 11A.
On the other hand, in case of the number of
scanning for the partial rewriting > the number of
scanning electrodes constituting the whole picture
(e.g., 400 lines), the partial rewriting is interrupted
to proceed to the subsequent whole display picture
1333~27
-32-
sc~nn; ng drive when the number of scanning for the
partial rewriting exceeds 400. In this embodiment, the
whole display picture scanning drive cycle has been set
to 1 second.
D. Display Operation Example
Figure 12 is an example of a multi-window
picture display. The hole display picture comprises
respectively different pictures in various display
regions. A window 1 shows a picture of a categorized
total result expressed in a circle. A window 2 shows
the categorized total at the window 1 expressed in a
table. A window 3 shows the categorized total at the
window 1 expressed in a bar graph. A window 4 shows
characters relating to formation of sentences. The
back ground is formed in plain white.
Herein, the window 4 constitutes a picture in
operation and the other pictures are in a still picture
state. In other words, the window 4 is under
preparation of a sentence and in a motion picture
state. The motion picture state may specifically
include motions, such as scrolling; insertion, deletion
and copying of words and paragraphs; and regional
transfer. These motions generally require a quick
movement. More specific display operation examples are
given hereinbeloW-
First example: One character is additionally
displayed in an arbitrary row in the window 4.
~ 13~3`~27
--33--
A character font is assumed to be composed of
16x16 dots. The additional display of one character
corresponds to rewriting of 16 scAnning electrodes.
According to the routine shown in Figures S - 8, only
16 scAnning electrodes are rewritten as follows during
the whole display picture scanning. First of all,
search of the flag memory 536 is started from the 49th
line in a field in which one character is additionally
rewritten in VRAM 521 by CPU 51 and the search is
continued until 16 bits of flags "ON" are detected to
partially rewrite only 16 scanning electrodes after
completing the field scAnning drive under way. Then, a
subsequent field scAnn;ng drive is sequentially
effected from a leading scAnn;ng electrode. If one
horizontal scAnning time is assumed to be 250 llsec, the
time required for rewriting 16 lines is 16x250 llsec =
3.8 msec, so that a high-speed partial rewriting is
performed. The time requires for one field scanning
drive is 50x250 llsec = 12.5 msec, so that the time
required from the rewriting of VRAM 521 by CPU 51 until
the actual display of the additional character is 16.3
msec at the maximum, which corresponds to about 61 Hz
in terms of frequency and provides a very quick
response. As a result, a partial scanning drive of
scanning electrodes corresponding to a font given by a
cursor or mouse may be repeated cyclically for
different scanning electrodes to afford a moving
1333427
-
-34-
display by such a cursor or mouse at a very high speed.
Second example: The whole picture area is
scrolled according to the routine shown in Figures 5 -
The timing for switching from the whole
display picture sc~nning drive to the partial rewriting
scanning drive is the same as in the above-mentioned
first example. Herein, the partial rewriting is
replaced by a whole display picture rewriting scanning,
so that the number of sc~nn;ng electrodes to be scanned
for rewriting amounts to 400. Corresponding thereto,
in a first one frame, 400 sc~nn;ng electrodes are
scanned by the non-interlaced sc~nn;-ng mode to rewrite
the whole picture, and in a subsequently frame, the
whole picture is sc~nneA by the interlaced scanning
mode. Thus, the display picture is rewritten
alternately by the non-interlaced scanning mode and the
interlaced sc~nn;ng mode. Herein, image data
transferred from VRAM comprise newest image data even
in the interlaced sc~nn;ng mode. In this example, if
one horizontal sc~nn;ng time is assumed to be 250 ~sec,
the time required for rewriting one whole pi-cture is
400x250 ~sec = 100 msec, which corresponds to a frame
frequency of 10 Hz and provides a visually recognizable
level of scrolling.
Third example: A window 4 is subjected to
smooth scrolling according to the routine shown in
lJ33127
Figures 9 - 11.
It is assumed that the window 4 occupies 200
sc~nn;ng electrodes. The smooth scrolling display
corresponds to rewriting of 200 sc~nn;ng electrodes.
S The driving of 200 scanning electrodes during the whole
display picture scAnn;ng drive is effected as shown in
Figure 11. In the first frame, the whole display
picture sc~nn;ng drive is performed, and the partial
driving of 200 sc~nn;ng electrodes in 200x250 ~sec = 50
msec is performed from the beginning of the second
frame and repeated until the subsequent time for
initiation of the whole display picture sc~nn;ng drive.
E. Ferroelectric Liquid Crystal Device
Figure 13 schematically illustrates an
embodiment of a ferroelectric liquid crystal cell which
comprises a pair of electrode plates (glass substrates
coated with transparent electrodes) 131A and 131B and a
layer of ferroelectric liquid crystal having molecular
layers 132 disposed between and perpendicular to the
electrode plates. The ferroelectric liquid crystal
assumes chiral smectic C phase or H phase and is
disposed in a thickness (e.g., 0.5 - 5 micr~ns) thin
enough to release the helical structure inherent to the
chiral smectic phase.
When an electric field E (or -E) exceeding a
certain threshold is applied between the upper and
lower substrates 131A, 131B, liquid crystal molecules
2 7
-36-
133 are oriented to the electric field. A liquid
crystal molecule has an elongated shape and shows a
refractive anisotropy between the long axis and the
short axis. Therefore, if the cell is sandwiched
between a pair of cross nicol polarizers (not shown),
there is provided a liquid crystal modulation device.
When an electric field E exceeding a certain threshold
is applied, a liquid crystal molecules 133 is oriented
to a first orientation state 133A. Further, when a
reverse electric field -E is applied, the liquid
crystal molecule 133 is oriented to a second
orientation state 133B to change its molecular
direction. Further, the respective orientation states
are retained as far as an electric field E or -E
applied thereto does not exceed a certain threshold.
The ferroelectric liquid crystal device used
in this embodiment has an inclination of monostability
so that the first stable state 133A and second stable
state 133B are unsymmetrical. As a result, the liquid
crystal molecules tend to be oriented to either one of
the orientation states or to another stabler third
orientation state. The present invention is suitably
applied to such a ferroelectric liquid crystal device
having an inclination of monostability but can also be
applied to a ferroelectric liquid crystal device in an
alignment state showing semipermanent or permanent
bistability as disclosed by U.S. Patent No. 4,367,924
133~127
-37-
or a ferroelectric liquid crystal device in an
alignment state retaining a helical structure.
Figure 1 4A and 1 4B illustrate an embodiment of
the liquid crystal device according to the present
S invention. Figure 1 4A is a plan view of the embodiment
and Figure 1 4B is a sectional view taken along the line
A-A in Figure 1 4A.
A cell structure 140 shown in Figure 14
comprises a pair of substrates 1 41A and 141B made of
glass plates or plastic plates which are held with a
predetermined gap with spacers 144 and sealed with an
adhesive 146 to form a cell structure. On the
substrate 1 41A is further formed an electrode group
(e.g., an electrode group for applying scanning
15 voltages of a matrix electrode structure) comprising a
plurality of transparent electrodes 1 42A in a
predetermined pattern, e.g., of a stripe pattern. On
the substrate 141 B is formed another electrode group
(e.g., an electrode group for applying signal voltages
Of the matrix electrode structure) comprising a
plurality of transparent electrodes 1 42B intersecting
with the transparent electrodes 1 42A.
On the substrate 1 41B provided with such
transparent electrodes 1 42B may be further formed an
25 alignment control film 145 composed of an inorganic
insulating material such as silicon monoxide, silicon
dioxide, aluminum oxide, zirconia, magnesium fluoride,
1~3127
`
-38-
cerium oxide, cerium fluoride, silicon nitride, silicon
carbide, and boron nitride, or an organic insulating
material such as polyvinyl alcohol, polyimide,
polyamide-imide, polyester-imide, polyparaxylylene,
polyester, polycarbonate, polyvinyl acetal, polyvinyl
chloride, polyamide, polystyrene, cellulose resin,
melamine resin, urea resin and acrylic resin.
The alignment control film 145 may be formed
by first forming a film of an inorganic insulating
material or an organic insulating material as described
above and then rubbing the surface thereof in one
direction with velvet, cloth, paper, etc.
In another preferred embodiment according to
the present invention, the alignment control film 145
may be formed as a film of an inorganic insulating
material such as SiO or SiO2 on the substrate 141B by
the oblique or tilt vapor deposition.
In another embodiment, the surface of the
substrate 141B of glass or plastic per se or a film of
the above-mentioned inorganic material or organic
material formed on the substrate 141B is subjected to
oblique etching to provide the surface with an
alignment control effect.
It is preferred that the alignment control
film 145 also functions as an insulating film. For
this purpose, the alignment control film may preferably
have a thickness in the range of 100 ~ to 1 micron,
1333427
especially 500 to 5000 A. The insulating film also has
a function of preventing the occurrence of an electric
current which is generally caused due to minor
quantities of impurities contained in the liquid
5 crystal layer 143, whereby deterioration of the liquid
crystal compounds is prevented even on repeating
operations.
As the ferroelectric liquid crystal 143, a
liquid crystal compound or composition as disclosed in
U.S. Patent Nos. 4561726, 4614609, 4589996, 4592858,
4596667, 4613209, etc., may be used.
The device shown in Figures 1 4A and 1 4B
further comprises polarizers 143 and 148 having
polarizing axes crossing each other, preferably at 90
15 degrees.
As described above, according to the present
invention, a partial rewriting scanning drive and a
whole display picture scanning drive are compatible
realized, and further a partial motion picture at a low
20 frame frequency can be effected at a high speed while a
still picture display is stably effected by using a
ferroelectric liquid crystal material having a strong
inclination of monostability.
