Note : Les descriptions sont présentées dans la langue officielle dans laquelle elles ont été soumises.
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AN INPUT/OUTPUT MODULE
WITHIN A PROGRAMMABLE CONTROLLER
WITH DISTRIBUTED PROGR~M CONTROL
BACKGROUND OF THE INVENTION
The present invention relates to an input/output
(I/O) module with distributed progra~ control, which is
connected, via at lea~t one system bus line, to at least
one central processing unit o~ a programmably controlled
apparatus. In particular, the present invention relates
to storing instruction lists in the input/output module
for the various devices associated with the module so as
to minimiæe interruption of the central processing unit.
The inventisn further relates to advantageous applications
of the I/O module~
Generally a large number of I/O modules are required
in programmably controlled apparatuses, in particular in
connection with programmable controllers for controlling
~15 and regulating machines:and technical processes. These
I/O modules make possible the exchange o~ measuring,
control, and regulating signals ~"MSR~signals"~ between
the programmable controller and the object to be guided.
Usually these MSR-signals are pres nt in v~ry large
quantities.
Fig. 1 illustratPs, in block diagram form, an example
o~ this type of programmably controlled apparatus. An
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important element is a primary central processing unit, 1,
which communicates with additional elements via at least
one system bus SB which can include a plurality of signal
lines. Example~ of types of these additional elements are
illustrated in Fig. 1 as a coordinating module 2, a mass
storage unit 3, a communications processor 4 to link the
programmably controlled apparatus to, for example, an
external bus 5 or external instruments 6 such as printers,
and an interface module 7 to link expansion units 8 to the
system bus SB. In addition, a programming unit 9 can be
provided to control the central processing unit 1,
preferably togather with an interchangeable storage module
10, individual user applications, can be loaded preferably
into the central processing unit 1 of the programmably
controlled apparatus.
Furthermore, this type of apparatus generally has
access to a large number of I/0 moduleis 11 which, while
forming a processing interface PS, make possible
communications between the programmably controlled
apparatus and the object to be influenced, e.g. a machine
or a ~echnical process. For example, a digital input
module 12, a digital output module 13, an analog value
input module 14, an analog value output module 15 and a
so~called intelligent I/0 module 16 which are represented
in Fig. 1 are such types of I/0 modules 11.
Intelligent I/0 modules usually include a large
number of devices having preerably the same basic logic
function for inputting and/or processing external signals.
A pre-processing of signals can thereby be possible in
that for each device in the framework of this basic logic
unction, it is possible to programmably preselect special
modes of operation. For this type of operating mode entry
or "mode setting", control word~ which are directly
preselected by the primary central pxocessing unit 1 for
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the respective I/O module can act on the device level. In
this manner it is possible to adapt each device to the I/O
modula by means of setting its cperating mode, depending
on the processing application of the device which is
connected to this I/O module, such that the result
variables at the output of the respective device of tha
module can be further processed in the primary central
processing unit without any or with only a few
intermediate processing steps. Using these kinds of
control words on the device level, the individual devices
of an I/O module can only be influenced separately from
each othsr. All devices make their result values
available to the central processing unit in parallel to,
and independently from, each other~ A linkage o~ several
result values of individual modular devices in this case
is only possible when superordinated within the central
processing unit.
In an additional form of signal pre-processing at the
I/O module, individual instruction words at the device
level are also directly entered by the primary central
processing unit into the I/O module, preferably while
being interrupt driven and pref~rably in conjunction with
a main user program. These instruction words are usually
proc~ssed at the module by means of a separate,
decentralized processing unit. For example, the
instructions may make it possible to have simultaneous
acceas to several devices, or to combine the result values
of several devices into ona total result value. This type
of signal pre-processing at the I/O module level reduces
the processing xequirements at the central processing unit
level and also contributes to an overall faster execution
of instructions because the execution o~ instructions at
the I/O module frequenkl~ can take place much faster in
real time than within the primary central processing unit.
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Modern ItO modules frequently have access to a large
number of parallel devices with preferably the same basic
logic function. Furthermore, it is gensrally desired t9
shift increasingly more operations from the central
processing unit and the resident user program to generally
faster operating I/O modules by enlarging the respective
supply of possible control words at the device level and
the supply of instruction words at the module level.
However, this endeavor is limited by the data transfer
times which are subject to interrupts when control words,
instruction words and result values are being exchanged
between the central processing unit and the I/O modules or
their devices. Each and every readout of a control or
instruction word from the primary central processing unit
or the entry of a result or intermediate result value by
one o~ the intelligent ItO modules results in a break due
to interruptions o~ the primary user program within the
primary central processing unit. Thus, the data transfer
times are limited. Furthermore, time losses arise in this
manner due to the requirement for the orderly interruption
or further processing o~ the main user program. A
preprocessing of signals on the I/O module level thus only
causes an increase of processing speed of the entire
automation system so long as the interrupt load of the
entire system does not become too great through the
exchange of individual control words, instruction words
and result values. Due to the constantly growing supply
of control and instruction words, though, which are
unnoticed by the user, a state is more frequently reached
at which the time savings from the rapid control word and
instruction word processing at the module level are lost
by the time loss resulting from the thus required
interrupt communication, so that as a result, the entire
system is more obstructed than relieved.
SUMMARY OF THE INVENTION
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The present invention overcomes the above-described
disadvantages of intelli~ent I/0 modules, so that even in
the case of a large supply of control or instruction words
at the equipment or module level, an increase of the
overall system processing speed can be achieved which is
parallel to the shift of parts of the primary user program
to the respective I/0 module.
In order to achieve these results, the present
invention provides an I/0 module with distributed program
control which includes a plurality of devices which may
have the same basic logic functions and which enter and/or
process a plurality of external signals wherPby at least
the one output of each device serves as an interrupt
source. The module also includes a main memory having a
plurality of memory areas, at least one memory area being
associated with each o~ the devices. The corresponding
memory area stores an instruction list which corresponds
to the interrupt source of the device and includes at
least one instruction word at the modular level or one
control word at the device level for distributed program
control. ~he module also includes a processing unit,
which, when an interrupt source of a device is activated,
signals that activity to a primary central processing unit
and prepares a means of identifying the interrupt.
Furthermore, the processing unit also internally
identifies the interrupt and executes in parallel to the
identification, the instruction word in the instruction
list corresponding to the activated interrupt source.
Furthermore, according to an embodiment of the
present invention, the memory area corresponding to each
device further includes a register area that comprises
registers storing set point, intermediate and result
values.
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Furthermore, according to an embodiment of the
present invention, the register area further comprises an
operation mode register for each device whereby the
operating mode of the respective device is programmably
adjustable by means of a control word at the device level.
According to yet a further embodiment of the present
invention, the module may further includ2 a control word
register into which instruction words at the modular level
or control words at the device level are entered by the
primary central processing unit in conjunction with a main
user program found in the primary central processing unit
when an interrupt source becomes active. The words of the
control word register are processed by the processing unit
either in parallel to the instructions in the instruction
list or with priority over the instructions in the
instruction list.
Th~ module may further comprise a dual port RAM that
is accessible by the processing unit via a modular bus
line and is also accessible by the primary central
processing unit via a system bus line~ The dual port RAM
stores the identical contents of one of the memory areas
for each device and the contents of the dual port RAM are
updated upon occurrence of changes in the main memory
r~sulting from action by the primary central processing
unit.
The module may fur~her include additional registers
which are present in the processing unit, whereby the dual
port RAM coordinates interrupts and directly transfers
instructions or control words from the primary central
processing unit to the module by accessing the additional
registers.
Advantageous specific embodiments and applications
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of the invention are further specified below.
BRI~F DESCRIPTION OF THE DRAWINGS
The present invention is explained in greater detail
below.with reference to the drawing fiqures in which:
Fig. 1 illustrates a block diagram representation of
a known programmably controlled apparatus serving in
particular as an automation system with a known
intelligent I/O module as the processing interface;
Fig. 2 illustrates a structural diagram of an I/0
module with distributed program control according to an
embodiment of the present invention;
Fig. 3 illustrates a time sequance chart for
processing an interrupt generated by a modular device
according to an embodiment of the present invention in
comparison to a known processing method; and
Fig. 4 illustrates a channel of a counter module as
an example of a device of an I/O module with distributed
program control according an embodiment of the present
invention.
2 O DETAI~ED DESCRIPTION OF THE INVENTION
In Fig. 2, an I/O module 16 with distributed program
control is represented in overview as a structural
diagramO This module includes a group, PBM, o~ a
plurality of modular devices Bl...Bn having preferably the
same basic logic function in order to enter and/or process
external processing signals P1, P2,--~ PN. The devices of
group PBM, thereby act as a processing interface PS. The
devices communicate via an internal modular busline BB
with a processing unit VE which is internal to the module
according to a first specific embodiment of the invention.
This processing unit VE includes at least one modular
central processing unit 20, which works together with a
modular main memory 21 which may be a random acc~ss memory
~RAM) and an interrupt rontroller 22. Furthermore, a
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control word register SWR, 23 can also be provided which
is preferably a portion of the modular main memory RAM 21.
In the devices Bl...Bn, some variables which are
accessible externally also act as interrupt source~ at the
inputs and outputs. When one o~ these signals is
activated, or when a particular signal state appears, e.g.
a zero crossing, an appropriat~ interrupt is triggered in
the primary central processing unit l; that is, there is
a temporary interruption of the actual user program being
processed at the primary central processing unit. In Fig.
2, in the case of the devices B1, B2...Bn, e.g., the
variables IBll...IBlk, IB21...IB2k,...l IBnl...IBnk are
represented as being provided on interrupt source lines
IQ. These interrupt variables on source lines IQ are e.g.
consolidated in interrupt controller 22 for further
processing; the interrupt controller 22 is preferably
accom~odated in the processing unit VE. The activation of
one of these interrupt sources on one of lines IQ is
preferably signalled to the central processing unit 1 via
the interrupt controller 22, partic~larly via a group
interrupt line SA.
According to the present invention, for each of the
devices Bl...Bn, a speci~ic range R~MBl... RAMBn o~ the
modular main memory RAM 21 has been reserved. Each of
these specific ranges contains a number of instruction
lists, each list corresponding to the number of interrupt
sources of the respective device. Thus, for the device
B1, the memory area RAMB1 contains the instruction lists
BBll...Blk which correspond to the interrupt sources
IBll...IBlk o~ device B1 respectively. Accordingly, the
memory area RAMBn contains the instruction lists
BBnl.O.BBnk which correspond to the interrupt sources
IBnl...IBnk respectively for the device Bn. According to
the presen~ invention, the instruction lists serve to
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store at least one instruction or control word. However,
a large number of instruction words at the module l~vel or
control words at the device level for distributed program
control can be stored in each list. The user can thus
assign an individual sequence of instruction and control
words to each of the interrupt sources IB11...IBnk of the
respective I/0 module 16 parallel to the user program in
the primary central processing unit 1. These instruction
and control word sequences are processed when the
corresponding interrupt source is activated by the modular
processor CPU 20 of the modular processing unit VE. The
instruction words affect the level of the entire module,
i.e., all devices Bi...Bn, one or several arbitrary
devices. In particular, reading, writing or controlling
lS operations can be carried out while being program
controlled by means of each instruction list depending on
the application, at one or several devices o~ the I/0
module.
When activating one of ~he interrupt sources along
the interrupt source line IQ associated with the device Bn
of the I/0 module 16, the primary central processing unit
1 is signalled regarding the activity of an interrupt
source via the processing unit VE, and means for
identifying the interrupt are prepared. These means can
e.g. include an interrupt data register IIR, which in turn
is preferably mounted in the main memory RAM 21 of the I~0
module and is preferably loaded with an interrupt
identification code via the interrupt controller, 22, the
interrupt controller control line 23 which runs to the
module processor CPU 20, and finally from the modular
processor CPU i~self. The information stored within the
register IIR serves both the module processor CPU 20 as
well as the primary central processing unit 1 in the
program controlled apparatus for identifying the current
active interrupt source. Thus, as a result, on the one
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hand the module processor CPU 20 causes the instruction
list BBnk belonging to the respective active interrupt
source to ~e executed in the memory area RAMBn of the
respective device Bn.
Parallel to this distributed processing of the
instruction list, an interrupt of the primary central
processing unit 1 is triggered preferably via the qroup
interrupt line SA due to the signalling of activity of a
device interrupt source. This primary central processing
unit 1 continues to process the main user program until a
certain point in the program i5 reached; only then can
this program be interrupted in an orderly fashion. The
interrupt identification in the primary central processing
unit 1 also joins in this activity in particular by
reading the contents of the interrupt data register II~ of
the I/O module 16 which is signalling the interrupt. This
has the goal of identifying the instruction list or
subroutine corresponding to the respective interrupt in
the main user program in order, for example, to retrieve
the processing result which is expected because of the
parallel processing o~ the instruction list.
Ons o~ the particular advantages of the present
invention is that in the time reguired by the primary
central processing unit 1 to interrupt the user program in
an ord~rly manner after the appearance of a group
interrupt alarm which signals the activity of an interrupt
source o~ a device on an I/O module and to identify the
reported interrupt, the instruction list corresponding to
the respective interrupt has, as a rule, already been
processed in the main memory RAM 21 of the respective ItO
module, and the processing result is held ready for the
primary central processing unit 1. The instruction lists
can be much more rapidly processed in the main memory of
the respective I/O module than i~ they were stored in the
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user program of the primary central processing unit 1.
As set forth above in the known case, whereby the
instruction words which correspond to an interrupt source
of a device on an I/0 module are stored in the main user
program of the primary central processing unit, an
increase of the processing speed of the overall system can
be reached only to a certain degree. In this known case,
when an interrupt source is active, the appropriate
instruction word(s) are transferred only individually to
lo the I/0 module via interrupt, then are processed at the
I/0 module, and the processing result then has to be
return~d respectively via interrupt to the central
processing unit. An increase of the computing capacity in
this case can only be achieved insofar as the interrupt
time losses during the exchange of the instruction word
and the result value between the primary central
processing unit and I/0 module are not gr~ater than the
time gains achieved due to the higher processing speed of
the instruction words at the modular level. Thus, an
increase of computing capacity only occurs if direct
transf~rs of individual instruction words appear at I/o
modules with little or modçrate frequency. With the
increase of instruction words, this time savings - usually
not noticed by the user - turns into a time loss since the
lost time prevails during the organization of the many
interr~pts of the primary central processing unit. In the
known system, this can only be avoided by restricting the
supply of instruction words, thereby forcing the user to
perfor~ the majo~ity of signal processing operations in
the primary central processing unit itself.
In contrast, in the present invention, each increase
in the ~hifting of instruction and control words from the
user program in the central processing unit to instruction
lists of the respective I/0 module results in an increase
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of the savings of processing time o~ the entire automation
system. The reason for this lies in that the number of
the interrupts which burden the central processing unit
does not increase with the num~er of instruction words
which are contained in the respective instruction list
BBnk. Rather, the number of interruptions generally
remains constant and usually has the value 1, since only
one single interrupt of the main user program is required
for one instruction list from the main memory R~M of an
I/0 module in order to retrieve the result.
Even in the case that only one single instruction
word is stored in this type of instruction list BBnk, the
I/0 module with distributed program control according to
the present invention makes possible a considerably faster
instruction word processing than if the same instruction
word first had to be loaded into the I/0 module by the
primary central processing unit 1 when an interrupt source
became active. This is more closely explained further
below in connection with Fig. 3.
According to a further specific embodiment of the
invention which is represented in Fig. 2, the main memory
area RAMB1~..RAMBn for each device Bl...Bn furthermore
preferably includes a register area BR1...BRn with
registers. These registers serve as intermediate storage
of data which exclusively concerns the respective device,
in particular they store setpoint values, intermediate
values, and result values. Thus, for example, in Fig. 2
respectively one setpoint value register B1-VWR...Bn-VWR,
one result value register B1-ER...Bn-ER, and one interrupt
alarm value register B1-AWR~..Bn-AWR are provided in the
main memory RAM for each device B1...Bn. The result of
processing an instruction list according to the present
invention can, for example, be stored in the result value
register Bn-ER of the corresponding register area BRn, or
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also for example in the setpoint value register or
interrupt alarm value register of one or several register
areas o~ other devices of the I/0 module which correspond
to other interrupt sources.
In Fig. 3, three processin~ levels in the
programmably controlled apparatus are symbolically
represented as E1, E2 and E3. The bottom level El thereby
refers to t~e individual devices of the I/0 module; the
middle level E2 refers to the modular (or internal)
processor CPU of the I/0 module; and, finally, the top
level E3 re~ers to the primary central processing unit 1
of the programmably controlled apparatus.
In the case o the time sequence chart which is
represented in Fig. 3, it is first presumed that at the
instant tl, the interrupt source IBnk of the device Bn is
activated at the device level E1. A~ result of this,
various operations are triggered at the middle level E2
and the top level E3. Thus, the identification of the
interrupt source first takes place at the middl~ level E2
by means of the modular processor CPU 20. For this
purpose, e.g., it can be checked with the aid of an
"interrupt enable mask IFM", which has already been shown
in a corresponding register in Fig. 2, whether the
respective interrupt has been released or blocked as a
~unction of the user. As an example, the time interval T1
has been entered for this purpose in Fig. 3. If the
checking of IFM results in the release of the active
interrupt source, then a group interrupt alarm SA for the
primary central processing unit joins in at the end of T1
at the instant t2. As a result of this signalling of the
activity of an interrupt source of a device of an I/0
module to the top level E3, the running user program
continues to be processed only for the duration T5 until
a suitable or orderly point in the program for
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interruption has been reached and then processing is
subsequently interrupted in an orderly manner.
Parallel to this interruption process, the
identification of the active interrupt source also follows
after time t2 within the middle level E20 This takes
place in particular by evaluating the interrupt data
register IIR and by determining the instruction list
corresponding to the interrupt source in the main memory
RAM. Time interval T2 in Fig. 3 indicates the time
interval for the processing of the interrupt data register
IIR and the subsequently setting o~ an instruction counter
BZ of the modular processor CPU 20 at the initial addreiss
of the identified instruction list. After time interval
T2, the identified instruction list BBnk is processed by
the modular processor CPU 20 during time interval T3. The
processing result is stored, for example, in the
corresponding result value register Bn-ER in the register
area BRn of the respective device. The result value thus
is available to the primary central processing unit
starting from the instant t3.
Typically, the central processing unit is generally
not yet ready to read the contents of the result value
register 8n-ER at time t3. Rather, in level E3~ a time
interval T6 for identifying the interrupt follows the time
interval T5 which is required for initiating the
interrupt. For the purpose of identifying the interrupt,
the contents of the interrupt data register IIR are read
and evaluated, for example, by the I/0 modules which
signal the activity of an interrupt source. The
identification of the interrupt is concluded at the end
of the time intierval T6 at time t4, so that only at that
tim~ can the contents of the respective result value
register be transferred from the level E2 to the level E3.
Thus, despite the fact that during the time interval T3 a
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large number of instxuction and control words of the
instruction list BBnk are generally being processed, there
is a waiting time T4 between the availability of the
processing result at the instant t3 and the transfer of
5 the result into the slower top level E3 at the instant t4
due to the considerably high~r processing speed at the
middle level E2.
Furthermore, Fig. 3 illustrates by a dash-dotted line
the result if the processing were performed in the known
manner which has been described above without the use of
the invention; i~e., with the omission of the parallel
processing at the middle level E2 during the time
intervals T2, T3 until the result instant t3. In this
connection, only after an orderly interruption of the user
program in the central processing unit during the time
interval T5 and after identifying the respective interrupt
during the time interv~1 T6 at the instant t4 is there the
possibility o~ individually transferring the respective
desired instruction word from the top level E3 ç.g. to a
control word register SWR of the processing unit VE of the
respective I/0 module into the middle level E2. During
the subse~uent time interval T7, the contents of this
control word register SWR, which itself is preferably a
component of the main memory R~M of the processing unit VE
on the respective I/0 module, are processed by the
corresponding modular processor CPU 20, and the processing
result in turn is stored in the result value register Bn-
ER which corresponds to the active interrupt source at
time T5. The transfer of the result from the middle level
E2 to the top level E3 usually again takes place in an
interrupt-driven manner, since during the interval between
the delivery of the instruction word at time t4 to ths
modular processing unit and the availability of the
proces~ing result at time t5, the central processing unit
has already resumed processing the user program which was
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interrupted during intervals T5 and T6 between the times
t2 and t4.
Thus, following the appearance of a group interrupt
alarm SA at time t5, another time interval T8 i~ then
required in order to interrupt the main user program in an
orderly manner. Furthermore, the time interval ~9 is
required during the course of identifying the interrupt in
order ~o recognize from which I/O module what result value
should be trans~erred where. The transfer of this result
value from the level E2 to the level ~3 is thus possible
at time t6 at the earliest.
According to the present inventionl it is possible to
store instruction words at the modular level as well as
control words at the device level in instruction lists and
then to jointly process them when the corresponding
interrupt source is active~ The control words make it
possible to programmably set the operating mode of each
device Bn on the I/0 module within the scope of the
general basic logic function depPnding on the application.
For this purpose, according to a further specific
embodiment, it is advantageous according to the
representation of Fig. 2 to provide at least one
additional register ("mode register") Bn-BMR in the
register area BRn which corresponds to each device within
the memory area RAMBn. Thus, in Fig. 2, the mode
registers B1-BMR...Bn-BMR are present for the devices
Bl...Bn in the register areas BRl...BRn. The contents of
these mode registers can on the one hand be changed in the
primary central processing unit 1 as a function of the
user program and be loaded into the respective device in
order to switch the operating mode. However, it is also
possible that these operations can be triggered by one or
several control words at the device level, which wor~s are
stored in distribution in one or several of the
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instruction lists BBll...BBnk in the ~ain memory RAM 21 ofthe processing unit VE of the respective I/0 module 16.
According to a further embodiment of the present
invention, in addition to distributed program control by
processing instruction lists which are stored in the main
memory RAM, the I/O module has acc~ss to the possibility
of processing, in a known manner, an instruction word or
control word which corresponds to an interrupt source and
is made directly available due to the activity of said
interrupt source by means of the primary central
processing unit. These types of singular instruction or
command words are preferably transferred directly into a
control word register SWR o~ the processing unit V~ of the
I/O module in coordination with the user program there,
particularly after an interrupt has been signalled by the
primary central processing unit, and subsequently is
processed by the modular processor CPU parallel to or
preferably before the instruction and control words in the
instruction lists BBll...BBnk. Depending on the
respective application cask, these types of directly
entered instruction or control words can have a higher
processing priority reserved for them than those words
which are stored in the separate instruction lists.
However, there is also the possibility that the
instruction words of an interrupt source, which are stored
in the corresponding instruction list within the modular
main memory RAM, or the individual instruction words,
which are directly entered by the user program of the
central processing unit into the modular processing unit
VE, are to be treated equally regarding their processing
priority so that they are processed strictly sequentially
by the order of their appearance. Finally, in order to
avoid a processing conflict between the instruction words
of an instruction list and those instruction words which
are directly entered by the primary central processing
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unit, there is, in isolated cases, also the possibility of
not entering any instruction or control words into the
respective instruction list and of being satisfied with
the direct entry of individual words by the central
processing unit, which requires more computing time due to
the increased interrupt load.
The invention thus has the additional advantage that,
without disturbing the distributed program control of the
IIO module by way of the instruction lists according to
the present invention, use of the known signal
preprocessing method can continue either independently
from or parallel to the distributed program control by
directly entering individual instruction or control words
as needed.
In a further embodiment of the present invention, the
instruction and control words in the instruction lists
which correspond to the respective interrupt source are
able to be entered by means of the primary central
processing unit preferably in conjunction with an
initialization routine found there. For the user there i5
thus the possibility, according to the representation of
Fig. 1, of both entering the parts of the user program,
which are stored and processed with priority in the
primary central processing unit 1, as well as the parts
which are designated for distributed program control of
the individual I/O modules, for example, by means of the
programming unit 9.
According to a further embodiment of the present
invention, a dual port R~M (DP-R~M~ is additio~ally
provided on the I/0 module. This type of memory DP-RAM
has already been represented in the structural diagram of
Fiy. 2 and has access to the same instruction lists or
register areas as the main memory RAM 21 of the processing
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unit VE. It is connected at least to the central
processing unit 1 via the system busline SB and, also at
least to the processing unit VE and the modular devices
PBM internal to the module via the modular busline BB.
This type of a dual port R~ DP-RAM makes possible at
least both a writing as well as a reading access to the
processing unit VE on the I/0 module 16 and to the primary
central processing unit 1. Furthermore, it is possible
that at least the register areas BR1...BRn in the main
memory RAM and in the port memory DP-RAM can be directly
~pdated by the corresponding modular devices Bl...Bn. The
port memory makes possible a decoupling of the modular
main memory RAM from the primary central processing unit
1. The modular processor CPU can thus access the register
areas BRl...BRn which correspond to the respective devices
and the instruction lists BBll...BBnk at the main m~mory
RAM, which correspond to the respective interrupt source
for processing in particular, without having a conflict
arise should there be a case of a coincidentally
simultaneous access by the primary central processing
unit~ This type of access conflict can consist in that,
for example, while the primary central processing unit is
writing to a memory area and the modular processing unit
is simultaneously reading the contents of that very same
memory area, this modular processing unit alxeady accepts
not only part of the newly entered data, bu* also part of
the originally contained data. In th~ event that the dual
port RAM i5 not present, these types of conflicts would
have to be prevented e.g. by means of coordinating
routines which regulate the access of various devices to
the same memory. However, these types of routines impair
the overall processing speed and are dispensable when a
dual port RAM i5 present. Thus, for example, the
processing results which ar~ generated due to the
processing of the instruction words within the instruction
lists are preferably entered for security in the
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corresponding result value register Bl-ER...Bn-ER of the
modular main memory RAM and o~ the dual port m~mory DP-
RAM by the respective devices themselves. Furthermore, it
is particularly possible to copy the contents of the dual
port RAM completely into the modular main memory RAM,
preferably in conjunction with a centralized
initialization program, when changes within the
instruction lists which are caused by the central
processing unit appear.
Finally, the dual port memory RAM has access to
additional registers which are correspondingly present in
the processing unit VE. For example, these registers
comprise the interrupt data register IIR and the interrupt
enable mask IFM which are required for coordinating the
interrupt. Other registers which ar~ correspondingly
present in the port memory DP RAM preferably refer to the
direct trans~er of instruction words ~rom the central
processing unit to the I/O module and include the control
word register SWR.
The I/O module according to the invention is
particularly suited for use in a programmably controlled
programmable controller for the real time processing of
processing signals. There, they can serve, for example,
as a control module, a binary value input and/or output
module, an analog value input, processing, and/or output
module, a counter module or trigger module for processing
equipment.
A channel of a counter module which is de~igned
according to the present invention is shown in Fig. 4 as
an example of a device for an I/O module with distributed
program control. For example, the progra~mable counter
channel PZXl as device B1 has access to a pulse input IE,
a port input TE, a data input DE and a counter output ZA.
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The pulses to be counted ara conveyed from the processor
to the pulse input IE via the processing interfac~ P1. A
release or blocking of the counter channel, which is
in~luenced by the processor, is equally possible via the
port input TE. A large amount of data is supplied to the
programmable counter channel PZK1 by the processing unit
VE via the data input DE by way of the modular busline BB.
This data includes control words on the device level with
which the respectively desired operating mode of the
counter channel, for example, of an up or down counter,
can be programmably adjusted by means of the current
contents of the mode register B1-BMR. Furthermore, the
current contents of, for example, the setpoint register
B1-VWR and of the interrupt alarm value register B1-AWR
can be entered into the counter channel via the data input
DE. Finally, it is possible to programmably activate or
block the counter channel by means o~ instruction words at
the modular level. If the counter level finally reaches
a desired setpoint value during the counting process, then
this is signalled at the counter output ZA.
In the example of Fig. 4, the signals at port input
TE and at counter output ZA simultaneously serve as
interrupt sources IB11, IB12 These interrupt sources for
interrupt source lines IQ are, for example, supplied to
the interrupt controller IK of the modular processing unit
VE for monitoring purposes according to the representation
of Fig. 2.
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