Note : Les descriptions sont présentées dans la langue officielle dans laquelle elles ont été soumises.
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M~l'HOD AND CIRCUIT FOR 1~ S~ G TRANSMISSION PATHS
Field of the Invention
The invention relates to a circuit and method of
testing and more specifically to a method and circuit for
generating pseudo random test data for verifying the
integrity of transmission paths.
Bac~4~ of the Invention
In the past, the integrity of transmission paths
has usually been verified using a signature test. A
signature comprised of a predetermined pattern of data bits
is transmitted through a tr~n~ ission path under test and is
compared to the data received at a receiver~ The
transmission path under test is considered to be fault-free
if the received data matches the transmitted data.
More recently, transmission circuits have become
increasingly more complex with a requirement for data to be
transmitted at higher rates. As bit rates increase, the need
for the testing of transmission circuits becomes more
essential since a transmission circuit which performs
adequately at low frequencies may not perform adequately at
much hiqher frequencies and may cause data to become corrupt.
Transmission circuits capable of transmitting data at high
frequencies often have many closely inter-spaced data lines
forming a data bus. It is not uncommon for noise to be
generated on the bus as data bits carried on the data bus are
changing binary values at very high frequencies. This noise
is often the cause of data corruption, resulting in the loss
of integrity of a transmitted data message. A static data
test such as a signature test may not detect data corruption
in a circuit capable of transmitting large amounts of data at
very high frequencies. Thus, it is desirable to provi~e test
data which is random or pseudo random and which covers a
myriad of possible hit combinations thereby to provide
varying stimuli for a transmission circuit under test.
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Pseudo random data is compr~sed of many varying patterns
which, while appearing random, are periodically based.
In the past, large memory devices have been used to
S store test data; however, memory devices capable of storing
an adequate amount of test data are physically large and may
not be practically incorporated on an integrated circuit that
also includes the circuit under test.
It is therefore an object of the invention to
provide an improved method and circuit for testing the
integrity of a transmission path.
It is also an object of the invention to provide
testing circuitry that may be co-located on an integrated
circuit also containing at least a portion of the circuit to
be tested.
It is a further object of the invention to provide
testing circuitry that is adapted to exercise the circuit
under test at a data rate similar to that normally sent
through the circuit under test.
Summary of the Invention
The circuit of the invention is particularly
well-suited to test the integrity of transmission paths such
as exist through a switching network module. A circuit
adapted to generate pseudo random data may be connected to
apply the generated data to the input ports of the module
whereas another circuit is responsive to the data at the
output ports of the module for synchronizing to the generated
data thereby allowing a continuous comparison between the
generated data and the data at the output ports of the
module. A mismatch of the compared data indicates a problem
associated with the particular transmission path being
tested.
In accordance with the invention there is provided
a method of testin~ a circuit comprising a plurality of
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transmission paths having x input terminals for receiving
series of input test patterns and having corresponding y
output terminals, the method comprising the steps of:
in a first generator for connection to the input
terminals, generating a first series of 2"pseudo random test
patterns, each pattern having n bits;
applying to the x input terminals at least a
portion of each of the generated first series of patterns for
transmission to the corresponding y output terminals;
in a second pseudo random test pattern generator at
the output of the circuit, generating a second series of
patterns by beginning the second series with an n bit seed
value corresponding to the nth test pattern generated by the
first generator whereby the test patterns subsequently
generated by the second generator correspond to the pseudo
random test patterns generated by the first generator and are
in synchronism with the test patterns on the output
tel ; n~ 1 S; and
c -ring each of the test patterns on the output
te~ inAls of the circuit with the corresponding test pattern
from the second generator and generating a signal in the
event of a mismatch.
From a different aspect, the invention also
provides a circuit for testing tr~n~ lssion paths. The
circuit comprises means for generating a first periodic
series of 2npseudo random test input patterns, each pattern
having n-bits for transmission through the transmission
paths; means for generating a second periodic series of 2"
patterns, the second series corresponding to the first
generated series, wherein the second series is generated
after the second series qeneration means is provided with an
n-bit starting seed value corresponding to an output pattern
transmitted through the transmission pa'hs; the provision of
the seed value corresponding to a synchronizing mode; the
subsequent generation of the second series corresponding to a
free-running mode; control means for selectively switching
the means for generating the second series from the
synchronizing mode to the free running mode; and comparator
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means for comparing e~ch pattern in the second series with a
corresponding output pattern from a series of output patterns
transmitted through the transmission paths for determining
the integrity of a data transmission.
The invention thus provides a simple and economical
circuit and method of testing the integrity of a transmission
path under conditions approximating normal operating
conditions. Furthermore, the circuit of the invention may be
practically implemented as an integrated circuit either by
itself or with other circuitry such as a plurality of
transmission paths that may periodically require to be
exercised. To that end, the circuit of the invention may
also comprise circuit means for switchably coupling it to
transmission paths under control signals such as from a
processor.
Detailed DescriDtion
An embodiment of the invention will be described
with reference to the drawings in which:
Figure 1 is a blocK diagram of a test circuit in
accordance with the invention; and
Figure 2 is a schematic block diagram of a portion
of the test circuit shown in Figure 1.
IA Figures 1 and 2, a linear feedback shift
register (LFSR) 5 for generating pseudo random test data is
shown comprising a conventional shift register 10 coupled to
an exclusi~e-or gate 13. A multiplexer circuit 15 is adapted
to selectively connect the input ports of a circuit under
test 20 via a data bus 14 or to a data inp~t bus 17 under
control of signals 31 from control circuit 30. In more
detail, Figure 2 shows the LFSR S comprised of a 15-bit shift
register 10 and an exclusive-or gate 13. The first 10 stages
3s of the 15-bit shift register correspond to bit positions 1 to
10 and provide a 10 bit parallel output stream of pseudo
random test data on data bus 14. The exclusive-or gate 13 is
connected to receive the values stored in two locations
(e.g., 14th and 15th bit positions) of the 15-bit shift
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register and generates an exclusive-or feedback signal which
is transmitted on feedback path 12 to the input stage of the
shift register 10. The circuit under test 20 receives the
test patterns from the LFSR 5 and provides the test patterns
on bus 22. As mentioned above, the circuit of the invention
is particularly well suited to the testing of a circuit such
as a switching network which of course comprises a plurality
of transmission paths. The multiplexer 15 is thus arranged
to switchably connect the test signals from the LFSR 5 or the
normal input data on bus 17 to the various input ports of the
switching network. Data bus 21 connected to bus 22 provides
ouL~L data to other circuitry connected to the circuit under
test 20. The data transmitted on data bus 21 is either
normal input data which originated on data bus 17 or the
input test data originating from the LFSR 5.
A second LFSR circuit 50 is configured in a similar
-nner as the first; however, a multiplexer 40 permits one of
two signals to be fed back to the input stage of a shift
register 51. An exclusive-or gate 53 is responsive to the
two most significant bits of the shift register 51, (e.g.,
bits 14 and 15), to generate an exclusive-or feedback signal
which is transmitted on feedback path 52 to the multiplexer
40 which is also cor.nected to data line 24 to receive a
signal carried on the least significant data line of data bus
22. The control circuit 30 provides a selection control
signal on control line 34 for selecting the signal carried on
data line 24 or the feedback signal carried on feedback path
52. The least significant data line on data bus 22 is
connected to data line 24 to permit a portion of the pseudo
random data transmitted in the least significant bit position
to be transmitted to the second LFSR 50 via the multiplexer
40. The control circuit also monitors the value stored in
the LFSR 5 and the LFSR 50 via control lines 16 and 19
respectively.
A comparator 60 is connected to receive the 10-bit
series of output test patterns from the circuit 20 and a
10-bit pattern generated by the second LFSR circuit 50 on
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data bus 58. The comparator 60 compares the two 10-bit
series of test patterns and generates true or false signals.
A clock signal provided on control line 18 provides a timing
signal to the first LFSR 5, the control circuit 30, the
second LFSR circuit 50 and to the comparator 60. If that
clock signal has the same frequency as that normally driving
the circuit under test 20, then the circuit is exercised
under real-life conditions.
In operation, the LFSR S is adapted to generate
pseudo random binary test data for provision to the circuit
under test 20. After a sequence of 215-l patterns have been
generated by the LFSR 5 the sequence of patterns repeats.
Upon power up of the test circuitry, the control
circuit 30 initializes the 15-bit binary value stored in the
LFSR 5 to a non-zero value to prevent the LFSR 5 from
generating only zero-bit patterns. After initialization, the
control circuit 30 continues to monitor the contents of the
first and second LFSRs 5 and 50 to ensure that they do not
remain in a state where either one of them contains all zero
bits. If an all zero state is detected in the LFSR 5 or the
LFSR 50, the control circuit 30 re-initializes the test
circuit by asserting the signals on control lines 32 and 34.
Once the LFSR 5 has been initialized, the binary
word stored in the 15-bit shift register 10 is shifted in the
more significant direction in a rotational manner; the bit
stored in the first stage of the shift register 10 is shifted
to the second stage; the bit stored in the second stage is
simultaneously shifted to the third stage, and so on. Each
shift occurs synchronously with each period of the clock
signal. As each shift occurs, the bits stored in the two
most significant bit positions, bits 14 and 15 are
exclusive-ored and the resultant signal is fed back to the
least significant bit position of the shift register 10.
Feeding back the resultant signal ensures that, with each
period of the clock signal, the binary value of the 15-bit
binary word in the LFSR 5 changes with each shift. The least
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significant 10 bits of the 15-bit binary word corresponding
to the first 10 stages of the shift register, form a binary
pattern and with each shift, a different pattern is formed.
Of course, the entire 15 bits could be used to form test
patterns, however, in the embodiment described only the least
10 significant bits are required. Providing an LFSR which
has more register stages than the bits used for the test
patterns as exemplified in the embodiment, provides more
patterns in the series of test patterns and thus provides a
greater variation of stimuli presented to the circuit under
test. The series of pseudo random binary data patterns are
transmitted to the circuit under test 20 via data bus 14 and
multiplexer 15.
After a transmission delay in the circuit under
test 20, the comparator 60 is presented with the first
patterrl via data bus 2Z. During the initialization stage,
the selection control signal is asserted on control line 34
to select a least significant bit of the series of patterns
transmitted on data bus 22 to provide an input signal to the
second LFSR circuit 50. After 15 clock cycles have occurred,
a 15-bit word corresponding to a word that was generated in
the first LFSR 5 will have been written into the second LFSR
circuit 50. By copying 15 successive values from the least
significant data line of data bus 22, and shifting the 15
bits into the second LFSR 50, a 15-bit word is captured which
was generated sometime before in the first LFSR 5. The
15-bit binary word in the LFSR 50 represents a seed value
from which it may generate data patterns on its own in a free
running mode. The control circuit 30 thus de-asserts the
selection control signal on control line 34 and the
multiplexer 40 provides the input stage of the second LFSR 50
with the exclusive-or feedback signal carried on feedbac~
path 52. With each successive period of the clock signal, a
10-bit binary word corresponding to the least significant
10-bits of the second LFSR 50 are presented to the comparator
60. Each 10-bit binary word presented to the comparator 60
on data bus 58 should henceforth match a pattern of the
series of patterns received on data bus 22. A mismatch
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between the two 10-bit binary words presented to the
comparator 60 results in the comparator generating a false
condition signal on an output line 62. A mismatch indicates
that a 10-bit pseudo random binary pattern has become altered
during transmission through the circuit under test 20.
Corrective action may be taken on each error detection or
statistics of false conditions may be logged and corrective
action taken when the number of false conditions exceeds an
acceptable predetermined number.
The invention thus provides a simple and economical
circuit and method of verifying the integrity of a
tr~n~ ission path. Since the circuit uses only digital logic
circuitry, it may be readily implemented as an integrated
circuit either on its own or as a portion of another
integrated circuit. In addition, the circuit may be driven
by the same clock signal source as that of the circuit under
test thus providing real life test conditions.
Numerous other modifications, variations and
adaptations may be made to the particular embodiment of the
invention described above without departing from the scope of
the claims.
