Note : Les descriptions sont présentées dans la langue officielle dans laquelle elles ont été soumises.
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1 Title of the Invention
A FIELD EFFECT TRANSISTOR
sack~round o~ the Invention
(Field of the Invention)
This invention re].ates to a field effect
transistor (FET), speci~ically to ~ structure of a
field effect transistor which is suitable for
integration, and has high outputs and gains.
(Related Background Art)
Recently accompanying the rapid development of
information network systems, the needs for direc-t
broadcast satellite communication systems as well is on
increase, and the frequency band is becoming higher.
High frequency FETs, especially GaAs metal-
semiconductor FETs (MESFETs) are practiced as
transis-tors which can make a breakthrough the
characteristic limit of the conventionally used Si
bipolar transistors. Recently for the miniaturization,
lower prices and higher performance of the systems, the
integration of the first stage amplification circuits
of a downconverter that converts a high frequency
signal to a low -frequency signal is advanced and the
circuits are formed as microwave monolithic integrated
circuits (MMIC's).
To achieve higher output and higher efficiency of
the GaAs MESFET, it is important to reduce a resistance
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1 between the source electrode and the gate electrode,
i.e , the source resistance (Rs) to thereby
increase the transconductance (gm)~ and, at the same
time, to increase the drain voltage resistance between
the gate electrode and the drain eleccrode. In view o~
this, as described in Japanese Patent Laid-open
Publication No. 177779/1986, the usual high-output
MESFETs use the structure of Fig. 1 for decreasing the
source resistance Rs. That is, a gate structure which
is called recess structure is used. In the recess
structure, a recess 3 oE a given depth is provided
between the source electrode 1 and the drain electrode
2, and the gate electrode ~ is formed on the bo-ttom
surface of the recess 3. Furthermore, for increasing
the drain voltage resistance, the gate electrode 4 is
offset nearer to the source electrode 1 so that
distance between the gate electrode ~ and the drain
electrode 2 becomes wide.
But in such device structure) for example, in an
n-channel MESFET, a phenomenon called long gate e~fect
occurs where a gate bias is lower, i.e., where the gate
voltage has a negative value, and its absolute value is
smaller. This long gate eEEect is a phenomenon that an
effective gate length increases due to a surface
depletion region on the side of the drain electrode 2.
This phenomenon is reported in good detail in The
Institute of Electronics InEorma-tion and Communication
2~8~
1 Engineers (AED86-142, 1986). It is known that the
transconductance gm lowers due to -this long gate e-~ect.
As means for improving the long gate ef~ect, the MESFET
of the struoture o~ Fig. 2 was disclosed in Japanese
Patent Laid-Open Publication No. 260861/1989. That is,
a recess 8 is formed in an operational layer 7 between
a source electrode 5 and a drain electrode 6, a gate
electrode 9 is ~ormed on the bottom surface of the
recess 8, and -the recess 8 has the stepped sidewall
nearer to the drain electrode 6. This two-step
sidewall prevents the long gate effect.
On the other hand, there is a high-frequency
MESFET having a gate electrode region of a planar
structure without such recess structure. In this
MESFET, the ion implantation of dopant ions is
per~ormed by utilizing self-alignment using the gate
electrode as a mask in order to reduce the source
resistance of the operational layer. The integra-tion
of this MESFET with the gate electrode region o~ such
planar structure is reported in GaAs IC Symposium
Technical Digest (1987), pages 45 to 48 and pages 49 to
~2. In addition, there is a MESFET having a gate
electrode region of such planar structure which was
developed by the applicant of the present application,
and this MESFET is described in IEEE MTT-S
International Microwave Symposium Digest, 1990, pages
1081 to 1084. In this MESFET, an epitaxial wafer of a
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I pulse-doped structure having a thin channel layer o~ a
higher carrier densi-ty, and a cap layer o~ a lower
carrier density formed on the channel layer is used.
The integration of this planar-structure FET having
such pulse-doped structure is disclosed in GaAs IC
Symposium Technical Digest, l990, pages 237 to 240.
But the respective conventional FETs described
above have the following technical problems. The
MESFET with the recess structure of Fig. 2 has solved
the occurrence of long gate effect intrinsic to the
recess-structure FET of Fig. l, but because o~ the
recess-structure intrinsically formed in the gate
electrode region, the homogeneity and reproductivity of
the manufactured FETs are not good. This results from
poor controllability of the recess etching in ~orming
recesses 3, 8, which causes deviations of an etched
depth. In integrating especially such MESFETs on
semiconductor substrates as high-output integra-ted
circuit devices, the yield becomes low, the
productivity becomes low.
On the other hand, the planar-struc-ture MESFET
without such recess structure in the gate electrode
region is free from the above-described problems
involved in homogeneity and reproductivity resulting
from the recess etching, but has the same problem as
the recess-structure FET of Fig. l. That is, for
higher output and higher drain voltage resistance of
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1 the FET, as described above, the gate electrode is
offset apart from the n ion added layer nearer to the
drain electrode. But in this structure, as described
above, long gate e~ect adversely occurs where a gate
bias is lower, and the transconduc-tance gm adversely
lowers. Furthermore, the MESFET having such planar-
structure gate electrode region has not been able to
find effective preventive means owned by -the recess-
structure MESFET, i.e., the effective means that the
sidewall of the recess has two steps as in Fig. 2.
Summarv o~ the Invention
An object o~ this invention is to provide a high
output FET which has solved the above-described
problems, and has a planar gate structure suitable for
integration and a structure for suppressing long gate
e~fect.
Further object of the present invention to provide
a field effect transistor comprising a heavily doped
thin channel layer formed on a substrate through a non-
doped buffer layer a cap layer ~ormed on the channel
layer a gate electrode formed on the cap layer in
Schottky contact therewith and a source electrode and a
drain electrode formed on both sides of the gate
electrode in ohmic contact with the cap layer, in the
cap layer there being ~ormed a doped layer having a
dopant of the same conduction as the channel layer
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1 added to.
In an FET according to the present invention, the
extension of a sur~ace depletion region ~rom a
substrate surface to the deeper is prevented by the
doped layer so that the surface depletion layer does
not affect the channel layer and as the result only the
depletion region under the gate electrode affects the
channel layer. Accordingly long-gate effect is not
caused. Additionally, in this time, the doped layer
itself is depleted by the surface depletion region so
that the insulation between the gate and the drain is
not degraded. Further as the FET has a planer
structure, the productive yield o~ the FET is higher
~han that of the FET having a recess-structure.
The present invention will become more fully
understood from the detailed description given
hereinbelow and the accompanying drawings which are
given by way of illustration only, and thus are not to
be considered as limiting the prasent invention.
Further scope of applicability of the present
invention will become apparent from the detailed
description given hereinafter. However, it should be
understood that the detailed description and specific
e~amples, while indicating preferred embodiments of the
invention, are given by way of illustration only, since
various changes and modifications within the spirit and
scope of the invention will become apparent to those
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1 skilled in the art ~orm this detailed description.
Brie~ Description of the Drawin~s
Fig. 1 is a sectional view o~ one example o~ the
conventional MESFETs;
Fig. 2 is a sectional view o~ another example o~
the conventional MESFETs;
Fig. 3 is a sectional view o~ the structure o~
MESFET according to one embodimen-t o~ this inven-tion;
~, Figs. 4A to 4D are sectional views of the MESFET
of Fig. 3;
Figs. 5A and 5B are sectional views o~ the FET
according to the embodiment and o~ the conventional
FETs both with the channels completely shut by
depletion regions Figs. 6A and 6B are sectional views
of the FET according to the embodiment and the
conventional FETs with their depletion layers in their
states where a gate bias is lower;
Figs. 7A and 7B are sectional views o~ the FET
according to the embodiment and the conventional FETs
with their depletion regions in their states where the
gate bias is further lower; and
Fig. 8 is a graph o~ the drain conductance gm
dependence o~ the FET according to the embodiment and
the conventional FETs on the gate voltage Vg.
DescriPtion of the Pre~erred Embodiment
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1 Fig. 3 is a sectional view of the structure of the
MESFET according to one embodiment of this invention.
The ~abrication process of this MESFET is shown in the
sectional views of the respective :Eabrication steps of
Figs. 4A to 4D. To clarify the st:ructure of this
MESFET, its fabrication steps will be explained
firstly, and then the operation of this MESFET will be
explained. First, a non-doped GaAs buffer layer lZ is
formed on a semi-insulating GaAs semiconductor
substrate 11 (see Fig. 4A). This buffer layer 12 is
formed by a crystal growing method, such as MBE
(molecular beam epitaxy), OMVPE (organic metal vapor
phase epitaxy), and to improve the carrier sealing of a
channel layer 13 which will be explained later, a ~eed
ratio between a V group material and a III group
material is controlled to form p-conduction. The
carrier concentration of this GaAs buffer layer 12 is
set at, e.g., 2.5 x 1015 cm~3.
Then, an Si-doped GaAs channel layer 13 is formed
on the buffer layer 12 at a carrier density as high as
4 x 1018 cm3 and in a thickness as thin as 200 A. On
this channel layer 13 subsequently is formed an n-
conduction non-doped GaAs layer 14 at a concentration
below 1 x 1015 cm3 and in a thickness of 150 R (see Fig.
4B). These layers 13, 14 are formed by a crystal
growing method, such as MBE, OMVPE, or others.
Next, on the non-doped layer 14 is formed a doped
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1 layer 15 which is an Si-doped GaAs layer at a ~ x 1018
cm carrier density and in a 50 A thickness. Then on
this doped layer 15 is formed an n-conduction non-doped
layer 16 at a carrier density below 1 x 1015 cm3 and in
a 200 A-thickness (see Fig. 4C). These layers 15, 16
are also formed by the above-described crystal growing
method. The non-doped layer 14, the doped layer 1~ and
the non-doped layer 16 constitute a cap layer. In the
above-stated thickness and dopant concentration of the
doped layer 15 of the cap layer, a surface depletion
region caused by a surface state depletes the doped
layer 15 itsel~ and as the result the surface depletion
region does not extend to the channel layer 13.
Subsequently a gate electrode 17 is ~ormed on an
epitaxial wafer of such structure by vaporization,
lithography, etching or other methods. Then an oxide
or others is formed on the sidewall o~ the gate
electrode 17, and with this oxide or others as a mask
Si ions are selectively implanted in the substrate
surface. This ion implantation forms n+-Si ion-
implanted region 18, 19 (see Fig. 4D). In this case,
the ion-implanted layer 18, which is on -the drain side,
is formed further from the gate electrode 17.
Finally a drain elec-trode 20 and a source
electrode 21 are formed in ohmic contact with the
respective ion-implanted region 18, 19 by the same
vaporization, lithography or other methods. When these
l electrodes are prepared, a MESFET of the structure o~
Fig. 3 is completed.
In the MESFET of this structure according to khis
embodiment, the gate electrode 17 is ~ormed on the ~la,t
cap layer, and a planar structure MESFET is ~ormed.
Consequently the disadvantage of the FET having a
recess structure at the gate electrode region, i.e.,
the disadvan-tage o~ lower ~abrication yields resulting
from poor homogeneity and reproduc-tion due to the
lO rece~s etching can be eliminated.
Next the operation of the MESFET according to this
embodiment will be explained below with reference to
Figs. 6A to 7B in comparison with the conventiona]
MESFETs.
Figs. 5A, 6A and 7A show the MESFET according to
this embodiment, and the parts common with those o~
Fig. 3 have common re~erence numerals.
Figs. 6B, 6B and 7B respectively show MESFETs
having a planar-structure ~ormed by the conven-tional
technology.
In this conventional MESFET, the same channel
layer 32 as the channel layer 13 in this embodiment is
formed on the GaAs semiconductor substrate 31. A
lightly doped cap layer 33 is ~ormed on this channel
layer 32. The same ion-implanted region 34, 35 as the
ion implanted region 18, 19 in this embodiment are
-~ormed on both sides of the cap layer 33. A gate
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1 electrode 36, a drain electrode 37 and a source
electrode 38 are ~ormed at the same positions relative
to one another as those o~ this embodiment.
Figs. 5A and i5B show the states o~ these MESFETs
where the same negative ga-te voltage Vg is applied to
their respective gate electrodes 17, 36 ~or their
respective source electrode 21, 38 and the channel are
completely closed by -their respective depletion region
direc-tly below their respective gates.
That is, in the FET o~ the embodiment shown in
Fig. 5A, a depletion layer under the gate electrode 17
which is designated by oblique lines, completely closes
the channel layer and also in the conventional FET o~
Fig. 5B. The depletion region under the gate electrode
36, which is designated by oblique lines completely
closes the channel layer 32. Surface depletion region
resulting from sur~ace inter~ace level between the
gates electrodes 17, 36 o+ the MESFETs and the n+-Si
ion-implanted region 18, 34 on the side of the drain
electrodes, and are integral with the depletion region
directly below the gate electrodes.
Figs. 6A and 6B show the states of the depletion
region o~ the MESFETs in their respective states o~
Figs. 5A and 5B in the case that the gate bias voltage
Vg lowered, i.e., the gate voltage Vg gradually
decreased to 0 voltage. The respective depletion ~, `
region directly below the gaties become shallower as
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1 negative charges accumulated in the gates electrode 17,
36 decrease, and the channels of the respective current
channel layers 13, 32 begin to open. In this state,
when a suitable voltage is applied to the applied
voltage begins to ~low between the respective drain and
sources.
Figs. 7A and 7B show the states o~ the depletion
region of the MESFETs when the gate vol-tage Vg in the
states o~ Fig. 6A and 6B are further decreased. When
an absolute value of the gate voltage Vg gradually
decreases down to one value, in the conventional MESFET
of fig. 7B, a depth o~ the depletion region directly
below the gate electrode 36, and a depth o~ the sur~ace
depletion region on the side o~ the drain electrode 37
extending to the channel layer 32 become substantially
equal to each other. Resultantly a short e~ec-tive
gate length La in Fig. 6B becomes a long effective gate
length Lb in Fig. 7B, and long gate effect takes place.
Consequently due to this long gate e~ect the
transconductance gm ~ the conventional MESFET
decreases, adversely de-teriorating its high ~requency
characteristic.
In contrast to this, in the MESFET according to
this embodiment o~ Fig. 7A, the growth of the surface ~-
depletion region deeper ~rom the substra-te sur~ace is
prohibited by the doped layer 15. Consequently the
channel layer 13 on the side of the drain electrode 20
12
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1 is Eree ~rom the ineluence o~ the sur~ace depletion
region, but is influenced by the depletion region
directly below the ga-te electrode 17. Accordingly an
effective gate length Lc does not change, and no long
gate effect takes place, as does in the conventional
MESFET. Consequently a current channel ~ormed in the
channel layer 13 completely opens, and the value of a
transconductance gm is retained high until the current
is saturated. As a result, its high fre~uency
characteristic is sustained in good state. At this
time, because the doped layer 16 per se is completely
depleted by the surface depletion region, the
insulation between the gate electrode 17 and the drain
electrode 20 does not lower. Consequently in the
MESFET according to this embodiment, it is possible to
retain the drain voltage resistance high.
Fig. 8 schematically shows the gate voltage
dependence characteristic of the -transconductance gm in
the case that the gate bias is changed as above. In
Fig. 8 the gate voltage [V] is taken on the horizon-tal
axis, and the transconductance gm [ms/mm] is taken on
the vertical axis. The characteristic curve 41
depicted by the solid line indicates a characteristic
of the MESFET according to this embodiment, and the
characteristic curve 42 depicted by the dot line show
characteristics of the conventional MESFET. As seen
from Fig. 8, in the conventional MESFET the value of
`- 2 ~ 6 5
1 the transconductance gm does not lower but retained high
at a certain value.
From the invention thus described, it will be
obvious that the invention may be varied in many ways.
Such variations are not to be regarded as a departure
from the spirit and scope of the invention, and all
such modi~ications as would be obvious to one skilled
in the art are intended to be included within the scope
of the ~ollowing claims.
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