Note : Les descriptions sont présentées dans la langue officielle dans laquelle elles ont été soumises.
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The present invention relates to a surge counter
provided on various supply lines such as power supply lines
and communication lines. More, particularly, the invention
is concerned with a surge counter for counting the number
of times invading surges occur and invade these lines.
If surges invade power supply lines used for
communication equipment such as telephone sets, facsimiles,
telephone switching boards, modems and the like, the
electronic circuits of the communication equipment could be
irreversibly damaged, for example, by fire. Therefore,
conventionally, surge absorbers are provided on input lines
of power supply lines, communication lines and the like for
protecting the communication equipment which is installed
in an area where surges may occur.
In order to efficiently protect the communication
equipment with surge absorbers, the electrical
characteristics of the surge absorbers must be selected
based on the results of a statistical investigation,
including the anticipated number of invading surges and the
value of the current induced by the surges in the area
where the communication equipment is to be installed.
Conventionally, for example, a surge counter for
recording the number of invading surges has been disclosed
in ~nexamined Published Japanese Patent Application No. 59-
211984. This surge counter comprises: a surge absorbingelement which is connected to the lines which could be
invaded by a surge and which comprises a gap type glass
sealed discharge tube and a nonlinear resistor connected in
series; a light sensitive element for detecting the light
emission of the discharge tube; and a counter circuit for
counting the signals detected by the light sensitive
element. In this surge counter, the surge input circuit
and the surge detecting circuit are independent so that
there is no possibility for surge inputs to enter the
detecting circuit. This counter has a simple design of the
detecting circuit, which can be easily implemented.
Surge counters for recording both the number of
invading surges and the surge current value have been
disclosed in, for example, Unexamined Published Japanese
Patent Application No. 60-9081, Unexamined Published
Japanese Utility Model Application No. 61-117484, and
Unexamined Published Japanese Patent Application No. 62-
193075.
The surge counter of Unexamined Published
Japanese Patent Application No. 60-9081 comprises a full-
wave rectifier circuit, for rectifying the dischargecurrent for an arrester, connected between the earth
terminal of the arrester and the earth, and a plurality of
discharge current measuring counter circuits connected in
parallel with each other and connected to the full-wave
rectifier respectively through potential dividing resistor
elements. In this counter, the discharge current of the
arrester is sorted into specified current ranges by plural
voltage dividing resistor elements.
The surge counter of Unexamined Published
Japanese Utility Model Application No. 61-117484 comprises
a nonlinear resistor for conducting a discharge current
flowing in the arrester, one or more capacitors connected
in parallel with the nonlinear resistor, a plurality of
sets of linear resistors and a counter driving coil which
are connected to the capacitors so that they distribute the
charging energy of the capacitor. This surge counter
detects a discharge current within a specified range at
every current value without a driving power supply by
setting resistance values of each set of linear resistors
at optional different values.
Further, the surge counter of Unexamined
Published Japanese Patent Application No. 62-193075
comprises a discharging gap with a shunt resistor provided
on the earth terminal of an arrester, a photosensor for
converting the light emitted from the discharging gap into
a current corresponding to the quantity of the light, and
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a counter section for counting the operations in response
to a detected current value of the photosensor. This surge
counter can accurately check the operational frequency by
the intensity of currents of an arrester without using
complicated electric circuitry.
However, the surge counter of Unexamined
Published Japanese Patent Application No. 59-211~84 has a
disadvantage in that it only records the number of
occurrences of the invading surges, but it does not record
the surge current value.
The surge counters of Unexamined Published
Japanese Patent Application No. 60-9081 and Unexamined
Published Japanese Utility Model Application No. 61-117484
have a reliability disadvantage in that the surge input
circuit and the surge detecting circuit are electrically
connected with each other, which makes it possible that a
surge could invade the surge detecting circuit.
Notwithstanding that the surge counter of
Unexamined Published Japanese Patent Application No. 62-
193075, seems to solve the foregoing problems, it has itsown drawback in that the light emitted from a single
discharge gap is detected by a single photosensor and the
surge current values need to be sorted for each detected
current. Accordingly, there is a disadvantage that a
highly sensitive photosensor and a complicated detecting
circuit are required for accurately sorting the surge
current values.
An object of the present invention is to provide
a surge counter for accurately sorting surge current values
having a simplified circuit design, without using a highly
sensitive photosensor and capable of counting the number or
occurrences of invading surges.
Another object of the invention is to provide a
highly reliable surge counter designed to substantially
restrain the invasion of surges in a surge detecting
circuit.
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A surge counter according to the present
invention, comprises a plurality of surge absorbing
elements, each having a different impulse discharge
starting voltage, which are connected in parallel with each
other and to surge invadable lines. Each surge absorbing
element includes a gap type discharge tube series connected
with a nonlinear resistor. A light sensitive element is
arranged close to each discharge tube for detecting the
light emitted there~rom. A counter circuit is connected to
each light receiving element for counting the signals
detected by the respective light sensitive elements.
In this disclosure, by definition, an impulse
discharge starting voltage means a voltage at which a surge
absorbing element starts the discharge when an experimental
surge voltage is applied to the surge absorbing element.
Surge current values are accurately sorted and
the number of invading surges is counted using a simplified
circuit construction. The surge detecting circuit cannot
be invaded by surges and thus, the reliability of the
circuit is high.
Embodiments of the invention will now be
described, by way of example, with reference to the
accompanying drawing, in which:
The single Figure is a block diagram of a surge
counter according to the invention.
The preferred type of discharge tube of the
present invention is an air gap discharge tube, a gas
sealed discharge tube, a micro-gap glass sealed discharge
tube or the like. The nonlinear resistor series connected
with the gap type discharge tube is preferably a zinc oxide
varistor, a silicon carbide varistor or the like. In
particular, the zinc oxide varistor which has both a large
factor of nonlinearity and a large varistor-effect is
suitable. The light sensitive element, is preferably a
photoconductive element which contains a polycrystal such
as CdS, CdSe, PbS etc., as a main component.
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In the Figure, for simplicity of explanation
only, three sets of surge absorbing elements, three sets of
light receiving elements and three counter circuits are
illustrated. The number of sets which may be used in
accordance with the teachings of the invention is not
limited to three sets, but, any number of sets may be
employed, depending upon the particular situation.
Surge absorbing elements c~, c2, and C3 are
connected in parallel with each other across lines A and A'
which may be invaded by surges and for simplicity, are
referred to as surge invadable lines. Each of the surge
absorbing elements c~, c2, and C3 comprises a gap type glass
sealed discharge tube a~, a2, and a3, respectively, connected
in series with a nonlinear resistor b~, b2, and b3,
respectively. While not shown, in the same manner, if a
fourth surge absorbing element C4 iS used, it would comprise
a discharge tube a4 connected in series with a nonlinear
resistor b4, and the surge absorbing element cn would
comprise a discharge tube an connected in series with
nonlinear resistor bD, etc. The nonlinear resistors bl to
b3 are provided for preventing the generation of a follow
current in discharge tubes a~ to a3, because the lines A and
A' are always connected to a power supply voltage. The
term "follow current" means the current at power frequency
that passes through a discharge path after the respective
high voltage surge absorbing element has started the
discharge.
Light sensitive element d~ is arranged close to
discharge tube a" in light receiving relationship
therewith, to detect the light emitted during discharge of
tube a~. The output of light sensitive element d~, is
connected to a counter circuit e~. In a similar manner,
light sensitive elements d2 and d3, are respectively
connected to counter circuits e2 and e3 and detect light
emitted by discharge tubes a2 and a3, respectively. The
discharge tube a~ and the light receiving element d~ are
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placed into a dark box fl so as to prevent interference from
extraneous exterior light. In the same way, dark boxes f2
and f3 are also provided.
The discharge starting voltages of the discharge
5 tubes al to a3 and voltages of the varistors bl to b3 are
selected to satisfy the relationship Vl < V2 < V3, where Vl,
V2, and V3 are the impulse discharge starting voltages of
the surge absorbing elements cl, c2, and C3, respectively.
While not shown, when impulse discharge starting
10 voltages of V~, V2, V3 ... Vn are provided for surge
absorbing elements c~ to cn, respectively, the discharge
starting voltages of the discharge tubes a~ to an and the
voltage of the varistors b~, b2, b3 ... bn are selected to
satisfy the relationship V~ < V2 < V3 < -- Vn.
The differences between V2 and Vl and the
difference between V3 and V2 are set in the following
manner. On the attached Figure, the setting currents of
the surge absorbing elements cl, c2 and C3 are annotated as
Il, I2 and I3 respectively, and the currents actually flowing
2 0 into the surge absorbing elements cl, c2, and C3 are
annotated as i~, i2 and i3 respectively. Voltage V2 should
be set so that the surge absorbing element c2 responds to an
imposed voltage across points B~ and B~ ' when the current
value il is larger than the setting current Il. In other
25 words, assuming that i represents a surge current invading
lines A and A', V2 is set so that, if i < I" the surge
absorbing element c2 does not respond, but if i ~ I" the
surge absorbing element c2 responds.
If the surge current is larger than I~ (i > Il),
3 0 then the surge current is distributed to surge absorbing
elements cl and c2 with current values of il and i2,
respectively. Here, V3 is set so that, if i < I2, the surge
absorbing element C3 does not respond, but if i > I2, the
surge absorbing element C3 responds. When additional units
35 are used if i > Inl, the surge absorbing element CD responds.
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If n=4, In~ is I3. The fact that the surge absorbing el~ment
C3 responds in the foregoing process is due to the voltage
generated across points B3 and B3' by the surge currents i
an~ i2 as is the case of the element c2.
In the case of n sets of surge absorbing
elements, with respective light sensitive elements and
counter circuits, the impulse discharge starting voltage Vn
is set relative to the setting current Inl in the same way.
In operation, when a surge voltage appears across
lines A and A', the surge absorbing element cl responds
first having the minimum discharge starting voltage Vl among
the voltages Vl, V2, and V3. As the surge current il flows
through surge absorbing element cl, a voltage corresponding
to the product of the impedance of the element cl and the
current value il is generated between the points Bl and B~'.
At this time, the light emitted by the discharge tube al is
received by the light sensitive element d~. Light sensitive
element dl generates a signal which operates the counter
clrcult e~.
When the surge current i which invades lines A
and A' is smaller than the setting current value I~ (i <
Il), then only the surge absorbing element cl responds and
the elements c2 and C3 do not respond. Accordingly, only
the counter circuit e~ operates. If Il < i < I2, then the
surge absorbing elements cl and c2 operate, and the element
C3 does not operate. Accordingly, only the counter circuits
el and e2 operate. Further if I2 < i, then the surge
absorbing elements c~, c2, and C3 all respond, so that the
counter circuits e1, e2, and e3 all operate.
Table l illustrates operation of counter circuits
e~, e2 and, e3 when a surge current of value i invades lines
A and A'. The number of invading surges and the current
values thereof both can be recorded by the numbers counted
by circuits e1, e2, and e3.
Table 1
Surge Current Counter Circuit
in Operation
i < Il el
Il < i < I2 el, e2
I <
2 - 1 el, e2 r e3
The surge counter according to the invention
records the surge current values and furthermore, it counts
the number of invading surges. In particular, if the
impulse discharge starting voltages of the surge absorbing
elements are set in a convenient way, the surge currents
which range from a very small current to an extremely large
current can be recorded.
Further, by arranging a plurality o~ surge
absorbing elements, the surge current can be distributed
into this plurality of surge absorbing elements, and a high
resistance to surges can be obtained as compared to the
conventional single surge absorbing element.
A particular embodiment of the circuit of the
Figure will be described in the following as an example.
However, the present invention is not limited to this
particular embodiment.
As shown in the Figure, the gap type discharge
tubes al to a3 are micro-gap type glass sealed discharge
tubes. The nonlinear resistors b~ to b3 are zinc oxide
varistors, and the light receiving elements dl to d3 are CdS
elements. The light receiving elements d~ to d3 are placed
close to discharge tubes a~ to a3, respectively.
In this embodiment, the direct-current discharge
starting voltages of the discharge tubes are selected to be
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300 V for al, 500 V for a2, and 700 V for a3. The voltages
of the varistors are selected 220 V for bl, and 270 V for
both of b2 and b3. As a result, the impulse discharge
starting voltages of the surge absorbing elements cl, c2 and
C3 have an average measured value of Vl = 700 V, V2 = 900 V,
and V3 = 1100 V, respectively.
Therefore, when a surge voltage of 700 V or more
is applied across lines A and A', the surge absorbing
element cl responds, and a detected signal is generated by
the light receiving element d~ due to the light emitted
during discharge of tube al, and the counter circuit e
operates. When the current flowing on the lines A and A'
reaches 1000 A, the voltage across element cl exceeds 900 V.
Hence, both elements cl and c2 respond, and counter circuits
e~ and e2 operate. When the current increases and reaches
a value of 2500 A, the voltage across element c2 exceeds
1100 V, and all three elements cl, c2 and C3 respond, and all
counter circuits el, e2, and e3 operate.
Table 2 shows the results obtained when the
operation of the counter circuits is tested by varying the
surge current. From the state of the operating counter
circuit in Table 2, not only the number of the invading
surges, but also the fre~uency distribution of the surge
currents could be recorded.
Table 2
Surge Current (A) Counter Circuit
in Operation
O < i < 1000 el
1000 < i < 2500 el, e2
2500 < i el, e2, e3
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While there has been shown and disclosed what is
considered to be the preferred embodiment of the invention,
various changes and modifications may be made therein
wi-thout departing from the scope of the invention.
