Note : Les descriptions sont présentées dans la langue officielle dans laquelle elles ont été soumises.
2 1 08883
DIFFERENTIAL EMITTER COUPLED LOGIC CIRCUIT
FIELD OF THE lNV ~:N ~ ION
The present invention relates generally to emitter
coupled logic (ECL) circuits with differential inputs and
output, and more particularly to logic function circuits.
R~CKGROUND OF THE lNV~N ~ ION
A multiplexer or logic function circuit such as an
exclusive OR (XOR), non-exclusive (NXOR), OR, NOR, AND or
NAND circuit is usually formed on a semiconductor
integrated circuit chip. For example, United States Patent
No. 4,963,767 dated October 16, 1990 by Nguyen X. Sinh
discloses an ECL (emitter coupled logic) multiplexer of non-
differential type. United States Patent No. 4,866,306
dated September 12, 1989 by Daniel F. Hopta discloses an
ECL multiplexer, which has series gates with differential
outputs and non-differential inputs. United States Patent
No. 4,628,216 dated December 9, 1986 by Nikhil C. Mazumder
discloses multiplexers and XOR and other logic circuits.
Also, ELECTRONICS LETTERS, 29th March 1990, Vol.26, No.7
shows a high speed XOR and ELECTRONICS LETTERS, December
1989 discloses a high speed multiplexer.
However, these prior art circuits have
disadvantages - low speed, a small noise margin and/or a
large power consumption - due to the use of series gates or
non-differential type circuits.
SUMMARY OF THE lNV~N ~ ION
The present invention provides differential ECL
circuits (e.g., logic function circuits), which overcome
such disadvantages.
According to one aspect of the present invention, a
differential ECL circuit comprises:
B
CA21 08883
first, second, third and forth transistor pairs,
each comprising first and second transistors whose emitters
are connected to each other;
first, second, third and forth constant current
sources, each being connected between the connected
emitters of each respective transistor pair and a first
potential terminal;
four load resistors connected between the first
and second transistors' collectors of the first and forth~o transistor pairs and a second potential terminal;
the first and second transistors' collectors of
the second transistor pair being connected to the second
and first transistor's collectors of the first transistor
pair, respectively;
the first and second transistors' collectors of
the third transistor pair being connected to the second and
first transistor's collectors of the forth transistor pair,
respectively;
means for providing a first differential input
signal between the bases of the first and second
transistors of the first transistor pair and between the
bases of the first and second transistors of the forth
transistor pair;
means for providing a second differential input
signal between the bases of the second and first
transistors of the second transistor pair and between the
bases of the first and second transistors of the third
transistor pair; and
first, second, third and fourth emitter follower
transistors, the emitters of the first and second emitter
follower transistors being connected to the first potential
terminal through a first emitter resistor, the emitters of
the third and forth emitter follower transistors being
connected to the first potential terminal through a second
emitter resistor, the bases of the first and second emitter
follower transistors being connected to the first and
second transistors' collectors of the first transistor
CA2 1 08883
pair, respectively, and the bases of the third and fourth
emitter follower transistors being connected to the first
and second transistors' collectors of the fourth transistor
pair, respectively.
By the differential ECL circuit, a differential
output signal of an XOR or non-XOR logic based on the first
and second differential input signals is provided across
the first and second emitter resistors.
According to another aspect of the present~0 invention, a differential ECL circuit comprises;
first, second and third transistor pairs, each
comprising first and second transistors whose emitters are
connected to each other;
first, second and third constant current sources,
each being connected between the connected emitters of each
respective transistor pair and a first potential terminal;
four load resistors connected between the first
and second transistors' collectors of the first and third
transistor pairs and a second potential terminal;
the first and second transistors' collectors of
the second transistor pair being connected to the second
transistor's collector of the third transistor pair and to
the first transistor's collector of the first transistor
pair, respectively;
means for providing a first differential input
signal between the bases of the first and second
transistors of the first transistor pair;
means for providing a second differential input
signal between the bases of the second and first
transistors of the second transistor pair and between the
bases of the second and first transistors of the third
transistor pair; and
first, second, third and fourth emitter follower
transistors, the emitters of the first and fourth emitter
follower transistors being connected to the first potential
terminal through a first emitter resistor and the emitters
of the second and third emitter follower transistors being
(~21 0888~
connected to the first potential terminal through a second
emitter resistor, the bases of the first and second emitter
follower transistors being connected to the first and
second transistors' collectors of the first transistor
pair, respectively, and the bases of the third and fourth
emitter follower transistors being connected to the first
and second transistors' collectors of the third transistor
pair, respectively.
By the differential ECL circuit, a differential
output signal of an OR or NOR logic based on the first and
second differential input signals is provided across the
first and second emitter resistors.
According to another aspect of the present
invention, a differential ECL circuit comprises:
first, second and third transistor pairs, each
comprising first and second transistors whose emitters are
connected to each other;
first, second and third constant current sources,
each being connected between the connected emitters of each
respective transistor pair and a first potential terminal;
four load resistors connected between the first
and second transistors' collectors of the first and third
transistor pairs and a second potential terminal;
the first and second transistors' collectors of
the second transistor pair being connected to the second
transistor's collector of the third transistor pair and to
the first transistor's collector of the first transistor
pair, respectively;
means for providing a first differential input
signal between the bases of the second and first
transistors of the first transistor pair;
means for providing a second differential input
signal between the bases of the first and second
transistors of the second transistor pair and between the
bases of the first and second transistors of the third
transistor pair; and
OGC, TECHSGlJRC~
Cd2 1 0{3883
first, second, third and fourth emitter follower
transistors, the emitters of the first and fourth emitter
follower transistors being connected to the first potential
terminal through a first emitter resistor, the emitters of
the second and third emitter follower transistors being
connected to the first potential terminal through a second
emitter resistor, the bases of the first and second emitter
follower transistors being connected to the first and
second transistors' collectors of the first transistor
o pair, respectively, and the bases of the third and fourth
emitter follower transistors being connected to the first
and second transistors' collectors of the third transistor
pair, respectively.
By the differential ECL circuit, a differential
output signal of an AND or NAND logic based on the first
and second differential input signals is provided across
the first and second emitter resistors.
Preferably in any one differential ECL circuit,
all of the transistors are of the same NPN (PNP) type and
the first and second potential terminals are low and high
(high and low) potential terminals, respectively.
In response to the differential input and select
signals, the transistor pairs function as logic circuits
(e.g. XOR, OR, AND).
The differential ECL circuit has no series gates.
Therefore, its speed is high and propagation times from any
input to the output are the same and the circuit is
symmetrical. Also, due to the differential input and
outputs, it has very good noise margin characteristics.
BRIEF DESCRIPTION OF THE DRAWINGS
Embodiments of the present invention will now be
described by way of example only with reference to the
accompanying drawings in which:
Figure 1 is a schematic diagram of a multiplexer
according to the prior art;
,.¢~, ,~,
~A21 0~88S
Figure 2 is a schematic diagram of an XOR circuit
according to the present invention;
Figure 3 is a schematic diagram of an OR circuit
according to the present invention; and
Figure 4 is a schematic diagram of an AND circuit
according to the present invention.
DETAILED DFSCRIPTION OF PREFERRED EMBODIMENT
1. MULTIPLEXER
First, a multiplexer according to the prior art
is described.
I. Structure of the Multiplexer
Referring to Figure 1, the multiplexer comprises
four differential transistor pairs and four constant
current sources, which are connected to the transistor
pairs. In each transistor pair, the emitters of two
transistors lla, llb; llc, lld; lle, llf; and llg, llh are
mutually coupled. The constant current sources comprise
transistors 13a - 13d, the collectors of which are
connected to the coupled emitters of transistor pairs, the
bases of which are connected to a common bias voltage line
15, and the emitters of which are connected to a ground
line 17 through resistors l9a - l9d. The ground line 17 is
the reference potential line in this circuit (a low
potential line). A positive DC voltage Bvg (typically 2.0
volts) is fed to the common bias voltage line 15.
The collectors of the transistors llc, lld, lle
and llf are connected to the collectors of the transistors
llh, lla, llb and llg, respectively. The collectors of the
transistors lla, llb, llg and llh are connected to a
voltage supply line 21 through resistors 23a - 23d,
respectively. Another positive DC voltage VCC (typically
4.5 volts) is fed to the voltage supply line 21.
Input lines 25a - 25h are connected to the bases
of the transistors lla - llh so as to feed first and second
7 CA21 08883
differential input signals and a differential select signal
to the transistor pairs. The input lines 25c and 25f, or
the bases of the transistors llc and llf, are connected to
each other. The input lines 25d and 25e, or the bases of
the transistors lld and lle, are connected to each other.
The multiplexer also comprises an emitter
follower circuit including four transistors 27a - 27d, the
bases of which are connected to the collectors of the
transistors lla, llb, llg and llh, respectively. Both
0 emitters of the transistors 27b and 27d are connected to
the ground line 17 through a resistor 29a. Similarly, both
emitters of the transistors 27a and 27c are connected to
the ground line 17 through a resistor 29b. Output lines
31a and 31b are connected to the emitters of transistors
27b, 27d and 27a, 27c, respectively, so as to provide a
differential output signal across both resistors 29a and
29b.
II. Operation of the Multi~lexer
Each of the first and second differential input
signals and the differential select signal consists of non-
inverted and inverted phase components. The non-inverted
and inverted phase components A and Ab of the first
differential input signal are fed to the input lines 25a
and 25b, respectively. The non-inverted and inverted phase
components B and Bb of the second differential input signal
are fed to the input lines 25g and 25h, respectively. The
non-inverted and inverted phase components S and Sb of the
differential select signal are fed to the input lines 25d,
25e and 25c, 25f, respectively.
When a select signal voltage Vss, which is the
potential difference between the non-inverted and inverted
phase components S and Sb, is negative or positive, the
logic level of the differential select signal is "0" or
~ , respectively. Also, when each of voltages Vsa and Vsb
of the first and second differential input signals is
. ~ ,.. . ...
CA2 1 08~
negative or positive, its logic level is "0" or "1", respectively.
With the voltage Bvg being fed to the bases of
the transistors 13a - 13d, a constant current flows in the
connected emitters of each transistor pair, so that the
total current Io flowing in the collectors of each
transistor pair is constant. In the following description,
when a differential signal is fed to the bases of the
transistor pair, the current Io flows in either one or the
other transistor of that pair. Voltage drops between bases
o and emitters of the transistors are ignored. The four
resistors 23a, 23b, 23c and 23d have the same resistance R.
Base potentials of the transistors 27a, 27b, 27c and 27d
are referred to as Va, Vb, Vc and Vd, respectively.
In response to the input and select signals, the
transistors of the four transistor pairs function as a
differential ECL circuit. Table I shows the relationship
between the input signal voltages, the base potentials of
the transistor pairs and the output voltage for both
negative and positive select signal voltages.
Under the negative select signal voltage Vss,
when both first and second input signal voltages Vsa and
Vsb are negative, the current Io flows in each of the
transistors llb, llc, llf and llh. Since the base-emitters
of the transistors 27c and 27d are reverse-biased, they are
non-conductive. Output potentials V(Y) and V(Yb) at the
output lines 31a and 31b are nearly equal to the base
potentials Vb and Va, respectively, so that the output
signal voltage, V(Y)-V(Yb), is negative (or logic "0").
Likewise, when the first and second input signal voltages
Vsa and Vsb are negative and positive, respectively, the
transistors llb, llc, llf and llg are conductive. When the
first and second input signal voltages Vsa and Vsb are
positive and negative, respectively, the transistors lla,
llc, llf and llh are conductive. When both first and
second input signal voltages Vsa and Vsb are positive, the
transistors lla, llc, llf and llg are conductive.
~2 ~ 0~8~
Under the positive select signal voltage Vss,
when both first and second input signal voltages Vsa and
Vsb are negative, the current Io flows in each of the
transistors llb, lld, lle and llh. When the first and
5 second input signal voltages Vsa and Vsb are negative and
positive, respectively, the transistors llb, lld, lle and
llg are conductive. When the first and second input signal
voltages Vsa and Vsb are positive and negative,
respectively, the transistors lla, lld, lle and llh are
conductive. When both first and second input signal
voltages Vsa and Vsb are positive, the transistors lla,
lld, lle and llg are conductive.
As a result, the logic output signals which
correspond to the first or second input signals selected by
15 the select signal, are provided from the output lines 31a
and 3lb.
2. XOR CIRCUIT
Second, an embodiment XOR circuit according to
20 the present invention is described.
I. Structure of the XOR circuit
As shown in Figure 2, the collectors of the
transistors llc and lld are connected to the collectors of
25 the transistors llb and lla, respectively. The collectors
of the transistors lle and llf are connected to the
collectors of the transistors llh and llg, respectively.
The input lines 25a and 25g, or the bases of the
transistors lla and llg, are connected to each other. The
30 input lines 25b and 25h, or the bases of the transistors
llb and llh, are connected to each other. The input lines
25c and 25f, or the bases of the transistors llc and llf,
are connected to each other. The input lines 25d and 25e,
or the bases of the transistors lld and lle, are connected
35 to each other. The output lines 31a and 31b are connected
to the emitters of transistors 27c, 27d and 27a, 27b,
OG(~ T~ ,~r
CA21 0888;3
respectively. The other connections are the same as those
of the circuit shown in Figure 1.
II. Operation of the XOR circuit
In the XOR circuit shown in Figure 2, compared to
the multiplexer shown in Figure 1, the non-inverted and
inverted phase components B and Bb of the second
differential input signal, instead of the non-inverted and
inverted phase components S and Sb of the differential
select signal, are fed to the bases of the transistors lld,
lle and llc, llf, respectively. The non-inverted and
inverted phase components A and Ab of the first
differential input signal, instead of the non-inverted and
inverted B and Bb of the second differential input signal,
are fed to the bases of the transistors llg and llh,
respectively.
In response to the differential input signals,
the transistors of the four transistor pairs function as a
logic circuit. Table II shows the relationship between the
input signal voltages, the base potentials of the
transistor pairs and the output voltage.
When both first and second input signal voltages
Vsa and Vsb are negative, the current Io flows in each of
the transistors llb, llc, llf and llh. Similarly, when the
first and second input signal voltages Vsa and Vsb are
negative and positive, respectively, the transistors llb,
lld, lle and llh are conductive. When the first and second
input signal voltages Vsa and Vsb are positive and
negative, respectively, the transistors lla, llc, llf and
llg are conductive. When both first and second input
signal voltages Vsa and Vsb are positive, the transistors
lla, lld, lle and llg are conductive.
As a result, the output signals from the output
lines 31a and 31b are of the XOR logic on the basis of the
first and second input signals.
3. OR CIRCUIT
11 CA21 0888~
Third, an embodiment OR circuit according to the
present invention is described.
I. Structure of the OR circuit
As shown in Figure 3, the OR circuit has a
similar circuit structure as the multiplexer shown in
Figure 1. The transistors lle and llf and their related
circuits and connections are deleted. The input lines 25c
and 25g, or the bases of the transistors llc and llg, are
connected to each other. The input lines 25d and 25h, or
the bases of the transistors lld and llh, are connected to
each other. The output lines 31a and 31b are connected to
the emitters of transistors 27b, 27c and 27a, 27d,
respectively.
II. Operation of the OR circuit
In the OR circuit shown in Figure 3, compared to
the multiplexer shown in Figure 1, the non-inverted and
inverted phase components B and Bb of the second
differential input signal, instead of the non-inverted and
inverted phase components S and Sb of the differential
select signal, are fed to the bases of the transistors lld,
llh and llc, llg, respectively. Table III shows the
relationship between the input signal voltages, the base
potentials of the transistor pairs and the output voltage.
When both first and second input signal voltages
Vsa and Vsb are negative, the current Io flows in each of
the transistors llb, llc, and llg. Similarly, when the
first and second input signal voltages Vsa and Vsb are
negative and positive, respectively, the transistors llb,
lld, and llh are conductive. When the first and second
input signal voltages Vsa and Vsb are positive and
negative, respectively, the transistors lla, llc, and llg
are conductive. When both first and second input signal
voltages Vsa and Vsb are positive, the transistors lla, lld
and llh are conductive.
. ~
~ , ~
12 CA21 08883
As a result, the output signals from the output
lines 31a and 31b are of the OR logic on the basis of the
first and second input signals.
5 4. AND CIRCUIT
Fourth, an embodiment AND circuit according to
the present invention is described.
I. Structure of the AND circuit
0 As shown in Figure 4, the AND circuit has a
similar circuit structure as the multiplexer shown in
Figure 1. The transistors lle and llf and their related
circuits and connections are deleted. The input lines 25c
and 25g, or the bases of the transistors llc and llg, are
connected to each other. The input lines 25d and 25h, or
the bases of the transistors lld and llh, are connected to
each other. The output lines 31a and 31b are connected to
the emitters of transistors 27a, 27d and 27b, 27c,
respectively.
II. Operation of the AND circuit
In the AND circuit shown in Figure 4, compared to
the multiplexer shown in Figure 1, the non-inverted and
inverted phase components B and Bb of the second
differential input signal, instead of the non-inverted and
inverted phase components S and Sb of the differential
select signal, are fed to the bases of the transistors llc,
llg and lld, llh, respectively. To the bases of the
transistors lla and llb, the inverted and non-inverted
30 phase components Ab and A, respectively, instead of the non-
inverted and inverted phase components A and Ab of the
first differential input signal, are fed. Table IV shows
the relationship between the input signal voltages, the
base potentials of the transistor pairs and the output
35 voltage.
When both first and second input signal voltages
Vsa and Vsb are negative, the current Io flows in each of
.
13 CA21 08883
the transistors lla, lld, and llh. When the first and
second input signal voltages Vsa and Vsb are negative and
positive, respectively, the transistors lla, llc, and llg
are conductive. When the first and second input signal
voltages Vsa and Vsb are positive and negative,
respectively, the transistors llb, lld, and llh are
conductive. When both first and second input signal
voltages Vsa and Vsb are positive, the transistors llb, llc
and llg are conductive.
AS a result, the output signals from the output
lines 31a and 31b are of the AND logic on the basis of the
first and second input signals.
5. OTHER CIRCUITS
The line 21 may be connected to the ground
terminal (the reference potential terminal) and negative
voltages may be fed to the lines 15 and 17. The circuit's
function is the same as described above.
By replacing all NPN transistors to PNP
transistors and altering the high and low potentials, the
same function circuits as those described above are
provided.
Other logic NOR, NAND and NXOR circuits are
formed where the output signals are inverted.
OGC, TECHS''llRCF
14 CA21 08883
a) ~
~ o o o o
_ ~ I H H O O H O H O
_ V ~ ~ 1~ H H ~ H 1:~ H
- 0~ 1 1 ~ ~ I ~ I ~
O ~ ~ V
O ~ O O
H O O H
U: O O O O I ~ H H ~;
~ H H H H ~ ~ I ~; ~; I
> V V > V ~> V
~V ~ V~ ~V O
Vo
P~
~ H ~ V V ~ V II
O O o o o ~
1~ H p ~ H H H ~ ~ HO O
~; V ~; V ~ ~~ V V ~
V ~ ~ V
O O p~ O
~_ O H O HO O O O H O
H 1~ H 1:~ H H ~C H ~ H
Ul ~V ~ V ~ ~ 'l V ~
-- V UI I I I V~ I ~V I ~ V I
~1 Q~I I V V ~ ~ ~ ~ ~ u ~ V ~'I ~
m ~v ~v ~ v ~ ~v ~ V ~V ~ Vv V
O O O O HO H L) O
H H H H ~ P~ ~ ~; H H
v v I I I I I I a) ~ r
~ ' V~V ~ ~V ~V ~V ~ m ~ ~V ~
V~)~ IIII++++ ~> ~OVV
~V, ~V ~V
U: U
h ~ ~ I + I + I + I + ~ u~ I + I +
U~ , .
~ V ~ I I + + I I + + - V ~ I I + +
OGC, TE~ n~
CA2 1 08883
a) a~
,
v Q v Q
o -- O o ~ o o o
~> ~ H O O O ~> ~> H H H O
P~ H H H I ~ ~ P:; H
O O
V: O O U o
~_ O H H ~ ~ H
Q~ V ~; ~ ,Q-~ ~
a ~ V ,~V, a ~ V V V V
V V
O O
O O O O
~ H _~ H H H
V V V ~ V
I V V V _ ~ I I I V
-- V ~ ~ V V V ~>
~ ~V, O V~ ~V ~V
O O O O O ,~ O O O O
-- H H H H ,¢ H H H H
H ~ l I I I ~
H ~ V V V V > ~> V V V V
H ~V> ~V ~V, ~V H
O O ~ O O
H H ~ H H
U P~ V ~ V U V ~ V P~
t~ I V I V ~ t~ V I V I
~~ V~ ~V, ~> ~> V ~ V
a a
v v
~ o o O o o
H H P~ H H
~VV VV~
a) Q I I V v a~ Q v V I
v V ~ ~ u ~ ~ ~ V v
V V ~ V v
m ~ m
o o
O O H H O O
H H ~; ~ H H
V ~ ~; ~ ~ ~ ~ V
V I I I ~ I I I V
~V, V~ V~ ~V ~V ~V
U: U
~r ~Q ~ ~Q
~ ~ u~ I + I + ~ ~ ~n I + I +
.,, -~
Cl~
JJ
_ V ~ ~ V ~
I I + + ~ U) U~ I I + +
~ \,
.~'
