Note : Les descriptions sont présentées dans la langue officielle dans laquelle elles ont été soumises.
214106~
-
SPECIFICATION
This inventive idea relates to a new method in controlling any line-powered appliance remotely via a
device which acts as a receiver with learning capability. The device is able to learn any key code
transmitted by any home entertainment remote control so that once prog~ g is completed, the
receiver will become dedicated to respond only to the key code that it has just learned. The receiver will
then alter the condition or characteristic of the line voltage that is applied to the appliance accordingly.
Throughout this document, the inventive product will be called Remote Switched Outlet with its
abreviation as RSO.
It is common in devices for controlling line-powered appliances/devices remotely that they have to
provide the user a ~ "~ er and a receiver. The transmitter and the receiver have to be a married pair.
To avoid false signal recognition, the receiver can only decode the signal transmitted by its own
l~n.~ r For controlling many appliances, one ofthe solutions is to have multiple of such married pairs
with di~relll coding. The coding can be accomplished by means of hardware or software. Devices of
such type are, however, inefficient because it is inconvenient and impractical for the user to carry that
many tran~mitters and to decipher the confusion as to which transmitter is for which receiver.
We have found that these disadvantages may be overcome by adding a learning capability to the RSO so
that the user can teach the receiver to respond to a specific con"--and transmitted by any infrared remote
control. Therefore, there is no need to supply the user a dedicated transmitter. Such method allows the
user to make use his/her own remote control not only to control the home entertainment units but also
other light fixtures or any other appliances via this inventive RSO. This method lets the user to configure
any multi-arrangement to their pr~re. ence.
2141064
OPERATION PROCEDURE:
RSO takes all the complicated tasks in itself and leaves the user a simple set of operation as described
below:
RefertoFig. 1:
1. Plug the RSO into the wall outlet. By default, "Learning" LED is lit indicating that it is ready to
learn.
2. Aim your remote control unit to RSO and press a key of your choice until the "Learning" LED
turns off.
3. Plug the appliance into the RSO's output receptacle.
To turn on or off the appliance, you just aim the remote control to the RSO and press the key that you
taught it in step 2. If you want to retrain it with defferent key comm~nd7 press and hold the push button
switch of the RSO for approximately 5 seconds until the "Learning" LED is lit, then follow step 2. If you
wish to turn on or off the appliance locally, you can simply press the push button switch momentarily
(less than 4 seconds.)
2141064
In drawings which illustrate embodiments of the invention,
Figure 1 is a product layout drawing to display the locations of Photo-Sensors, Push Button
Switch, "Learning" LED, Input AC Plug and the Switchable Output Receptacle.
Figure 2 is a block diagram of the RSO design to overview the integration of all major circuitries.
Figure 3a: is a detail sçh~m~tic diagram of AC circuit design.
Figure 3b: is a detail schematic diagram of DC circuit design.
Figure 3c: is a detail schematic diagram of INFR~RED DETECTION design.
Figure 3d: is a detail schematic diagram of MICROPROCESSOR circuit.
Figure 2 displays an overview of the major circuitries comprised of a Power Supply, an Infrared
amplifier/detector, a microcontroller, a Triac Driver and a Triac. The following is circuit description as to
how these circuits function:
AC CIRCUIT: ( Refer to Fig. 3a )
The AC circuit comprises of J2 (an AC input line plug), a Triac Driver U2, a Triac T1, R8, R9, R10,
R13, C14, C15 and an AC switched output Jl.
In this design scheme, the ground of J2 is used as a common ground for the entire circuitry and the hot
line of the AC is chosen to be the switching line. The switching takes place when MTl and MT2 of the
triac are conducted. For the triac Tl to fire and conduct MT1 and MT2, it requires a miniml1m threshold
level of 25mA in between the gate and MT 1. For this reason, MAC 1 5A6FP is chosen to handle 400V ~
15 A load maximum with its trigger current no more than IGT=75mA. The triac Tl is required to be
triggered by the U2 pin 4 continuously at zero crossing to conduct MTl and MT2. U2 is not only an
optocoupler/driver but also a zero crossing device which will fire the Triac only in a region of 9V to 20V.
The MOC3042 is chosen in position of U2. The current is limited by (5v-1.7v)/R11. U2 is turned on
214106~
when PA5 of the micro is going low. The Triac dissipates heat at approx. 1 watt for 1 Amp. of load. The
maximum load could go up to 15 Amps which yields 15 watt of power dissipating. Therefore, a heatsink
is required. Since the specified triac MAC15A6FP (FP package of T0221C) has an isolated ground case
which can be bolted down to the ground plane of the PCB, therefore, heat can be transferred and
escaped to the plug of the external appliance. R13 and C14 form a snubber circuit which will slow down
the rate of rising and falling current so that the triac will be protected in the event of high voltage surge or
kickback current generated from an inductive load.
DC CIRCUIT: ( Refer to Fig. 3b )
The power supply is basically a half wave rectifier accomplished by diode D1. A series capacitor C15 will
step the voltage down and limit the power to 2.5w. After rectification, zener diodes D3 re~ tes the
voltage at lOV which is filtered by C4. Regulator U6 is required to regulate at 5V which is further filtered
by C5. lOV is used for IR circuit and 5V (~ lOmA is used for the microprocessor circuit. During the
sleep mode, the micro draws apl)roxil-lately lOOuA awaiting an interrupt. When it is interrupted by S1 or
output going low on U1-1, more current will be required.
2 1 4 1 0 6 ~
IN~RARED SIGNAL DETECTION CIRCUIT: ( Refer to Fig. 3c )
IRD1 and IRD2 are the SFH 205 type Silicon Planar PrN Photo-Diode. The signal-to- noise ratio of such
photo diode is particularly favorable, even at low ill~lrnin~nces. This type of photodiode is outstanding for
low junction capacitance, high cut-offfrequency and short switching times. The photodiode is particularly
suitable for IR remote control receiver. IRD1 and IRD2 are reverse-biased by R3. When light strikes, it
responses very fast to the changes.
The MC3373 is a spec~ ed high gain amplifier/signal processor bipolar analog IC which provides
signal amplification and pulse shaping needed to couple the signal to the microprocessor U3. In the
carrier mode setup, the MC3373 acts like an AM receiver subsy$em, amplifying the incoming signal,
demod~ ting it, and providing some basic wave shaping of the demodulated envelope. The tuned circuit
at Pin 3 provides the main system selectively reducing random noise interference and permitting
multichannel operation in the same physical area without falsing. In the multichannel case the carriers
must not be ha,l.,ollically related. The bandwidth is determined primarily by C2 and R6 (typically from 30
KHZ to 60 KHZ centering at 40 KHZ). R12 and C6 reduce the gain to stabilize the amplifier. C6 is also a
bypass for 40 KHZ frequency. C3 is further filtering out the high frequency noise. C8 also acts as a peak
hold capacitor. R1 discharges the peak. R1 and C8 form a RC constant for discharging of envelope
detector value.
214106~
MICROPROCESSOR CIRCUIT: ( Refer to Fig. 3d )
Pin 13: Connected to supplied voltage +5V for VDD.
Pin 14: Tied to COM ground.
Pin 15,16: Associated with X1, C12 and C13 to set clock freguency
f=4MHZ.
Pin 1: RESET line is held low at RC constant by R2 and C7.
PAO: Has an internal pull down resistor enabled by software.
Logic high to cause an interrupt.
Pin 6, 7: PA1 and PA2 could be used in the future for additional switches.Pin 4: IRQ active low.
Pin 8: Jumper option; needs to be pulled up if EEPROM is not installed.Pin 3: PB0 serial communication which uses I 2C interface to EEPROM.
Pin 12: PA7 is data line.
Pin 11: PA6 ties to PA5
Pin 9: PA4 provides current sinking for LED1.
Pin 10: PA5 is active low to turn on U2.
EEPROM CIRCUIT:
EEPROM is required to provide memory retension in case of power failure.
2l~lo6~
-
CONTROL WARE
The following is the description of the Control Ware strategy. It is the core design of the inventive RSO.
When the unit is first powered up, The microcontroller will try to load data from the EEPROM. If there
is no data present, it will turn on the Learning LED to indicate that it is ready to receive a new command
code.
Learnin~ st~Pe: At this stage, the microcontroller is awaiting for an incoming signal. When the user
activates a signal by pressing a command key on the remote control. The signal bursts are detected and
decoded as a string of TTL level pulses. The microcontroller will take the ratio of these positive going
pulses and the negative going pulses. The resultants in hexadecimal value will be stored in the
EEPROM.
O~er~tinP st~Pe: From this point on, when there is an interrupt of an incoming signal, the
microcontroller will try to decode and process the ratio of the pulses. The resultant value will be
compared with the previously stored value. If matched, PAS will go low to turn on the triac driver U2
which in turn, will fire the triac. If unm~tc~ed, it remains at its state and continues to wait for an interrupt.
X141061
SOURCE CODES
; IRll.asm
$base 10t
PDRA equ $10
PDRB equ$11
tofr equ 3
tof equ 7
rtifr equ 2
rtie equ 4
org MOR
So~ware Pull Downs - enabled
3-pin oscillator - no
RC oscillator - no
STOP conversions to WAIT - no
;
db % 00~0 1111
COP - enabled
IRQ LOW and edge-, PA3-PA0 HIGH and edge+
Port A IRQ Enable - yes
Low Voltage Reset Enable - YES
;
21410~4
-
; 4 MHz Crystal Resonator used. Timer cycle=2uS; TOF=5 12uS
; Port A
SW1 equ 0
SW2 equ 1
LED equ 4
LED_ equ $10
TRIAC_ equ $60 ; PA5 & PA6
SDA equ 7 ; PA7
SCL equ 0 ; PB0
err equ 1 ; PB1
; flag bits
dmod equ 3
n_bytes equ 16
min_cyc equ 8
max_cyc equ 2*n_bytes-1
rec_dly equ 70
term_pls equ 30
ldly equ 18 ; 5 minute delay
sw2EEd equ n_bytes+2
tmp3 equ $FC ; reused stack area
$FD ; reused stack area
21~1061
org RAM
cycles ds 1
stream ds n_bytes ; array for new stream
ldly_LSB ds 1
tmpO ds 1
tmpl ds 1
Idly_MSB ds 1
tmp2 ds 1
flag ds 1
Ip_width ds 1 ; duration of the low pulse
hp_width ds 1 ; duration of the high pulse
org ROM ; program begins at location $0200. IASM05K
start
Ida #3
sta ddrb ; initialize PB0, PBl as outputs
sta prtb
Ida #$f0 ; software pulldowns on PA3,PA2,PAl,PA0
sta pdra
sta ddra ; now initi~li7e them as outputs
bset LED,prta
bset SDA,prta
Ida #$17
sta tcsr ; RTI on
clr flag ; initflag
21~064
main
bset l,icsr ; clear external interrupt flag
wait
bra main
;
dly256 clrx
dlyx ; X $ lmS delay (~ fosc= 4 MHz; Destroys reg. A, X
Ida #199 ;2c x*(A*10+8)+6cycles
dlyj 1 nop ; 2c --I
nop ; 2c I 10
deca ; 3c I
bne dlyjl ; 3c--I
decx ; 3c
bne dlyx ; 3c
stx cop
rts ; 6c
;
ep_rO
Ida #cycles ; address ptr of eeprom stream data swl
sta tmpO
eeprom_r
bclr SDA,prta ; start condition - SCL should be high
Ida #$AO ;slaveaddr.of24COlA/writeoperation
bsr send8 ; SP=top-7
12
~1~106~
bsr seteeptr ; sendwordaddress
bset SDA,prta ; for Start Condition
bset SCL,prtb
readnb
Ida #$A1 ; slave addr. of 24COlA/ read operation
bclr SDA,prta ; start condition - SCL should be high
bsr send8 ; SP=top-7
Idx #8
bclr SDA,ddra ; data line becomes input for reading
rd_lp
bset SCL,prtb ; clock out data from eeprom
sec ; by default set CARRY
brset SDA,prta,bs3 ; but clear it if SDA line was not high
clc
bs3 rola ; rotate CARRY to A
bclr SCL,prtb ; clockidle state
decx ; -- # of bits to go
bne rd_lp ; morebits?
bclr SDA,prta
bset SDA,ddra ; data line becomes output
bset SCL,prtb ; stop conditionclock
sta tmp3
Ida tmpO
cmp #cycles
bne ncyc
Ida tmp3
sta tmpl
2141~64
cyc
bset SDA,prta ; stop conditiondata
ldx tmpO ; ptr
inc tmpO ; addressptr++
Ida tmp3
cmp ,x ; compare two elements of the arrays
bne cmp_xit ; exit onfirst mi~m~tch
dec tmp 1 ; bit count-2 - there are 2 'bits' per byte
dec tmpl
bpl eeprom_r ; if not last, then check more
brset dmod,flag,sw2pressed ;if sw2 pattern recog.- same as sw2 hit
clr Idly_MSB ; else for swl - disable delayed off
Ida #TRIAC_ ; and, toggle triac on/off
eor prta
sta prta
sl_xit bsr dly256
bsr dly256
bset LED,prta ; turn offLED
nmx rti
cmp_xit ; failed to match swl data but still sw2 can
brset dmo~ fl~ nmx ; sw2 pattern did not match either?
bset dmod,flag ; mark that sw2 pattern is to be checked
bra eep_rO ; sw2 datacomparison
14
21~106~
eteeptr
Ida tmpO ; tmp is RAM byte address
sub #cycles ; [A] is now EEPROM word address (swl)
brclr dmod,flag,send8 ; if sw2 mode, then eeprom ptr is di~ren
add #sw2EEd ; adjust eeprom ptr for sw2 data
send8 ; Shift-out 8 bit data from A (MSBit first)
bclr SCL,prtb
Idx #8
wr_lp asla ; shift MSBit to carry
bcc bsl
bset SDA,prta ; set SDA,prta according to carry
nop
bsl bset SCL,prtb
nop
bclr SCL,prtb
decx
bclr SDA,prta
bne wr_lp
bclr SDA,ddra ; data line becomes input
bset SCL,prtb ; ackn. cycle
nop
exs8 bclr SCL,prtb ; end ackn. cycle
bset SDA,ddra ; data line becomes output
bclr SDA,prta
rts
;
214106~
sav_arr
bclr SDA,prta ; start condition - SCL should be high
Ida #$AO ; slave addr. of 24CO 1 A / write operation
bsr send8 ; SP=top-7
bsr seteeptr
Idx tmpO
lda ,x ; get stream data byte
bsr send8 ; senditto eeprom
bset SCL,prtb ; stop conditionclock
inc tmpO ; addressptr++
Ida tmpO ; ptr
bset SDA,prta ; stopconditiondata
cmp #tmpO ; reached the end of stream data?
beq sl_xit ; if yes, then exit
Idx #10 ; prog~ ""il-g delay
jsr dlyx ; delay
bra sav_arr
set_rec
Ida prta
ora #TRIAC_ ; TRIAC-off
sta prta ; turn offtriac
bclr LED,prta ; LED on
sw_rel
clra
sta cop
Ida #%11 ; wait for swl release
and prta
16
21~1064
bne sw_rel
sl_xit2
jsr dly256
rti
w2pressed
bclr err,prtb ; debug
Ida #Idly ; setupdelay
sta Idly_MSB
clr Idly_LSB
bset dmod,flag ; mark that sw2 was pressed = dmode
Ida #%10010000 ; TRIAC-on, LED-off
bra dbncO
swlpressed ; toggle triac on/offor go to record mode if long pressed
clr Idly_MSB ; else for swl - disable delayed off
bset LED,prta ; turn offLED
bclr dmod,flag ; remember swl not sw2 was hit
mtoggle Ida #TRIAC_ ; toggle triac
eor prta
dbncO sta prta
Ida #rec_dly
sta tmpl
dbnc Idx #50
jsr dlyx
dec tmpl
beq set_rec
Ida #%11
21410~
and prta
bne dbnc
bra sl_xit2
;-
xternal_isr:clra
sta cop
brset SW2,prta,sw2pressed; is SW2 pressed?
brset SW1 ,prta,swlpressed; is SW1 pressed?
new_stream
clr cycles
bil * ; wait until IRQ line goes back high
clra ; clear timer overflow count
wt410 brclr tof,tcsr,c410
inca ; ++ timer overflow count
bset tofr,tcsr ; clear Timer Overflow Flag
cmp #term_pls ; such long high pulse ends the stream
bcc f end
c410 bih wt410 ; wait until IRQ line goes low
Ida timer ; load timer count first
sta tmpO ; save timer value
cyc_beg
clr tmp2 ; clear timer overflow count
wait4hi brclr tof,tcsr,chk_hi
bset tofr,tcsr ; clear Timer Overfiow Flag
inc tmp2
Ida tmp2
18
2I4I 061
cmp #term_pls ; such long high pulse ends the stream
bcc f end
chk_hi bil wait4hi ; wait until IRQ line goes back high
Ida timer ; loadtimercount again
sta tmpl ; save for future high pulse width meas.
I_width sub tmpO ; calculatelo-pulsewidth
bcc Ipwm
dec tmp2
Ipwm bsr merge2
sta Ip_width
hi_puls clr tmp2 ; clear timer overflow count
wait410 brclr tof,tcsr,chk410
inc tmp2
bset tofr,tcsr ; clear timer overflow flag
Ida tmp2
cmp #term_pls ; such long high pulse ends the stream
bcc f end
chk410 bih wait410 ; wait until IRQ line goes low
Ida timer ; load timer count again
sta tmpO ; save for future high pulse width measure
sub tmpl
bcc hpwm
dec tmp2
hpwm
bsr merge2
sta hp_width
Idx #Ip_width
cmp ,x
19
21~10~ 1
bcc div_ax ; ishi-pulselarger?
Ida Ip_width
dx #hp_width
div_ax
clr tmpl ; used for result of div_ax
tst ,x
beq fex ; don't allow divides by 0 ! ! ! !
divx2 sub ,x
inc tmpl ; ++ count
bcc divx2
and #$0F ; don't allow result be more than 4-bits
bra calc_ptr
merge2
Isl tmp2
Isl tmp2
Isl tmp2
Isra
Isra
Isra
Isra
Isra
ora tmp2
rts
f end Ida cycles
cmp #min_cyc
2~106~
bcc feOOO
fex rti
feOOO brset LED,prta,fejOO1; end recording mode if on
Ida #cycles ; address ptr of eeprom
sta tmpO
Jmp sav_arr
fejOO1
bclr dmod,flag ; mark that swl pattern is checked 1st
jmp eep_rO ; compares stream and refer
alc_ptr
lda cycles ; = bit #
cmp #max_cyc
bcc f end
Isra ; #bits/2 to get offset byte
add ~ ealll ; point to array byte
tax ; x = address pointer
lda tmpl
brclr O,cycles,even ; pack the 2 data ratios in 1 byte of stream
lda tmp 1 ; odd - means 2nd of two ratios in the byte
ora ,x
bra svnib
even Isla ; even - means 1 st of two ratios in the byte
lsla
lsla
Isla
214106~
vnib
sta ,x
inc cycles ; increment cycle counter
jmp cyc_beg ; start newcycle
**********************************************************************
rti_serv
clra
sta cop
tst Idly_MSB
beq ex_rti
rtiO 1 dec Idly_LSB
bne ex_rti
dec Idly_MSB
bne ex_rti
Ida #%11110000 ; TRIAC-off, LED-off
sta prta ; turn offtriac
ex_rti
bset rtifr,tcsr ; clear RTI Flag
ti
***********************************************************************
org Vectors ; vectors begin at $03F8
2141064
dw rti_serv ; rti is used for long delay (delayed off)
dw external_isr ; external interrupt service routine
dw start ; there is no swi
dw start ; resetvector
~14106~
LST ~ILE
IR11.ASM Assembled with IASM
1; IR11.asm
2; Remote Switched Outlet
3; Remote Switched Wall Switch
4; Project Started on July 2, 1994
5; Project completed on Nov. 30, 1995
6;
7;
8 ;
9;
10;
11; Version 11 [IR_11]
12;
13 ;
14; 1994
16
17
18
0200 19 $base 10t
0200 21 PDRA equ $10
0200 22 PDRB equ$11
0200 23 tofr equ3
0200 24 tof equ 7
0200 25 rtifr equ2
24
2l4ln6 Z
0200 26 rtie equ4
27
0017 28 org MOR
29
30; Software Pull Downs - enabled
31 ; 3-pin oscillator - no
32; RC oscillator - no
33; STOP conversions to WAIT - no
34;
00170F 36 db%0000 11::
38;
37
39 ; COP - enabled
40; IRQ LOW and edge-~ PA3-PA0
HIGH and edge+
41 ; Port A IRQ Enable - yes
42; Low Voltage Reset Enable - YES
43;
44; 4 MHz Crystal Resonator used. Timer cycle=2uS; TOF=512uS
46; Port A
0018 47 SW1 equ 0
0018 48 SW2 equ 1
0018 49 LED equ 4
0018 50 LED_ equ $10
0018 51 TRIAC_ equ$60 ;PA5&PA6
0018 52 SDA equ 7 ; PA7
2I4106 1
53
0018 54 SCL equ O ; PBO
0018 55 err equ 1 ;PB1
56
57; flag bits
0018 58 dmod equ 3
59
0018 60 n_bytes equ 16
0018 61 min_cyc equ 8
0018 62 max_cyc equ 2*n_bytes-1
0018 63 rec_dly equ 70
0018 64 term_pls equ 30
0018 65 Idly equ 18 ; 5 minute delay
0018 66 sw2EEd equ n_bytes+2
0018 67 tmp3 equ $FC ; reused stack area
68; $FD ; reused stack area
69
OOEO 70 org RAM
71
OOEO 72 cycles ds 1
OOEl 73 stream ds n_bytes ; array for new stream
OOFl 74 Idly_LSB ds 1
OOF2 75 tmpO ds 1
OOF3 76 tmpl ds 1
OOF4 77 Idly_MSB ds 1
OOF5 78 tmp2 ds 1
OOF6 79 flag ds 1
OOF7 80 Ip_width ds 1 ; duration of the low pulse
26
214106q
00F8 81 hp_width ds 1 ; duration of the high pulse
82
83
0200 84 org ROM ; programbegins at
location $0200. IASMOSK
start
0200 A603 86 lda #3
0202 B705 87 sta ddrb ; initi~ e PB0, PBl as outputs
0204 B701 88 sta prtb
89
0206A6F0 90 lda #$f0 ;softwarepulldownsonPA3,PA2,PAl,PA0
0208 B710 91 sta pdra
020A B704 92 sta ddra ; now initialize them as outputs
020C 1800 93 bset LED, prta
020E lE00 94 bset SDA, prta
0210 A617 95 Ida #$17
0212 B708 96 sta tcsr ; RTI on
0214 3FF6 97 clr flag ; init flag
98 main
0216 120A 99 bset l,icsr ; clear external interrupt flag
0218 8F 100 wait
0219 20FB 101 bra main
102
103
104
105
021B 5F 106 dly256 clrx
2l~lo6l
107 dlyx ; X * lmS delay (~ fosc= 4 M:Hz; Destroys
021CA6C7 108 Ida #199 ;2c x*(A*10+8)+6cycles
021E 9D 109 dlyjl nop ; 2c --I
021F 9D 110 nop ; 2c I 10
0220 4A 111 deca ; 3c
0221 26FB 112 bne dlyjl ; 3c--I
0223 5A 113 decx ; 3c
0224 26F6 114 bne dlyx ; 3c
0226 CF03F0 115 stx cop
0229 81 116 rts ; 6c
117
118 ; ---- -- -- ---- ------
119
120 eep_rO
022A A6E0 121 lda #cycles; address ptr of eeprom stream data swl
022C B7F2 122 sta tmpO
123 eeprom_r
022E lFOO 124 bclr SDA,prta ; start condition- SCL shouldbehigh
0230 A6A0 125 Ida #$AO ; slave addr. of 24COlA / write operation
0232 AD62 126 bsr send8 ; SP=top-7
0234 AD57 127 bsr seteeptr ; send word address
0236 lEOO 128 bset SDA,prta ; for StartCondition
0238 1001 129 bset SCL,prtb
130 readnb
023A A6A1 131 Ida #$A1; slave addr. of 24COlA / read operation
023ClF00 132 bclr SDA,prta ;startcondition-SCL shouldbehigh
023E AD56 133 bsr send8 ; SP=top-7
0240 AE08 134 Idx #8
2I91 064
0242 lF04 135 bclr SDA,ddra; data line becomes input for reading
136 rd_lp
02441001 137 bset SCL,prtb ;clockoutdatafrom eeprom
0246 99 138 sec ; by default set CARRY
0247 OEOOO1 139 brset SDA,prta,bs3 ; but clear it if SDA
line was not high
024A 98 140 clc
024B 49 141 bs3 rola ; rotate CARRY to A
024C 1101 142 bclr SCL,prtb ; clock idle state
024E 5A 143 decx ; -- # of bits to go
024F 26F3 144 bne rd_lp ; more bits?
0251 lFOO 145 bclr SDA,prta
0253 lE04 146 bset SDA,ddra ; datalinebecomes
output
0255 1001 147 bset SCL,prtb ; stop condition clock
0257 B7FC 148 sta tmp3
0259 B6F2 149 Ida tmpO
025B AlEO 150 cmp #cycles
025D 2604 151 bne ncyc
025F B6FC 152 Ida tmp3
0261 B7F3 153 sta tmpl
154 ncyc
0263 lEOO 155 bset SDA,prta ; stop conditiondata
0265 BEF2 156 Idx tmpO ; ptr
0267 3CF2 157 inc tmpO ; address ptr++
0269 B6FC 158 Ida tmp3
026B F1 159 cmp ,x ; compare two elements
of the arrays
29
21~ 1 06~
026C 2618 160 bne cmp_xit ; exit on first mismatch
026E 3AF3 161 dec tmpl ; bit count-2 - there
are 2 'bits' per byte
0270 3AF3 162 dec tmpl
02722ABA 163 bpl eeprom_r ;ifnotlast,then
check more
164
0274 06F675 165 brset dmod,flag,sw2pressed ;if sw2 pattern
recog.- same as sw2 hit
0277 3FF4 166 clr Idly_MSB; else for swl - disable delayed off
0279 A660 167 Ida #TRIAC_ ; and, toggle triac on/off
027B B800 168 eor prta
027D B700 169 sta prta
027FAD9A 170 sl_xit bsr dly256
0281 AD98 171 bsr dly256
0283 1800 172 bset LED,prta ;turnoffLED
0285 80 173 nmx rti
174 cmp_xit ; failed to match swl
data but still sw2 can
0286 06F6FC 175 brset dmo~,fl~g,nmx ; sw2 pattern did not
match either?
0289 16F6 176 bset dmod,flag ; mark that sw2 pattern
is to be checked
028B 209D 177 bra eep_rO ; sw2 data comparison
178
179;
180 seteeptr
2l4lo6~
028D B6F2 181 Ida tmpO ; tmp is RAM byte address
028F AOE0 182 sub #cycles ; [A] is now EEPROM word
address (swl)
029107F602 183 brclr dmod,flag,send8 ;ifsw2mode,then
eeprom ptr is dirreI enl
0294 AB12 184 add #sw2EEd; adjust eeprom ptr for
sw2 data
185 send8 ; Shift-out 8 bit data
from A (MSBit first)
0296 1101 186 bclr SCL,prtb
0298 AE08 187 Idx #8
029A 48 188 wr_lp asla ; shift MSBit to carry
029B 2403 189 bcc bsl
029D lE00 190 bset SDA,prta; set SDA,prta according
to carry
029F 9D 191 nop
02A0 1001 192 bsl bset SCL,prtb
02A2 9D 193 nop
02A3 1101 194 bclr SCL,prtb
02A5 5A 195 decx
02A6 lF00 196 bclr SDA,prta
02A8 26F0 197 bne wr_lp
02AA lF04 198 bclr SDA,ddra ; data line becomes
02AC 1001 199 bset SCL,prtb ; ackn. cycle
02AE 9D 200 nop
02AF1101 201 exs8 bclr SCL,prtb ;endackn cycle
02Bl lE04 202 bset SDA,ddra ; datalinebecomesoutput
02B3 lF00 203 bclr SDA,prta
21 1106'1
02B5 81 204 rts
205;
206
207 sav_arr
02B6 lFOO 208 bclr SDA,prta ; start condition - SCL should be high
02B8 A6A0 209 Ida #$AO ; slave addr. of 24COlA / write operation02BA ADDA 210 bsr send8 ; SP=top-7
02BC ADCF 211 bsr seteeptr
02BE BEF2 212 Idx tmpO
02CO F6 213 Ida ,x ; get stream data byte
02Cl ADD3 214 bsr send8 ; send it to eeprom
02C3 1001 215 bset SCL,prtb ; stop conditionclock
02C5 3CF2 216 inc tmpO ; address ptr++
02C7 B6F2 217 Ida tmpO ; ptr
02C9 lEOO 218 bset SDA,prta ; stop condition data
02CB AlF2 219 cmp #tmpO ; reached the end of
stream data?
02CD 27B0 220 beq sl_xit ; if yes, then exit
02CF AEOA 221 Idx #10 ; prog~ "~ing delay
02Dl CD021C 222 jsr dlyx ; delay
02D4 20E0 223 bra sav_arr
224
225 set_rec
02D6 B600 226 Ida prta
02D8 M60 227 ora #TRIAC_ ; TRIAC-off
02DA B700 228 sta prta ; turn off triac
02DC 1900 229 bclr LED,prta ;LED on
~141 06~
230 sw_rel
02DE 4F 231 clra
02DF C703F0 232 sta cop
02E2A603 233 Ida #%ll ;waitforswl release
02E4 B400 234 and prta
02E6 26F6 235 bne sw_rel
236 sl_xit2
02E8 CD021B 237 jsr dly256
02EB 80 238 rti
239
240 sw2pressed
02EC 1301 241 bclr err,prtb ; debug
02EE A612 242 Ida #Idly ; setup delay
02FO B7F4 243 sta Idly_MSB
02F2 3FF1 244 clr Idly_LSB
02F4 16F6 245 bset dmod,flag ; markthat sw2was pressed=dmode
02F6 A690 246 Ida #%10010000 ; TRIAC-on, LED-off
02F8200A 247 bra dbncO
248
249 swlpressed ; toggle triac on/offor go to record
02FA 3FF4 250 clr Idly_MSB; else for swl - disable delayed off
02FC 1800 251 bset LED,prta ; turnoffLED
02FE 17F6 252 bclr dmod,flag ; remember swl not sw2 was hit
0300 A660 253 mtoggle lda #TRIAC_ ; toggle triac
0302 B800 254 eor prta
0304 B700 255 dbncO sta prta
0306 A646 256 Ida #rec_dly
0308 B7F3 257 sta tmpl
21410~ 1
030A AE32 258 dbnc Idx #50
030C CD021C 259 jsr dlyx
030F 3AF3 260 dec tmpl
0311 27C3 261 beq set_rec
0313 A603 262 Ida #%11
0315 B400 263 and prta
0317 26F1 264 bne dbnc
0319 20CD 265 bra sl_xit2
266;
267 external_isr:
03 lB 4F 268 clra
031C C703F0 269 sta cop
031F0200CA 270 brset SW2,prta,sw2pressed;is SW2pressed?
0322 OOOOD5 271 brset SWl,prta,swlpressed; is SWl pressed?
272 new_stream
0325 3FE0 273 clr cycles
0327 2EFE 274 bil * ; wait until IRQ line goes back high
0329 4F 275 clra ; clear timer overfiow count
032A OF0807 276 wt41o brclr tof,tcsr,c410
032D 4C 277 inca ; ++ timer overflow count
032E 1608 278 bset tofr,tcsr ; clear Timer Overflow Flag
0330 Al lE 279 cmp #termQls ; such long high pulse
ends the stream
0332 2469 280 bcc f end
0334 2FF4 281 c41o bih wt41o ; wait until IRQ line goes low
282
0336 B609 283 Ida timer ; load timer count first
0338 B7F2 284 sta tmpO ; save timer value 285 cyc_beg
34
21~106~
033A 3FF5 286 clr tmp2 ; clear timer overflow count
033C OF080A 287 wait4hi brclr tof,tcsr,chk_hi
033F 1608 288 bset tofr,tcsr ; clearTimerOverflowFlag
0341 3CF5 289 inc tmp2
0343 B6F5 290 Ida tmp2
0345 Al lE 291 cmp #term_pls ; such long high pulse ends the stream
03472454 292 bcc f end
0349 2EF1 293 chk_hi bil wait4hi; wait until IRQ line goes back high
034B B609 294 Ida timer ; load timer count again
034D B7F3 295 sta tmpl ; save for future high pulse width meas.
034F BOF2 296 I_width sub tmpO ; calculate lo-pulse width
0351 2402 297 bcc Ipwm
0353 3AF5 298 dec tmp2
0355 AD38 299 Ipwm bsr merge2
0357 B7F7 300 sta Ip_width
0359 3FF5 301 hi~uls clr tmp2 ; clear timer overflow count
035B OF080A 302 wait410 brclr tof,tcsr,chk410
035E 3CF5 303 inc tmp2
0360 1608 304 bset tofr,tcsr ; clear timer overflow flag
0362 B6F5 305 Ida tmp2
0364 A1 lE 306 cmp #term_pls ; such long high pulse ends the stream
03662435 307 bcc f end
0368 2FF1 308 chk410 bih wait410 ; wait until IRQ line goes low
036A B609 309 Ida timer ; load timer count again
036C B7F2 310 sta tmpO ; save for future high pulse width measure
036E BOF3 311 sub tmpl
0370 2402 312 bcc hpwm
0372 3AF5 313 dec tmp2
~1 41 064
314 hpwm
0374 AD19 315 bsr merge2
0376 B7F8 316 sta hp_width
0378 AEF7 317 Idx #Ip_width
037A Fl 318 cmp ,x
037B 2404 319 bcc div_ax ; is hi-pulse larger?
037D B6F7 320 Ida Ip_width
037F AEF8 321 Idx #hp_width
322 div_ax
0381 3FF3 323 clr tmpl ;usedforresultofdiv_ax
0383 7D 324 tst ,x
0384 27 lD 325 beq fex ; don't allow divides by 0 ! ! ! !
0386 F0 326 divx2 sub ,x
0387 3CF3 327 inc tmpl ; ++ count
0389 24FB 328 bcc divx2
038B A40F 329 and #$0F ; don't allow result be more than 4-bits
038D 2024 330 bra calc_ptr
331
332
333 merge2
038F 38F5 334 Isl tmp2
0391 38F5 335 Isl tmp2
0393 38F5 336 Isl tmp2
0395 44 337 Isra
0396 44 338 Isra
0397 44 339 Isra
0398 44 340 Isra
0399 44 341 Isra
36
2:L~1064
039A BAF5 342 ora tmp2
039C 81 343 rts
344
039DB6E0 345 f end lda cycles
039F A108 346 cmp #min_cyc
03A1 2401 347 bcc feOOO
03A3 80 348 fex rti
349
03A4 080007 350 feOOO brset LED,prta,fejOOl; end recording mode if on
03A7A6E0 351 lda #cycles ;addressptrofeeprom
03A9 B7F2 352 sta tmpO
03AB CC02B6 353 jmp sav_arr
354 fejOOl
03AE17F6 355 bclr dmod,flag ;markthatswlpatternischeckedlst
03BO CC022A 356 jmp eep_rO ; compares stream and refer
357
358
359 calc_ptr
03B3 B6E0 360 Ida cycles ; = bit #
03B5 AllF 361 cmp #max_cyc
03B7 24E4 362 bcc f end
03B9 44 363 lsra ; #bits/2 to get offset byte
03BA ABEl 364 add ~,ea." ; point to array byte
03BC 97 365 tax ; x= address pointer
03BD B6F3 366 Ida tmpl
03BF OlE005 367 brclr O,cycles,even; pack the 2 data ratios
in 1 byte of stream
03C2 B6F3 368 Ida tmpl ; odd - means 2nd of two ratios in the byte
2~106~
.
03C4 FA 369 ora ,x
03C5 2004 370 bra svnib
03C7 48 371 even Isla; even - means 1st oftwo ratios in the byte
03C8 48 372 lsla
03C9 48 373 Isla
03CA 48 374 Isla
375 svnib
03CB F7 376 sta ,x
03CC 3CE0 377 inc cycles ; increment cycle counter
03CE CC033A 378 jmp cyc_beg ; start new cycle
379
380
381
382
383 *********************************************************
**********************
384
385 rti_serv
03D1 4F 386 clra
03D2 C703F0 387 sta cop
03D5 3DF4 388 tst Idly_MSB
03D7 270C 389 beq ex_rti
03D9 3AF1 390 rtiO1 dec Idly_LSB
03DB 2608 391 bne ex_rti
03DD 3AF4 392 dec Idly_MSB
03DF 2604 393 bne ex_rti
03E1 A6F0 394 Ida #%11110000 ; TRIAC-off, LED-off
03E3 B700 395 sta prta ; turn offtriac
2141064
,
396 ex_rti
03E5 1408 397 bset rtifr,tcsr ; clearRTIFlag
03E7 80 398 rti
399
400 ******$*****************
**********************
03F8 401 org Vectors ; vectors begin at
$03F8
03F8 03D1 402 dw rti_serv; rti is used for long delay (delayed off)
03FA 03 lB 403 dw external_isr ; external interrupt service routine
03FC 0200 404 dw start ; there is no swi
03FE 0200 405 dw start ; reset vector
406
407
Symbol Table
BS 1 02A0
BS3 024B
C4LO 0334
CALC_PTR 03B3
CHK4LO 0368
CHK_HI 0349
CMP_XIT 0286
CYCLES OOE0
CYC_BEG 033A
DBNC 030A
DBNC0 0304
39
2141~6~
DIVX2 0386
DIV_AX 0381
DLY256 021B
DLYJl 021E
DLYX 021C
DMOD 0003
EEPROM_R 022E
EEP_R0 022A
ERR 0001
EVEN 03C7
EXS8 02AF
EXTERNAL_ISR 03 lB
EX_RTI 03E5
FE000 03A4
FEJ001 03AE
FEX 03A3
FLAG 00F6
F_END 039D
HI_PULS 0359
HPWM 0374
HP_WIDTH 00F8
LDLY 0012
LDLY_LSB 00Fl
LDLY_MSB 00F4
LED 0004
LED 0010
LPWM 0355
LP_WIDTH 00F7
2~lo6~
L_WIDTH 034F
MAIN 0216
MAX_CYC 001F
MERGE2 038F
MIN_CYC 0008
MTOGGLE 0300
NCYC 0263
NEW_STREAM 0325
NMX 0285
N_BYTES 0010
PDRA 0010
PDRB 0011
RD_LP 0244
READNB 023A
REC_DLY 0046
RTI01 03D9
RTE 0004
RTIFR 0002
RTI_SERV 03Dl
SAV_ARR 02B6
SCL 0000
SDA 0007
SEND8 0296
l K 028D
SET_REC 02D6
SL_XIT 027F
SL_XIT2 02E8
START 0200
41
21~106~
STREAM 00El
SVNIB 03CB
SWl 0000
SWlPRESSED 02FA
SW2 0001
SW2EED 0012
SW2PRESSED 02EC
SW_REL 02DE
TERM_PLS 001E
TMP0 00F2
TMP 1 00F3
TMP2 00F5
TMP3 00FC
TOF 0007
TOFR 0003
TRIAC 0060
WAIT4HI 033C
WAIT4LO 035B
WR_LP 029A
WT4LO 032A
42
