Note : Les descriptions sont présentées dans la langue officielle dans laquelle elles ont été soumises.
CA 02444239 2003-10-24
HOUSING E'OR CONNECTION TO BOTH BROADBAND AND NARROWBAND
NETWORKS AS A SHELF IN A TELECO ICATIONS RACFC
BACKGROUrTD OF THE II~TV'EI~TIOI3
1. Technical Field of the Tnvention
The present invention relates to providing high~-
speed communications services to ordinary residences and
small businesses on digital subscriber lines.
2. Backctround of the Invention
The sudden emergence of the Internet has produced an
urgent demand for high-speed. communications services to
ordinary residences and small businesses. These services
are distinguished by bursty data patterns and
asymmetrical data transfer - far mare information sent
toward the subscriber premises than received from it. A
partial response to this need, at least om the physical
signal level, has been found in new "xDSL'° transmission
technologies, such as ADSL (Asymmetric Digital Subscriber
Line). These have recently become sophisticated enough
to allow dynamic bit-rate adaptation on each subscriber
line, so that a wide range of loop lengths can be
accommodated. But all this variability (bursty data,
dynamic bit rates, etc.) has made it nearly impossible to
predict, control, manage, or guarantee the Quality of
Service {~oS) provided to each subscriber, as required
for a viable commercial service.
Several companies are working on ADSL products using
DMT (Discrete Multi-Tone) and/or CAP (Carrier-less
Amplitude Phase Modulation) technology - each with their
own equipment configurations and target applications.
These products simply multiplex the AI3SL data streams
1
CA 02444239 2003-10-24
~Lcgetl2er wi~~~r little or i~c~: ==learible. baudwid.th ~~.wi-~'~:~~o~? anc~.
~~o t~os management featur es o
SiII~I~iAR~I t~~' THE ll~l~tTEIdTIE7~I
.fin obj ect of the present invention is to solve the
management problems described above by combining the data
management features of ATM (Asynchronous Transfer Mode)
with the physical--layer transmission flexibility of xDSL.
Another abject of the present invention is to
provide an architecture for a telecommunications system
in which plain old telephone service and a broadband
digital service are simultaneously provided to individual
subscribers on conventional transmission lines already
deployed for telephony.
Still another object of the present invention is to
provide such an architecture in such a way as to provide
maintainability of the digital subscriber line hardware
without interfering with lifeline telephony service to
subscribers.
Yet another object of the present invention is to
provide the practical hardware components capable of
carrying out the above objects for such,a system.
F~ccording to a first aspect of the present
invention, a shelf fog use among a plurality of shelves
in a rack for use in a telecommunications system for
providing both narrowband and broadband services to a
plurality of subscriber premises, comprising a housing
~or connection to a narrowband network and for connection
to a broadband network for connecting said narrowband
network and said broadband network to said plurality of
subscriber premises via a corresponding plurality of
twisted copper pairs, wherein said housing includes
plural sections including an upper section for housing in
a central portion thereof a plurality of lowpass ffilter
cards with connectors thereon for insertion in a
backplane of said housing, and wherein. said upper portion
2
CA 02444239 2003-10-24
of said housing also has end portions reserved for
connecting said narrowband network and said plurality of
twisted copper pairs, and a lower section for housing a
plurality of line termination cards in a central portion
thereof, each with connectors thereon for insertion in
said backplane of said housing, and wherein said lower
section includes at least one and portian reserved for at
least one network termination card for oable connection
to said broadband networks
According to a second aspect of the pz:esent inventian,
there is provided a housing, for connection to a narrowband
network and for connection to a broadband network for
connecting said narrowband network and said broadband
network to a plurality of subscriber premises Via a
corresponding plurality of tv~~isted copper pairs, wherein
said housing includes plural sections including:
a first section Tor housing i~:: a central portion
thereof a plurality of lo~~~pass filter cards with connectors
thereon for Insertion in a backplane of said housing, and
wherein said first section o' said housing also has end
potions reserved for connecting said narrowband network
and said plurality of twisted copper pairs; and
a second section for housing a plurality of line
termination cards in a central portion thereof, each with
connectors thereon for insertion in said backplane of said
housing, and wherein said second section (20) includes at
least one end oortion reserved far at least one network
terminatio-n card for said cannection to said broadband
network.
According to a third aspect of the present invention,
~0 there is nrcVided a shelf, comprising:
3
CA 02444239 2003-10-24
a housing for connection to a narrowband network and
for connection to a broadband network: for connecting said
narrcwband _network and said brcadband network to said
plurality of su'.oscriber premises via a corresponding
plurality of twisted pairs, wherein said housing includes
plural sections including:
a first sectr~on for housing in a central portion
thereof a volurality of ,.owpass filter cards with connectors
thereon for insertion in a backplane of said housing, and
wherein said first section of said riousing also has end
portions reserved for connecting said narrowband network
and said plurality of twisted copper pairs; and
a second section for housing a p1_uraiity of line
termination cards in a central portion thereof, each with
connectors thereon for insertion in said backplane of said
housing, and wherein said second section includes at least
one end portion reserved for at least one network
termination card fo~w connec';~ion to said broadband network.
According to a fourth aspect of one present invention,
there is provided_ a shelf for use among a plurality of
shelves in a rack for use in a telecommunications system
for providing both narrowband and broadband services to a
plurality of subscrvber premises; comp.r~_sing:
a housing for connection to a narrowband network and
for connection to a broadband network for connecting said
narrowband network and said broadband network to said
plurality of subscriber premises V;~a a corresponding
plurality of twisted copper pairs, wherein said :housing
includes pluvial sections inc'uding:
an upper section for housing in a central portion
thereo- a plurality of lowpass filter cards with connectors
4
CA 02444239 2003-10-24
thereon for insertion in a backplane of said housing, and
wherein said upper portion of said ,sousing also has end
portions reserved for connecting said narrowband network
and said plurality of twisted copper pairs; and
a lower section for housing a plurality of line
termination cards in a central portion thereof, each with
connectors thereon for insertion in said backplane of said
housing, and wherein said lower section includes at least
one end portion reserved for at least one network
termination card for cable connection to said broadband
network.
Thus, the present invention provides a high-speed
digital access communications system, covering a wide
range of configurations and applications, using new
packet and xDSL technologies with the possibility to
offer subscribers the variety of QoS classes defined, f or
example, in the various ATM Forum specifications< Since
it uses the existing copper cable plant already deployed
throughout the developed world, the system is economical
allowing Local Exchange Carriers to compete with
alternative service providers such as CATV companies
(which are deploying heavily overbooked cable modem
technology on their coax cable plant)~ The system also
preserves the reliability and simplicity of analog
"lifeline's POTS, so that subscribers and telephone
operating companies are not required °~o change the way
voice services are providedd
5
CA 02444239 2003-10-24
6
These and other objects, features and advantages of
the present invention will become more apparent in light
of the following detailed description of a best mode
CA 02444239 2003-10-24
-C..'TllS~Uda_111~g't''s~ '~~1~Y'~Cta_~. :~~ ~_'J1't_I~'Lrc~.l'.:eC.
1~°~ °~a~J"~~. ~.G.C::C3~E1~"J2.s~~~'~~'1C~
dra~TlT'~;~
DRIEF ~~ESC~IfTiOH OF THE iJRAVJihI'G
Fig ~. illustrates a basic xDSL shelf laye~ut, which
may be an. ADSL shelf in the embodiment illustrated, fo~
uses for example, ~_n an ATI~ subscriber access multiplexer
(ASAIwI) system, according to the present invent ionW
Fig. lA shows the shelf of Fig. 2 in detail, and in
particular shows how front access is achieved.
Fig. 1B shows a standard configuration of xDSL
shelves in a Central Office (CO) rack, according to the
present invention.
Fig. 1C shows a shelf without cards, with various
connectors for connection to the backplane, a terminal
block, etc.
Fig. 1D shows a side view of a shelf, according to
the present invention<
Fig. 1E shows a rack, according to the present
invention, for housing a selected number of shelves,
according to the present invention.
Fig. 2 shows a functional block diagram of the
present invention whereby high speed packetized data in,
e.g., ATM format is combimed with traditional POTS
service, e.g., in an xDSL-shelf which may be an ADSL
shelf in the embodiment illustrated for providing the
means whereby POTS lifeline services on a twisted copper
pair are overlaid with high speed digital services for
communicating high bandwidth services to a customer~s
premises.
3 O Fig . 3 shows further details of ~.he xDSL shelf of
Fig. 2 which carp b;e an ADSL shelf, as illustrated, fear
serving a plurali~.y of customer prem~_ses, in this c'wase
with up t.o 48 lanes.
7
CA 02444239 2003-10-24
Fi~~ :3z~. .i.l_l.t~~~:i2te~; r~. ~'..a't~~ 2c~':~E's~ i.'tlC3~:~~.Jd
LIZ
pric~riti zed date wherein guarantee. ba~-~dwid~LYs and
o2rer booing in a same QoS cuss is miix:ed witrx a fairness
feature, according to tl~e present inventions
Fig. 4 shows additiorsal fle~ibilzt~r built. into an
xDSL shelf which is shown here in twa diffez~ent
embodiments, one called a 'hub' and the other a 'remote
,
for use in an ASANI system, according 'to the present
invention.
Fig. 4A shows LT-LPF BPA wiring and LT-BPA
transceivers for supporting the 'hub" applicat ions with
DS-3 links to 'remote" shelves, according to the present
invention.
Fig. 4D shows wiring with non-redundant DS-3 LT card
15 installed for the 'hub" application, according to the
present invention.
Fig. 4G shows redundant DS-3 LTs on the same shelf
in a 'hub" application, according to the present
invention.
20 Fig. 4D shows switch signal wiring for redundant DS-
3 LTs in the same shelf for a "hub" application,
according to the present invention.
Fig. 4E shows a solution for DS-3 LT card redundancy
in separate shelves for a "hub" application, so as to
25 provide IQ bus redundancy, according to the present
invention, where only a single IQ bus is provided per
shelf .
Fig. 5 shows how the hub and remotes of Fig. ~ could
be deployed in one embodiment of an AS~1.I~ system,
3~ according to the present inventions
Fig ~ shows four ~DSL shelves 5.n one rack of an
ASANI systemp the shelves may be ADSL shelves as
illustrated, for use with redundant IQ ~aus extender cards
~E~T~ in arA 'A/8' bank switchover scheme to extend the TQ
8
CA 02444239 2003-10-24
bus to additional whelves ~i~.c:~ serrvve r. a . g ~ . ~air~h.
v:.h_r_ ee suc:h.
s~acksF up to 57G subscribers,
Figo 7A shows a schematic: bloc's d~_agraru of a lowpa s
filter card for insertion in ;~r~e of the slots 2~ in the
upper section 22 of the shelf 10 of Fig. 1.
Fig. 7B shows a side view of such a low~~ass filter
card with four lowpass filter/splitter circuits thereon,
for insertion in a slot of the upper portion 22 of the
shelf 10 of Fig. 1.
Fig. 7C shows a front view of the card of Fig. 7B,
as seen from the front of the shelf of Fig. 1.
rig. 7D shows an optional separate splitter shelf,
according to the present invention.
Fig. 8 shows a separate splitter shelf, such as that
of Fig.. 7D, used to add xDSL service to an existing DLC,
according to the present invention.
Fig. 8A shows an ADSL remote cabinet, such as shown
in Fig. 8 in more detail, wherein the configuration shows
supports up to 96 lines in a type 3002 cabinet.
Fig. 9 shows a compact xDSL shelf, in this case, an
ADSL RAM (remote access mux) shelf, according to the
present invention.
Fig. l0 shows a functional block: diagram of an LT
card, according to the present invention.
Fig. 10A shows a front view of an LT card.
Fig. lOB shows a side view of an LT card.
Fig. 11 shows a simplified block diagram
illustration of a channel of an LT card in a shelf
connected to a subscriber ADSL modem via a twisted pair,
according to the present invention.
Fig. 12 shows an example of frequency allocation of
the telephony and the ~ANI~modulated subchannels {tones)
individually optimized as a function of line impairments,
aCCOrding tO t~'le present in~Y'E.'n'~:7.f~rl.
CA 02444239 2003-10-24
Fic~. 13A shcaws a simp_l..i:C~.ed ~loc7~. diagram c~f an AD~L
modem fap° use a.T-~ a subscz°~.be:~~as ~f~ren~isese according
to
the ~re~s~'xZt inV'2T°Tt i aTio
Fig. 13B shows the a~cteL°a.or of a physical. embodiment
of an ADSL modem such as shown iT~ Fi.c.~. 13A.
Fig. 13C shows an LED layout for vhe 32W dem of Fig.
138.
Fig. 13D is a table showing the meanings of the
various LED indicators of Fig. 13C.
Fig. 13E shows a more detailed functional block
diagram of an ADSL modem for use in a subscriber s
premises, according to the present invention.
Fig. 14A is a simplified block diagram illustration
of an NT card, according to the present invention.
Fig. 14B is a table illustrating some of the
downstream and upstream functions of the NT card of Fig.
14A.
Fig. 14C shows a front view of an NT card, according
to the present invention.
Fig. 14D shows a side view of an NT card, according
to the present invention.
Fig. 14E shows a more detailed block diagram of an
NT card, according to the present invention.
Fig. 14F shows a cell header structure for an ATM
cell which is the main entity which is conveyed through
an ATM network.
Fig. 14G is a table showing the ranting of received
ATM cells depending upon certain bits in the cell header,
combinations of which can be checked accarding to the
modes shown in the table.
Figa 14FI shows an IQ bus cell layout, according to
the present invention.
Fig~ 15A is a block ~~.agram of an .A.D~L Alarm Central
Unit (ACU)~
Fig. 15B lists the funs°~ions of the signals of the
ACU of Fig m 15A
la-
CA 02444239 2003-10-24
Fig. 16 shciws an actual physical embodiment of an
ACI1 card for insertion in the rightmost slot of the shelf
of Fig. 1.
Fag i~ is a side vie~~ cW the ACU card of Fic~. _1.6.
DETAILED DESCRIP~'IO~t t~~' PREFERRED EMBODTMENTB
Fig. ~. shows a new shelf arrangement 1.0 for use in a
subscriber access multiplexer system according to the
invention. The embodiment shown is for use in an ATM
subscriber access multiplexer (ASAM) system, but it
1~ should be understood that the invention is not limited to
ATM embodiments. The shelf ~.O is populated by at least
one or a redundant pair of network termination (NT) cards
12a, 12b, up to twelve xDSL, in this case ADSL
(Asynchronous Digital Subscriber Line), line termination
(LT) cards 14, an equal number of Low Pass Filter (LPF~
cards 24, an optional Networlc Element Processor (NEP~ ~.6a,
(or an optional redundant pair 16a, ~6b), and an Alarm
Collection Unit (ACU) 18. An LT card is described in
more detail below in connection with Fig. 10, while a
network termination card is described in more detail
below in connection with Fig. 14A-14E. A lowpass filter
card is disclosed in more detail below in connection with
Figs. 7A, 7B and 7C. An alarm colle~ctiora unit (ACi~) 28
is shown in block diagram form in Fig. 15, and a physical
2 5 embodiment is shown in Fig. 16.
These cards can be mounted.as shown in Fig. 1 in a
bottom section 20 of the shelf 10 and can be, e.g., six
rank spaces in height where one rack space equals x..75
inches (4.45 cm). An upper portion ~2 of the shelf can
3 0 be, a.g., three rack spaces in height for containing up
to, e.g. , twelve 3.owpass filter (LPF) cards 24, with each
LPF card dedicated to an associated ADSL--LT directly
below it. Also in the upper portion 22 of the shelf 10
may be located connections 2~ for PaiS (plaira old
~ 5 telephone service) interfaces and coa~nectaons 28 for drop
11
CA 02444239 2003-10-24
tipJring leadsF connections 3t~ for power, and a small
board 32 for DS~3~I~'~' equipment prc~t'ction as e~plai_ne~
below The POTS oa:~, but need not, be. i.n analog baseband
form. It could take other forms, such as '1SDN. Note
that the lowpass ~:ilters 24 are grouped in the center of
the upper portion '22 of the shelf, with 'the connections
26 for POTS and connections 28 for drop tipJ.ring leads
for location at ends 33 of the upper portion 22 of the
shelfo Since the lowpass filters plug into the backplane
upon insertion in slots of the shelf and do not connect
to cables, they are positioned in the center of the upper
portion 22. The connections 26, 28, 30 and 32, on the
other hand, require cabling access and are positioned,
according to the present invention, at the ends 33 to
facilitate such connections near the periphery of the
shelf 19, rather than requiring cables passing over
central portions of the shelf. Similarly, the LT cards
14 are positioned in the center of the lower section 20
of the shelf 10, since they do not require cabling and
are connected to other modules by the backplane, to which
they are connected via a connector upon insertion. Thus,
the NTs 12A, 12B, the NEPs 16A, 16B and the ACU 18 are
positioned at ends 35 of the lower section 20 to provide
easy cable access. It is also noted that the shelf is
designed entirely f or front access. The shelf 10 can be
dimensioned to fit both U.S. and European equipment
racks, e.g., beinr~ 498 mm wide and 285 mm deep.
The ADSL-~LTs and the LPFs are dimensioned as four
lines per card. As such, a basic shelf supports forty~
3 0 eight ADSL lines in a physical configuration shown ire.
Fig. 1.
Fig. 1A shows a front view of an actual shelf with
redundant NT cards, ~.2 LT cards, 12 corresponding LPF
cards, and an ACU card all inserted therein. Fig. 1B
shows a plurality of shelves mounted in a central off ice
12
CA 02444239 2003-10-24
y ~;c~~, such. ~a shown say r'ic~ . 1F, i ~~ a s Larsdar d
configuration for sorvaa~g 192 1~DS~ lines., Up ~~~o four:
adj acent racks can share the same f seder b~~ us i nr~
extensi oau units ins~.all ed i ra place of :DTs, as expl wined
below in conz~ectlor~ wi-~h ~'igo 5 ~ In that case ,~ a :Angle
r
optionalJ_yprotected NT card can support up tc~ 576 ADSL
lines. Fig. 1C shows the shelf of Fig. 1A without any
cards installed and shows the connectors insta3.led in the
backplane, into which mating connectors on the cards are
insertable by sliding the cards into the slots shown. In
this way, front-access-only is achieved. A side view of
the shelf is shown in Fig. 1D.
It should be realized that without modification t:he
LTs could be located in the upper portion and the LPFs in
the lower portion. Similarly, the various power and
connection sections can be located other than as shown
exactly in Fig. 1. Thus, the ATM subscriber access
multiplexer (ASAM} shelf described above, although
unique, can have additional as well as ather physical and
packaging arrangements to fit particular applications.
In addition to the above-described frant-access-only
shelf compatible with both U.S. and international racks,
the above-described shelf facilitates high density, i.e.,
small volume per line design. Also included is a
practical high-speed (155~622 MbJs) backplane data bus.
It contains a simple, flexible shelf I1~ (identification}
mechanism. Connectorization and wiring is designed for
future BITS capability. It satisfies both U.S. and
European eleatromagnetia compatibility (EMC)
requirements. It includes card arrangemea~t for NT and LT
Cab ilng f Crr. TWk'~ , Coaxial , or f lber .
AS Suggested abOV'e, 1.t Can be Llti.a_l~ed a8 a X1111~
sized LT shelf for maximum density and minimum cost, as
shown in Fig. 1B for a Cc3, or as described more f~al~_y
13
CA 02444239 2003-10-24
~7~1C~'r ~''e G'a~nl'1~mn.'~3.CSY'~ I~l'~r1 FS.~ o .~'s '~'~u
a LC~~TS_~'"~~-;~Gef;.'~ ~'9B
:shelf nor small remote sites.
The POTS lowpass filters (LPF) 24 of Fig. ~: can be
pa.ssi~.~e filters that are contained as showm in separate
units for ensuring POTS inununity to xI~SL failures,
maintenance and "churn as well as for lower
digital/analog crosstalk. In other words, an LT card or
any other aspect of the ADSL channel can be maintained
without disturbing the POTS. Consequently, overall
performance is increased.
A functional block diagram of an LT/LPF pair from
the group 14, 24 of Fig. 2 is shown serving a single
copper pair 36 in Fig. 2. Although only a single twisted
copper pair 36 is shown, it should be realized that the
preferred embodiment includes four twisted copper pairs
per LT/LPF card pair. Tn other words, the LT/LPF blocks
shown within the ADSL shelf section 34 will be replicated
four times for each such LT/LPF pair shown in Fig. 1 (See
the LT card of Fig. 10).
As seen in Fig. 2, an ADSL data stream formatted as
ATM cells are transported over the copper pair 36
formerly used for telephony only (POTS service) in an
overlay fashion, through the use of highpass ffilters 38,
39 and lowpass filters 40, 42 at both the ADSL shelf to
the left of a dash line 44 and at the subscriber premises
on the right side of the line 44. The line 44 signifies
the place where copper distribution to the subscriber
begins. Normally, the AI~SL shelf section 34 will be part
of a shelf 1Q such as shaven in Fig. ~.A within a rack in a
3~ central office, as shown in Fig. 1B, within which office
also resides a CO switch 46 and a broadband switch such
as a packet switch, e.g., an ATM switch 48. The
broadband switch could be located elsewhere, such as
further~ upstream. The CC~ switch 46 is for connection t~
a switched telephone network, such as the public switched
14
CA 02444239 2003-10-24
~:eLep2~~~~le d~et.~a-c~'~~ (PSI'Y~) ~~e~'!~ pL~c~S~~.c~~nc~
hOTS se.~vxc.e on a
line 50 to the twisted ce~pper p~.i.r 36 ~n~. i~~ts~ custorne~
~aremzses vi a copper wir es 52 at the e;usi:.ome~~ eY~d, as
shown in Fig 2 on tree right~~hand, side of as clashed line
54, signifying a customer premises bouxidary; for
connection to a telephone 56 for normal voice
communication. However, the ADSL shelf 34 could just as
easily be located in a remote cabinet in association with
a DLC (Digital Loop Carrier) shelf, as described further
below, with both AT~7L traff is and POTS being carried to
it, e.g., by a SONET (Synchronous Optical NETwork)
transport product.
The ATM switch 48 is for connection to an ATM
network which provides connection to various services,
including Internet Service Providers (ISPs) and other
high bandwidth service providers. The ATM switch 48
provides ATM formatted data on a line 58 to a network
termination (NT) card 60 which is, in turn, connected to
a plurality of ADSL line termination (LT) cards such as
the card 62 which includes the highpass filter 38 for
providing the ADSL signal on a line 64 to a junction node
66 for combination with the normal telephony signals
provided by the lowpass filter 40. The node 66 thus
forms a means for frequency d~.vision multiplexing, i.e.,
joining the POTS service on the line a0 at a low
frequency with the high bandwidth services provided on
the line 58 and converted to ADSL by the LT 62 at a
higher frequency for passing through the filter 38 and on
to the line 64 for combination with the telephony service
at the node 66 of the twisted copper pair 36. Fig. 12
(not to scale) shows an example of bandwidth allocation
for POTS service at baseband, e.g~~ 0~4 kHz, with DMT
technology used for the ADSL signal between 40 kHz and
1a1 MHz. In this case, the spectrum .alloc:ated for use
3~ downstream is much larger than that allocated for
CA 02444239 2003-10-24
,~.pstreatn; and izence ~~he desianati oTy as ''as~~mme~~.~: i_cal'
digital. subscribes line (AD SL)
Referring back ~:.o Fig. 2 P at v~l~e customer end 64; a
node 68 allows the signal on the line 36 to be spli~l: off
on a line 70 before passing a telephonlj signal through a
lOWpaSS filter 42 ir~ a Networ)t Interface Device (NID)
(not shown). The NID can be an enclosure (box) for
mounting on the wall of a house, and both the node 68 and
LPF 42 can be inside the NID. The line 70 is connected
to an ADSL modem 72 which highpass filters the signal on
the line 70 and demodulates and decodes. the ADSL signal
for providing a high bandwidth signal on a line 74 to
customer premises equipment such as, but not limited to,
a personal computer (PC) 76. The NID enclosure can be,
for example, as shown in copending and co-owned patent
application filed on even date herewith entitled "
Apparatus for Mounting a Low Pass Filter in a Telephone
Network Interface Box" having U.S. Serial No. (Atty.
Docket No. 907-1.58) now U.S. patent No. 6,044,151.
It should be mentioned that the POTS signals in the
baseband p art of the signal spectrum of the signal an the
line 36 of Fig. 2 can include conventional analog modem
and even mechanized loop testing (MLT) signals, neither
of which,will be degraded by or affect. the ADSL service.
The functional block diagram shown in Fig. 2
illustrates both the data and telephony paths to the
customer. The shelf (basic shelf) architecture is
further illustrated in Fig. 3. The basic shelf 10
includes an "IQ bus~° including contro7_ leads 78, which is
more full y described in copending U. S <, provisional patent
application Seria3_ No. (Airty. TJock.et No. 902°--583)
enta_tled "Method for Priol~iti.~,ed Data Transmission az~d
~~at~~ Transanissi r>n t~r:~ange~~ent°'~ , :~il.ec~ c~r~ even date
herewith (see E.P. 0881853, as mentioned. previously). P.s
was known in the prior art, whenever a number of any
16
CA 02444239 2003-10-24
~CiT"~t~ ~f t~lT'It.ifT~.~ L~T"t:Lt,:.~ I'Ie':~.G~_ 't. t'?
~~C-c.'.SS ;.,. CC?TIlICIGTI TCIEC~.h..:,Ttz C'i"
bLIS, soiTie aCCeSS gl""ant C1'ItErIQIi is needed, e.g< , upon
a
grant sigIial, e~C~? ~ermlT"l~l unit enters an arbitratle~n
phase based or~F the ~_espect? <<re priority values assigned
to
the terminal unit. The problem with this is a problem of
fairness, in 'chat tlTe terminal having a low priority
might never get accessn In brief, and as illustrated in
Figd 3A, the I~ bus invention makes the priority
adaptable after each grant cycle, so that if a unit does
1o not get access, its priority can be increased. In
addition, the priority value can be linked tc~ an access
made requested by the terminal unit, e.g., a Guararateed
Cell Rate GCR (CBR, VBR, ABR in case of an ATM-based
bus), Non-Guaranteed Cell Rate NGCR (VBR, ABR, EBR in
15 case of an ATM-based bus) by allocating value ranges to
each access mode, increase of the priority then being
limited by the boundaries of the respective ranges. For
instance, five different levels of QoS classes are shown
at the left-hand side of Fig. 3A, with the lower three
20 classes having both guaranteed cell rate and non-
guaranteed cell rate subclasses indicated. Naturally,
the constant bit rate (CBR) and variax>le bit rate-real
time (VBRrt) classes do not have non-guaranteed cell rate
(NGCR), since they must be guaranteed. The non-
25 guaranteed cell rates are shown grouped at the bottom of
the priority mapping to the right, which shows QoS
subclasses with guaranteed subclasses at the top
(shaded). Nevertheless, according to the present
invention, overbooking of non-guaranteed bandwidth is
0 allowed by providing not only prioritization, as shown,
but also an aging mechanism, as shown on the far right of
Fig. 3A. Edhen a terminal subscri?aing to a non-guaranteed
class of service dies not get abcess within a
predetermined period, its priority is increased according
~5 to a selected algorithm to a value within a range
17
CA 02444239 2003-10-24
,~.<~rrespond ink; to arv access ~mde ha~% inch a r~ighex° :acce5:~
probability. One particular and non-limiting way of
defining priority values is suggested in Fig. 3A, with
2I5-1 priority values d~finad and evenly allocated (for
instance) among the QoS subclasses. As an example, for a
hardened-UBR QoS class, the guaranteed cell rate (GCR) is
normally defined as a number of cells per second. A
period having a time defined by the inverse thereof can
thus be defined as shown in Fig. 3A, indicating how the
priority of the cell from the lowest subclass (Non-~-
Guaranteed Hardened UBR) can be increased after it is not
granted access. to the bus after a waiting time T ~ 1,'GCR
seconds. In the example. shown, the priority is increased
in a single step to that of the Guaranteed Hardened UBR
subclass, thus statistically implementing a minimum cell
rate for the lowest subclass. These teachings
advantageously provide a flexible method al~_owing access
based on a type of access mode and on agreed access
parameters. The IQ bus is thus distinguished by a unique
grant mechanism and fairness algorithm. It provides
multiple QoS classes with multiple cell priorities per
class. It features a cell aging priority mechanism, as
well as a QoS priority mechanism to ensure cells comply
with the class of service parameters defined in Bellcore
Specification GR-1110. It is provided with fault
tolerance and recovery mechanisms, allowing any fault on
the multiplex bus to be quickly identified and isolated.
It has a redundant extension capability as well, as
described below in connection with Fig. 6. The IQ bus
builds upon an earlier °°I~ bus'° (without C~oSj
described
it copending UoS. provisioizal patent application Serial
I~6. (Atty . ~c~c~et f~ica. 3t~~-5~1) entitled. °'priorit~m~a~ed
Access Control l~tethod and Arrangement°° ,, filed on even
data herewith, (,which gave rise to U.S. patent ~lo.
6, 105, 08~) .
18
CA 02444239 2003-10-24
As sho~t?'~ ~.~'~, bot:~. :~'~.gs G ~i and 3 y '~fae NTs~ ~_~ad
~2~.; r~an
be pro~rided in either a :~ edundant o~- ~-~c~r~-redundant
configuratie~n. Irs this architecture, the normal.NE
processing is performed by the NT, and the NT ~~an be
prova_ded as eithe~v a Ss~NET User Networl~. Interface (~JNI)
interface, a DS--3 UNI interface or later, a DSI inverse
multiplex UNI interface. If SONET NTs are provided as
redundant pairs, Automatic Protection Switching (APS) is
provided using the normal 1+1 switchover mechanism
detailed in Bellcore document GR-253. fln SONET NTs, the
physical interface (fiber) is located on the faceplate of
the NT itself (see Figs 14C and 14D), with no need of
additional interface circuitry. If, however, NTs are
provided as DS-3 ports, equipment protection (without
cable protection) is provided using the DS-3 I/O board 32
shown in Fig. 1 installed above the NTs in the shelf,
allowing the single DS-3 facility (coax cable Tx/Rx pair)
to be split and accessed by either NT (inter-NT
communication arbitrates which one is active).
From the foregoing it will be appreciated that the
heart of the ADSL shelf architecture is the above-
mentioned IQ bus and control leads 78. The IQ bus
effectively acts as a multiplexer at the same effective
speed as the NT physical interface. Since ADSL-LTs
provide several classes of service (as deffined in
Bellcore document GN-111a and the ATM Forum Standards), a
grant mechanism allows higher priority upstream cells
greater access to this ATM MUX bus, in order to meet the
QoS parameters required of the respective services
3~ provided. As mentioned, two methods ~:~ cell priority can
be chosen to guarantee QoS requirements and relative
fairness--a weighting priority mechanism abased on
service guarantees) and an aging mechanism (based on time
a cell has been waiting fox a grant)a This mechanism is
3~ tanique and the subject of the aboveme~ationed provisional
1.9
CA 02444239 2003-10-24
application Serial I~o. (Atty Docket 902-583) , (see E. P.
0881 853 as mentioned previously).
The ACU 18 lm Fig. 3 is shown in block diagram form
in Fig. 15, and it performs the following functians~ (~_~
collects external customer designated alarm contacts on
lines 8U and forwards these events to the NT 12a via
lines 78; (2) collects failure indications i.n the rack
and forwards this information to the NT 12a; (3) receives
processed alarm data from the NT and displays the alarm
condition (critical, major, minor) on the AC:U's faceplate
as well as providing contact closures for visual and
audible (and telemetry alarms) to a rack fuse panel and
to a CO alarm interface via a line 82. The ACU also
contains: (4) an alarm cutoff (ACO) function to silence
audible indications until a new alarm is detected (as
well as a remote ACC) function via line 82); (5) a craft
interface port 84 for controlling oAi~ and P functions of
the ADSL NE (using a link to the processor .in the NT);
(6) an ethernet port for OS connection via the NEP; and
(7) a lamp test function. One ACU card is provided per
rack when ~a system spans multiple racks. An ACU is
provided per NT (or redundant NT pair) when multiple
systems reside in a given rack. Multiple systems reside
in a given rack when a very wide bandwidth is to be
served by, e.g., a single shelf. In such a case, a
single shelf may use up the entire bandwidth of an OC-°3
or DS-3 cable.
As shown in Figs. 3 and 10, each ADSL LT 14a, 14b,
..., 141 communicates with up to four remote modems (ADSL
NT or ANT) at corresponding customer premises via DMT
(Discrete Multi-Tone) per T1.413 (see Fig. 12), using A.TI~
cells as the data transport format, according vo the
present invention The subscrp.ber can have a lowpass
filter (LPF) .42 mounteds for e~ampleF on the outside ~ra~.1
of his home in an NID (Network ~Cnterfac~;e Device) bo~~ tc~
CA 02444239 2003-10-24
separate the low frequency service (telephony) from the
higher frequency services (ADSL). As mentioned, a way to
mount such an LPF within an existing design NID is shown in
copending application U.S. Serial No. (Atty. Docket 907-
158) filed on even date herewith, no~.a U,S. patent No.
6,044,151. The two services, once split, use different
twisted pairs in the house wiring, with the ADSL pair
terminating in either an ANT or directly in a PC via an NIC
(Network Interface Card). ANTS, for example, can come in
1Q two types: one. with an ATMF 25.6 Mb/s interface, the other
with an ethernet interface (in this case the ANT packages
the ethernet data as ATM cells using AAL5 (ATM Adaptation
Layer 5) protocol). Both options can be provided on the
same ANT, as shown in Fig. 13B,
The basic shelf 10 also contains, as shown in Figs.
1 and 3, an optional network element processor (NEP)
redundant pair 16a, ~.6b, which communicates over the IQ
bus 78 mechanism and communicates with its redundant
partner over separate leads 86 to determine which one is
active. 'fhe NEP can terminate signaling channels for SVC
20 (switched virtual connection) services or PVC .(permanent
virtual connection) services and can terminate the ACU
ethernet port.
Presently, the two NEP cards 16a, 16b of Figs land
3 are not being implemented, although there are two slots
x eserved far it, Tt is planned to be avrailabl~e later for
terminating and prcacessing SVC (Switched Virtual Circuit)
vigrlaling channels, and for providing ~a~n ethernet
texwinat,;,or:~ for the ACL1 etherne-L: pc9rt. ~l'hera a.ra nu
other functions presently= planned ~~r~r the N:~P o.ards.
As Sklc~tnTr1 1x~ ~'i c~~ ~ , t l .e ~~s?_cw ~:~'tel_:~ _1.n ~Ld.y c?.l..;aC~
b
30 .ase~ as a 'gZ~ub~'~ -ahel« ~~ F wivk~~ one r~r' :~~c~.~e ADSI:ng~.~~'
slo~:_s
a ,'~ i.~ a G~.~ a C.~n. ~~ ~ '° J ~ T ~:. j ,.' ~.y ~~ ~... a~ l f ,
~ "~ P ~"~ ~ .m" .d.
P y m~ :~ ~. ' f~eu_ AIDS~ ~.;.,10'.~1 a : '~.~.C..".,
~f..'ilV'Euh''~r~ alld.a.~'' ~iTru-etC".:, ,~C'~.C~:..i~S ~,7i:w,~y~":_~~~
C,~'o31'~..~ø~.~.~ '~:.h~~ ~~~b ~~ ~a
2 ~.
CA 02444239 2003-10-24
~,'~:7n~'.c'3.'~.en~~,L'~ ~ieTllC3~,~.'~ ~'WDi7L ~~.C.lf ~y0y~
'~.~~, 8.a ~i'1C'J~T2'! ~l~"1 ~''lg~
4 ~ In such cases, for the babe the e$LPF~~ modules a.bo~;e
the DS--3--Lis are replaced with DS3~LrL' interface modules
(one type f~rr i~oi~~~edundant operation amd another type yor
redundant DS-~~ ~sequipment ~arotectionB operations o A
third type of DS~3 LT interface module carp be prov~i.ded
for redundant IQ bus operation, with the DS--3-LTs being
on separate shelves for reliability purposes (due to
there-being only one IQ bus per shelfj. The present
architecture uniquely provides for each of these
redundancy options.
As shown in Fig. 4A, the LT-LPF backplane wiring is
shown with LT transceivers. In this case, the LPF and LT
cards can be configured for redundancy of the LT cards to
be inserted in the LT slots in either a same shelf or in
separate shelves. For example, in Fi.g. ~B, a non
redundant option LT is shown with a DS~-3 interface
inserted in LPF slot 1, wherein input and output DS-3
coax cables from a CO switch are connected to a DS-:3
interface card for insertion in LPF slat ~., which is
connected through the backplane to a DS-3~-LT card for
insertion in LT slot 1, such as the DSw3-LT card 92 of
Fig. 4. The lowpass filter function is carried out at
the remote shelf 96 of Fig. 4 where a DLC is available.
The configuration shown in Fig. 4B for LT slot 1 and LPF
slot 1 could also be used in connection with Fig. 4E, as
explained below.
Fig. 4C shows an application with redundant DS-3-LT
cards for insertion, e.g>, in LT slot ~. and LT slot 2 of
3U a given shelf. In that case, a different kind of DS~3
z/o card is used, double wide as shown, with a center
tapped transformer on the card which is connected both t~
the transmit (TXA/TXB~ and to the receive (RXA/1~8~)
back~lane wiring associated with both LPF slot ~. a.nd LPF
~ 5 slot 2. The NT controls which LT slot is to be active.
22
CA 02444239 2003-10-24
F i:~o ~D is siroi ~_ar a..a .r icy. %:~.~_ bv~h ac~d.i ti_c~nalllr
s~iows
arbitration interfaces bettaeen ~ed.und~~~a.t. DS.-3-=_LTs~
As suc~c~estec~ above, since therE is on.l~r one
naa~sed.undant IQ bus per shelf s the eduipm~e.nt protec~.~.an
?ntplied by f~_g. ~C with .~. and B redvanc~ant DS~3-LT cards
in slots 1 and 2 will be inefyective if the IQ bus itself
has a failure. If it is desired to avail this sort of
failure, a different kind of redundancy' in the DS-3 cards
can be pr~vided, as shown in Fig. 4E. In that case, half
20 of the transmit and receive signals are used in. the
shelf, and the other half can be routed to a different
shelf, instead of slot 2 in the same shelf. The top two
cables shown in Fig. 4E would thus be routed to another
shelf and be connected into, e.g., the DS-3 out and DS-3
in transformers shown in Fig. ~B in another shelf. The
DS-3 out and DS-3 in cables of Fig. 4E would go to the CO
switch or other network element.
As will be observed in Fig. 4, an ADSL shelf 90 may
have both ADSL-LTs 14a and aggregate type LTs such as the
DS-3-LTs 9,2, 94 shown. Service classes in both cases are
provided for subscribers by separate buffers per service
class (CBR, VBR, UBR, etc.), each contending for upstream
access to the IQ bus via the control lads and the grant
mechanism based in part on the priority assigned. to each
upstream cell. In the case of aggregate LTs, such as
shown in the hub 90 of Fig~ 4, the service class buffers
have a cell priority equal to the sum of the aggregate
cell priarities in each buffer (or even some percentage),
in order that the remote subscribers are assigned a fair
3o share of the hub~s operating bandwidth. :fin times of
bursty upstream traffic, congestion and DS-3~LT buffer
overflow is managed by limiting the DS-3 link bandwidth
and allowing temporary buffer fill ire the remate ADSL~LTs
(until such time that the traffic pea~~ subsides). It is
~5 noted that pDTS interfaces are not shc~wr~ :in Fig. ~: but
23
CA 02444239 2003-10-24
~,TC~uld norma_ll_y be pro~ja.ded f ~ " g ~ , ~~~~ ~I~~~ s
ac.~j ac~'eni~ os
i.r~cc~r por atec~ in the Remotes 9 5 , 9 8 .
fig. 5 shows the hub 90 of Fief a =E boated zn
central of five 10G which riay ai.sc~ iualude a ~O switc:h
102
and an AT~i switch 104. The 00 switch is connected ~to a
public switched telephone network (PS'TN) 1D6 arid the ATM
switch to an ATM network 108 which. is, in turn~ connected
to other services 110 which may include various Internet
service providers 112, ..., 114. As illustrated in Fig.
4, the hub shelf 90 rnay be populated by both ADSL LT
cards such as the card 14a and various other cards
including DS-3 LT cards 92, 94. Four copper pairs
emerging from the ADSL LT card 14a of Fig. 4 are
illustrated as a plurality of copper pairs 116 in both
Figs. 4 and 5. These leads provide an ADSL link directly
between the hub and the various customer premises
illustrated, including a customer premises 118 shown in
detail. Tf the shelf 90 were used exclusively with ADSL
LTs 14, such as shown in Fig. 1, all of th.e subscriber
lines would be like the lines 116 without using the sheaf
90 as a hub and without the remotes of Fig. 5. In other
words, there would be twelve groups of 4 gOTS plus ADSL
lines 116 serving 48 different customer premises. The
implementation of Fige 5 provides for many more customer
premises served by a single shelf, but with the
accompanying increased competition for upstream
bandwidth. This can be tolerated in cases where the
majority of subscribers are using lower quality of
service.
A lowpass filter 120 is mounted in a network
interface device arrangement (not sho~wnj for terminating
the subscriber line ~t the customer's premises. It
filters out all but the low frequency telephozzy signal
.from the copper pair and provides it on a line 122 to a.
traditional telephone 124 for voice c~ommunicationsa Tt
24
CA 02444239 2003-10-24
also f ii i~er s higi~ frec~uencu% dia! pulse or r i ng trip
transients so that they do not interfere in the upstream
direction with. the high~speed data traffic. A second
copper pair connected before the lowpass filter, as
shown, is provided tc~ an ADSL modem 126 which, after
highpass filtering, demodulates and decodes the ADSL
signal and provides output bits on a line 128 to a user
terminal 130 such as a personal computer, Internet
computer, etc., e.g., for Internet access or far access
to other high bandwidth services 110. It should be
realized that the ADSL modem also operates in the reverse
(upstream) direction, albeit in a much narrower
bandwidth, to encode and modulate bits onto the ADSL line
from the subscriber to the ATM network as per ANSI T1.413
(see Fig. 12).
The remote shelves 96, 98 of Fig. ~ are also shown
in Fig. 5 connected to various customer premises, which
are similar to premises 118.
Fig. 6 shows in detail the above-mentioned feature
of the present architecture whereby a plurality of ADSL
shelves 10a, lOb, lOc, 10d such as shown in Fig. 1 can be
daisy-chained together in a rack by means of an extender
card (EXT) in each subsequent shelf. The extender card
function is to effectively extend the IQ bus from shelf
to shelf (daisy-chained, e.g.,-to a maximum of twelve
shelves altogether), allowing up to, e.g., 57.6 ADSL
subscribers accessed to the system. In other words, the
extender card allows an NT card in a first shelf to act
as an NT card for another shelf or a plurality of other
3 0 shelves. 7C. e., in this case,. three racks w~_th altogether
twelve daisy-chained shelves. The extender cards can be
mounted as shown ~_n Fig~ 6 in the NT slots of subsequent
shelves and may be redundant. In that caseg any fsilure
of an NT car extender card baL~k switches all LTs frorv the
'"A" NTelextender string to the g~~lB str ingd. The active
CA 02444239 2003-10-24
str: ity Lher~ assuinea cc~ia~o? of ea~:~ ;~heyi " s I C~ W .rs
~ 'I'~~e.
IQ bus itself (~rithi~. each shel f ) is riot vedurrdan-~ F :gut
meets reliability r ecguir: ernents P as the NT has the ability
to remove ea :h LT :~rorn the I~ bus (disable) i.o iscl_ate a
fault and remove it from service.
As suggested above, the POTS lowpass filters can be
provided for different optiorss including "integrated" in
a CO shelf for maximum packaging density, minimum cabling
and installation complexity and mini~ttum cost as described
above or "separate" (remote, non-integrated) for
regulatory flexibility and access to existing (crowded)
DLC cabinets.
Fig. 7A shows a lowpass filter card, such as one of
the LPF cards 24 shown in Fig. 1 in schenatic block
diagram form. Four different lowpass filtersjsplitters
are shown on the card. To the left of each card is a
voice port for connection to the narrowband (NB) network
via the CO switch 46 via the line 50. On the righthand
side of each lowpass filter/splitter is a port which is
connected both to the twisted copper pair 36 to the
subscriber and to the highpass filter 38 of the LT 62
(see Fig. 2). A side view of the physical dimensions of
such a four-channel LPF card is shown in Fig. 7B, while a
front view is shown in Fig. 7C.
Fig. 7D shows a sputter shelf for use in
applications where the lowpass filters need to be remote
from the ADSL shelfo Such a shelf can be used, for
example, when (a) separate service providers are
responsible for the telephony and ADSL services, or (b)
3 0 in DLC (digital loop carrier) configurations where remote
cabinets of DLC equipment cannot accommodate ADSL
equipment (due to lack of physical space)f. but since the
subscriber transmission pairs terminate in the DLC
cabinet (and enough room is a~jailable for a small lowpass
CA 02444239 2003-10-24
f 3.1t'e~:' "spl~'~'.YS..e~'~','~ , ';~'~._;.s sI-~elf t:7T'f=L~i~
1:w ~.aT~..~-"tca.ll ~r.~. a.ia the
DLC c~.k~inet o
Iz~~ this case, the basic xDSL shelf is used, as
previousl~T showra,~ but ;myth the LPF boards nat populated
.
A separate g'splitter' shelf, as sl~.own i.z~a Figo 7, is then
provided aid has a configuration the same as, ar very
much liJ~e, the top portion of the basic xDSL shelf 10 of
Fig. 1. The main difference in remote sp7.itter
configurations is the cabling and the use of "stackable'~
connectors. The splitter shelf is shown in Fig. 7, arid a
typical configuration using sputter shelves is shown in
Fig. 8. In an initial implementation, LPFs (anl the
sputter shelf) need no power, as all circuitry is
passive.
Fig. 8A shows a remote cabinet that can be used whe-n
adding ADSL service to existing metallic-fed DLCs. This
configuration supports up to 96 lines in a type 3002
cabinet.
It should be noted that the "separateness" of the
lowpass filters 24 as shown in Fig. 1 from the >JTs, as
well as the separateness of the LPFs of Figs. 7, 8 and 8A
is not only advantageous for the reason mentioned above,
i.e., for facilitating separate service providers for
telephony arid ADSL services, but also for the very
important reason, according to the present invention, for
physically separating the lifeline telephony service from
the ADSL service. Such separateness provides an
increased level of integrity for the lifeline POTS
service, since such physical separateness itself ensures
3 D that any maintenance actions which maJr need to be
performed on the ADSL part of the system can be done in ~.
physically separate manner, and therefore in such a way
as to not affect the PATS service (and vice versa)o
Another ec~uipmer~t shel f is th.e RAID (Remote ADSL P~ltax)
5 shelf as shown in F3_g. 9 < Tha.s shelf is deployed very
27
CA 02444239 2003-10-24
ICl.f.~C.',i'I i ;Lily.': tale ~'"''~111C5'~..'c ~.J.~r'J~ ~h~,.L~It:'
S ~ v 1 :~ c~. ~"'vhC~~elri 7 n t' ~g
a.nd i n fact may hare the same shelf a~ch~.tecture as that
shown i~ Fig: 3 a The difference is that the R.A~I shelf is
more suited for' CPE or DLC applicatiorxs where8 eog. d. no
more vhara. ~.wer_tymfour lines are regui~ed, and a smaller
shelf (6RS versus 9RS) is desired. As such, a lshelf
may be designed and physically configured, for example,
as shown in Fig. 9a This shows the flexibility of the
xDSL shelf of the present architecture.
to Fig. 10 shows a functional block diagram of one of
the ADSL LT cards 14a of Figs. 1, 3 and 4. The
implementation of the various functional blocks is
realized in this implementation by the application of an
ADSL chip set of assignee for DMT technology. This chip
set consists of three chips (integrated circuits]
identified as RCFiAP for ATM functions, a DACHA./SACHA chip
for Reed Solomon coding and decoding, and a front-end DSP
chip called ADSLB. The remaining blocks are preferably
carried out by other means outside the chip set. The
three chip chip set RCI3AP, SACHA and ADSLB are also shown
in Fig. 11 in a simplified block diagram that shows the
chip set in both an LT 14a in an ADSL shelf 34 and in an
ADSL modem 72 at a customer's premises in reverse
ordering of chips.
In regard to the.ATM functions carried out by the
RCHAPB chip, such takes care of the encapsulation of ATNi
cells in 54-byte slots and the access to two separate 1Q
buses~ i.e~, upstream and downstream. There is also a
dummy cell added to the 53 standard ATM cells in order to
3o allow a change-over from ane LT to another on the
upstream IQ, interface (between cells). Un the downstream
IQ interface, this byte is not filled in, and on the
upstream IQ interface; the bus is in high impedance state.
during this bytem
28
CA 02444239 2003-10-24
'the main ent.~_'i..y ~al~ich is ~..~:~a~.~reyed. t~~rc~uc~~:c
a~~~ ATNY
net~~ork ~.s a cell which is dit~idec~ aw':o tyro parts, each
with a fixed sizes the headex {~ Kbytes) , and the
i nior~nation fiela (~8 bytes) o Dependixy on the value of
the header of the ATM cell, a, number of .ATM-related
functions may be performed, such as insertion and
extraction of maintenance cells, cell rate decouplingB
Header Error Control (HEC) generation/cherkp payload
scrambling, cell loopback, etc.
The data that are sent on the ADSL line are forward
errar- corrected (FEC) by Reed Solomon {R5) coding to
improve the bit error rate. To allow for an even better
protection against burst errors an interleaving
possibility is incorporated, with the disadvantage of an
increased transfer delay for interleaved data. Alsa, a
scrambler is included to randomize the data before the RS
encoder. After the RS decoder, the data is then
descrambled.
Also carried out by the SACRA chip set, besides Reed
Solomon (de)ceding is mapping and demapping. In the ADSL
system, a DMT approach may be followed in which, for
example, up to two hundred fifty-six carrier frequencies
can be used (see Fig. 12). Each of these frequencies
will carry a number of bits according to a mapping table.
The function of the mapper is,to assign the bits to the
different frequencies. The mapper caxa. also send some
special DMT symbols for link initialization and
maintenance. The demapper will demodulate and monitor
the received symbols. After demodulation, it delivers
3~ the data. to the on~chip RS decoder. Some special
functions are included in the demapper for initialization
and maintenance of the ADSL link. An example of an ADSL
mapper is shown in Fig' ~. of copendinq and co-owned
application Serial No. U8J~77,468g filed July 208 1.996
3~ and described at page '~, line 5a through page 9, line 23.
29
CA 02444239 2003-10-24
A similar description is given in copending provisional
application Serial IVo. Batty. Docket ~To. 902-5°75) filed
on even date herewith, entitled "Method and Windowing
Unit to Reduce Leakage, Fourier Transformer and DMT Modem
Wherein the Unit is Used", at page 5, line 10, through
page 7, line 26 the~~eof (which gave rise to U.S. patent No.
6, 240, 129) .
The output of thei moppet is a complex representation
of all the carrier frequencies. An Inverse Fast Fourier
Transformer is used to transform this representation to a
time signal. In cooperation with the IFFT, a carrier
selective scaling can be installed. In the upstream
direction, an FFT is used to transform the received time
signal to a frequency representation.
The main function of the front-end digital signal
processing is to separate the received signal as much as
possible from the transmitted signal, and to correct for
the line and analog front-end characteristics.
The ADSLB chip function includes analog-to-digital
(A/D) and digital-to-analog (DjA) conversion. The
function of the subscriber line analog front end is the
termination of the analog line interface and the
transformation of the digital data into an analog
passband signal that can be transmitted on a physical
subscriber line 36 and vice versa. For the D/A and A/D
conversion, a sigma-delta (E~) approach is used.
As shown in Fig. 11, the subscriber line analog
front-end function includes a line driver used to amplify
the ADSLB output to the levels appropriate to be
transmitted over the subscriber line. A hybrid is
included as a passive network that performs the
termination of the subscriber line with its nominal
impedance and handles the conversion between four-wire
and two-wire in the LT at the upstream end. It perforx~.s
the separation in the upstream direction between the
upstream and downstream signals, and the combining in the
3~
CA 02444239 2003-10-24
downstream direction. The reverse is performed at the
downstream end of the line.
Referring back to Fig. 10, it is noted that the LT
14a includes four separate line termination paths for
four separate subscribers. Although not shown in Fig. 20
or 11, it should be realised that the twisted pair
connects not only to the HP-filter and hybrid shown in
Figs. 10 and 11, but also to a lowpass filter 40, such as
shown in Fig. 2. Fig, 10A shows a front view of an LT
card, while Fig. lab shows a side view.
Since POTS signals and ADSL signals are transported
frequency-multiplexed on a subscriber line, as shown in
Fig. 12, a POTS lowpass filter 26 is required, which
performs the following functions: (1) combining the POTS
25 and ADSL transmit signals toward the subscriber premises,
(2) separating the POTS and ADSL signals from the
subscriber premises; (3) protecting the PUTS from audible
interference, generated by signals from the ADSL modem
and the ADSL shelf; and {4) protecting the ADSL receiver
from all POTS-related signals, particularly dial pulses,
ringing and ring trip transients.
These functions are performed while meeting all the
requirements for POTS performance, such as return loss,
insertion loss and group delay, such as those in ANSI
Standard T1.413. The combination and separation of POTS
and ADSL signals is achieved by lowpass and highpass
filtering, as shown in Fig. 2. Only the highpass filter
and the hybrid are part of the LT. As mentioned above,
the lowpass part preferably resides on a different
printed board assembly (LPF),
Also shown in Fig. 30 is an on-board controller
(OBC), which may be embodied as a microprocessor included
to handle a variety of tasks, such as initialization ~f
ASICs, monitoring and processing of maintenance massages,
and detection of a malfunctioning LT, On-board memory
31
CA 02444239 2003-10-24
may inclhde flash~PROIYI and DRAM used for executable code
and data. Inventory information may also be stored on an
EEPR03~ so as to provide the necessary data for an
adequate identification of a replaceable item. Such may
include product identification, manufacturing information
and inventory information. Also shown in Fig. 10 are
power supply functions by way of on-board mounted DC/DC
converters. A test access port (not shown) may also be
provided.
As will be understood by anyone of skill in the art,
from American Rational Standard for Telecammunications
"Network and Customer Installation Interfaces--Asymmetric
Digital Subscriber Line (ADSL) Metallic Interface", ANSI
T1.413-1995, the~nature of the signal on the twisted pair
36 shown in Fig. 11 and in Fig. 2 may be a standardized
asymmetric digital subscriber line signal that allows the
provision of plain old telephone service (POTS) and a
variety of digital channels. In the direction from the
network to the customer premises, the digital channels
2o may consist of full duplex low-speed channels and simplex
high-speed channels; in the upstream direction, only low-
speed channels are provided. The transmission system is
designed to operate on two-wire twisted metallic cable
pairs with mixed gauges. The standard is based on the
use of cables without loading coils, but bridged taps are
acceptable; with the exception of unusual situations. As
shown in Fig. 12, for example, the power spectrum is
shown as including a 4 KHz band reserved for POTS
service, with the portion of the spectrum between 40 KHz
and 1.1 MHz occupied by a large plurality of carriers,
with tone spacing of 4.3125 KHz. A small portion of the
spectrum is used for upstream data, as shown, with the
remainder used for downstream data. Each of the ~ KHz
tones is SAM-modulated and individually selected and
optimized as a function of individual subscriber line
3~
CA 02444239 2003-10-24
char acteristics . Some .:.ones a.re allocated with a large
number of bits, while others a lesser number or none at
all, due to line conditions.
As sraown in Fig. 13., the functions already described
in connection with an ADSL LT 14a are replicated in the
ADSL modem 72. In addition, a selected interface to the
subscriber PC 76 may include, e.g., an ATM-25 and/or
Ethernet interface, as shown in Fig. 11.
Fig. 13A shows a simplified block diagram
illustration of an ADSL Network Termination (ANT) unit.
It includes a modem part which performs the ATU-R
transmitter reference model functions, for example, as
shown in Section 4.3 of ANSI T1.413-I~95. An ATM
function is added, according to the present invention,
for ATM translation and signal processing. In the
downstream direction, the ANT unit terminates the ADSL
signal, demodulates, and the interconnect function
converts the ATM cells into a digital bitstream to the
subscribers digital terminal equipment (DTE). In the
embodiment shown, the interfacing black to the customer
equipment includes both ATM and/or ethernet interfaces,
as shown. Fig. 13B shows an ADSL Network Termination
Unit with the line, ATM and ethernet connections shown.
The line connector is RJ14, while the ATMF-25 and lODase-
T connectors are RJ45. Fig. 13C shows five LED
indicators that are visible on the top of the box of Fig.
13B for giving the indications indicated in the table of
Fig. 13D .
A more detailed func-tional block diagram of an ADSL
3 0 modem 72 (such as already shown in Fig. 21) is shown in
Fig. 13. The lowpass filter 42 of Fig. 2 is shown as
part of an external "splitter" in Fig. 13, which also
includes the node 68 of Fig. 2.
An external AC/DC inverter (6V DC/xV AC) and an on-
3 5 board DC/DC power supply are shown in Fig. 13 and are
33
CA 02444239 2003-10-24
used to feed the power to the board. The external power
supply (AC/DC) converts the high voltage from the wall
outlet to a voltage that can be handled by the ADSZ modem
i2, such as r~ volts DC. Further conversions are shown
from the DC/DC power supply.
An analog front-end may include the highpass filter
39 already shown in Fig. 2, as well as a hybrid and line
driver such as shown in Fig. 11. The hybrid is for 2-
wire to/from 4-wire conversion.
I0 An ADSLB block is shown for terminating the analog
line interface and for transformation of digital data
from a DACHA/SACHA block into an analog passband signal
that can be transmitted on a physical subscriber line and
vice versa. The ADSLB performs analog-to-digital (A/D)
and digital-to-analog (D/A) conversion.
Again, the SACgiA is the DMT signal
modulatorldemodulator. This software-configured ASIC
processes the ATM cells (scrambled) from the RCHAP block
and delivers the DMT modulated signal to the ADSLB and
2o vice versa. Note that there is no difference between the
DACHA and the SACRA, except a lower cost for the SACRA.
A DACHA can be used as well, and is especially necessary
to support a standardized 4.3125 KHz t~ne spacing mode.
The RCHAP provides the interconnection between the
SACHA/DACHA and the rest of the system. It contains 16
ATM cell buffers in both upstream and downstream
directions, and performs virtual path/virtual channel
(VP/VC) translation, extraction and insertion of ATM
cells, and handles on-board tasks.
A RAPID block provides interfacing between RCHAP,
ATM-izer and IDT-PRY blocks. Tt also contains DMA
controller and logic for ethernet functions.
The IDT-PRY block translates ATM cells between the
on-board parallel data bus (with standard byte-wide
34
CA 02444239 2003-10-24
cells) and the serial data over the AT~~ forum physical
connector (with scrambled 4B5B coded data).
The ATM-izer is the upstream controller, responsible
for upstream quality of service, cell shaping and
policing. It is responsible for translating downstream
AALS packets into ethernet-frames and vice versa.
Handling upstream ATM Forum data is also performed by the
ATM-izer.
An 182596 controller performs CSMAJCD medium-access
control, moves ethernet frames between SRAM packet memory
and a serial ethernet transceiver. It is monitored by
the OBC. An I82503 performs ~ serial transceiver
function to 802.3 lOBase-T, direct interface to I8259G.
For code processing, an T960 microprocessor is
included to handle a variety of tasks, such as
initialization of ASICs, memories, etc., monitoring and
processing of the maintenance messages, on-line/off-line
test support. Memory is included in the C)BC as well,
such as 2 Mb DRAM for program executables and a 1.5 Mb F-
PROM for boot bode, power-on test, a 53.2 Kb for ethernet
packet memory, etc. A small EEPROM (4 Kbit) is used for
a remote inventor circuit.
Fig. 14A shows a simplified block diagram of an
embodiment of an NT card, according t,o the present
invention. It provides a high-speed optical or
electrical access to a Synchronous Optical Network
(SONET) transport system. It converts Asynchronous
Transfer Mode (ATM) cells to SONET packets (i.e., frames)
and vice versa. Thus, the NT card adapts ATM cells
carried on the IQ bus to the SONET transmission system
and vice versa. zt also includes necessary functions as
listed in the table of Fig. 14B for operating and
maintaining the ATM subscriber access multiplexer of the
present inventiono
CA 02444239 2003-10-24
It 1S ~~ted that the table of Figo 14~ is split into
two columns representing downstream functions and
upstream functions. The downstream functions, for
example, have been grouped and numbered 1-4, and
similarly labeled in Fig. 14A in the top section of the
respective four blocks. Similarly, for the upstream
functions, these have been grouped in the right-hand side
of the table and have been numbered 5-8, with the same
numbers shown in the lower half of the blocks of Fig.
14A. It should be realized that these functions can be
moved between blocks, and this is just an example.
In regard to the physical medium block, this can be
an optical interface for interfacing an optical transport
system with a receive and transmit optical fiber carrying
25 signals, e.g., with a nominal bit rate of 155.52 Mbps.
The interface is symmetric, i.e., it has the same bit
rate in both directions and could operate, e.g., at a
wavelength of 1.3 Vim. This signal can be a SONET
(Synchronous Optical Network) signal at the OC-3 level
for conversion to STM-1/STS-3c in the electrical domain.
This is a serial signal which the physical medium
interface block converts to parallel form at a slower
rate for processing on the NT card, with the parallel.
downstream output locked on to the received clock.
The transmission convergence sublayer processing is
done in the second block, wherein the ATM cells are
delineated within a hierarchical transmission frame
structure used to transport the ATM Cells. These cells
are divided into two parts, each with a fixed size, the
3 0 head with five octets, as shown in Fig. 14F, end the
payload with 48 octets, as shown in Fig. 14H. zn the ATM
block of Fig. 14A, ATM layer processing is carried out.
In the upstream direction, all fields in the ATM cells
received on the IQup interface are transported
3 5 transparently, except for the Header Error Control (HEC)
CA 02444239 2003-10-24
field (see ITU-T Recommendation I.361, 'sE-ISBN ATM Layer
Specificationss). The HEC may be checked ar not, as an
option. The routing of received ATM cells depends upon
the VPI (Virtual_ path Identifier) and VCI (Virtual
Channel Identifier) bits in the cell header. The full
VPI octet and the eight least significant bits of the VCI
can be checked for VPI/VCI combinations corresponding
with a data channel to be extracted. This method
provides for a maximum of 21b channels which can be marked
1o for extraction. All valid cells received from the IQ
interface are transmitted either upstream in a virtual
container or synchronous payload envelope (VC-4/SPE, or
to an on-board controller.
For downstream ATM layer processing in the ATM block
of Fig. 14A, each VC-4/SPE carries the equivalent of
44.151 cells (53 octets which are octet-aligned and
floating within the VC-4/SPE. The ATM cell delineation
uses the correlation between the Header Error Contral
(HEC) in the cell header and the cell header itself. The
cell delineation mechanism, as recommended. by ITU-T
Recommendation I.432, "B-ISBN User-Network Interface-
Physical Layer Specification", is used. Tn~hen the ATM
cell boundary identif icatian in octet H4 is used, the
cell delineation will start searching at- the octet
indicated by H4. Tf not, the search will start at the
ffirst octet of the payload period: The ATM cell
information fields are descrambled according to the self-
synchronizing scrambling/descrambling scheme recommended
by ITU-T.
Valid non-idle cells, each with its confirmed HEC
octet and descrambled information field, are sent to the
IQ down interface, which is the last block Shawn in Fig.
14A. In that block, idle cell periods are added to adapt
a received bit rate of up to 149.76 Mbit/s to 152.64
Mbit/s.
37
CA 02444239 2003-10-24
The routing of received ATM cells depends upon the
VPI, VCI and PTI (payload type identifier) bits in the
cell header. In total, 16 bits or four nibbles of
VpIJVCI com~b~nat~.ons can be Checked, avcording to the
modes shown in Fig. 14G. In each mentioned mode,
different nibbles of VPI/VCI are selected. The selected
VPI/VCI nibble combination corresponds with a specific
data channel to be extracted. Cells can be extracted by
looking only at the VPI/VCI combination or by looking at
the VPI/VCI combination and at the PTI bits. In the
second case, each FTI (23 in total) can be marked for
extraction. This marking will then be used for all
VPI/VCI combinations for which extraction is indicated,
with the inclusion of the PTI check.. All. valid cells
received in the virtual container or synchronous payload
envelope, independent of their VPI/VCI combination, are
transmitted downstream on the IQ down interface (cells
marked for extraction are also sent to the ATM interface
bus) .
ATM cell insertion and extraction is provided at the
NT both in the direction of the network and in the
direction of the I~ bus, in order to provide for the
transmission and reception of Operation And Maintenance
and signaling cells. Cell insertion and extraction is
under control of an On-Board Controller (OBC).
In the upstream direction, the OBC has the
possibility of inserting ATM cells in the outgoing VC-
4/sPE. The OBC has to provide a valid cell header
without IiEC, followed by a least six bytes and, at most,
the complete cell payload {a total of 52 octets). The
HEC is calculated before the cell is put into the VC-
4/SPE. Interfacing between the OBC and upstream cell
stream is performed by using a FIFO buffer on which a
back pressure signal indicates if the OBC is allowed to
insert a cell or has to wait until the previously
38
CA 02444239 2003-10-24
inserted cell is transmitted. Cells received on the IQ
up interface have a higher priority than cells coming
from the OBC. Synchronization is performed by a
syr_chro?,; zati on signal whi ch ?_ndi Gates to tha Gel 1
insertion device where the boundary between two inserted
cells in the FIFO buffer is. Downstream, the OBC has the
possibility of inserting ATM cells in the IQ down cell
stream. The OBC has to provide a valid cell header
without HEC, followed by at least six bytes and at most
the complete cell payload (a total of 52 octets). The
HEC is generated when transmitted onto the IQ interface.
Interfacing between the OBC and the downstream cell
stream is performed by the same cell FIFO buffer as for
the upstream cell insertion. Also for downstream cell
insertion, a back pressure mechanism is implemented.
Cells received in the VC-4/SPE have a higher priority
than cells from the OBC~ Synchronization is performed by
a synchronization signal, which indicates to the cell
insertion device where the boundary between two inserted
2O cells in the FIFO buffer is.
For cell extraction in the upstream direction, such
is performed using the cell filtering mechanism described
above. Only the first four octets of the cell header and
the complete payload are extracted from the IQ up
interface. For interfacing between the extraction
circuitry and the OBC, a FIFO buffer is used. The OBC
should synchronize to the extracted cell stream by
reading blocks of 52 octets until the buffer is empty.
Downstream cell extraction is performedoa.sing the
cell filtering mechanism mentioned above. Only the (first
four octets of the cell header and the complete payload
are extracted from the VC-4/SPE. Before a possible
extraction, the HEC in these cells is already checked for
errors. For interfacing between the extraction circuitry
~ 5 and the OBC, a FIFO buffer is used. The OBC should
33
CA 02444239 2003-10-24
synchronised tc~ tree extracted cell sti_~~eam bar reading
blocks of 52 octets until the buifez is empty. The cell
which is extracted towards the oBC can optiona-~ly be sent
to the IQ down interface also.
As suggested above, the ICS down and IQ up buses
transport ATM cells with a five-octet header and a 48w
octet information field. In front of each cell is one
dummy octet, illustrated in Fig. 14H. The ATM cells are
encapsulated in 54 octet slots and provided access to the
IQ bus. The adaptation of 155.52 Mbit/s to 152.64 Mbit/s
(53/54*155.52 Mbit/s) is performed by the deletion of
idle cells. This can be done due to the fact that the
maximum bit rate of valid ATM cells contained in the vC-
4s/SPEs is limited to 149,76 Mbit/s (2~°-27155.52
Mbit/s) .
The dummy octet is added to the ATM cells in order
to allow a changeover from one LT to another on the IQ up
interface (between cells). On the zQ down interface,
this octet is not filled in, on the IQ up interface, the
bus is in high impedance state during this octet.
The NT card is managed by an ADSL workstation (AWS)
which may be located in an operating system (OS) as shown
in Fig. 5. Such an OS may communicate through an ATM
network and an ATM switch in a central office with the NT
card in the shelf. See copending and co-owned U.S.
patent application S/N (Atty. Docket No. 907-160) (now U.S.
patent No. 5,991,814) entitled "ASAN Network Management
System with Open Lcop Flow Control", filed on even date
herewith f or further details. Fig. 14C shows a front view
and Fig. 14D a side view of an NT card, such as may be used
in a slot of a shelf of Fig. 1.
Figo ~.4E' shows a mare detailed functional block
diagram of an NT card 12a of Fig. 1. An
optical/el ectrica7_ transceiver prou:~des a ~OI~ET/SDH
CA 02444239 2003-10-24
compliant interface for 1.55.52 'Mbps STNtI. or STS3-c
signals in one integrated package. Cl~ck recovery is
done in the S/UNI+. In order to do this clock recovery,
it requires a reference clock. The recovered clock
(155.52 MHz) is divided by eight in the S/UNI+ and serves
as one of the inputs for serving as a reference clock to
a PLL circuit located in a UIAC block to which a VCXO
output clock must track (if loop timing is enabled). The
resulting clock out of the VCXO serves as input cloak for
transmit data towards the optical transceiver, where this
clock is used to synthesize the transmit clock, and which
also serves as a system clock. The reference clock input
and the VCXO output clock are further divided by a factor
N in the UIAC ~N = 2048 for Bellcore and N' = 128 for
ITU). After a phase comparison between the two resulting
divided clocks, the resulting voltage is fed to a lowpass
filter, after which the signal drives the VCXO. Loop
timing can be established by locking the transmit clock
(system clock) on the receive clock.
2o At the ATM side of the S/UNI+ there a.re two internal
four~cell synchronous FIFO's present that are controlled
by the UIAC. This interface acts as an SCI/PHY (Utopia-
like) interface. Back pressure (upstream) is inherently
present due to the FIFO's integrated in the S/UNI. For
the upstream direction, this means that if there is a
full load of 155.52 Mbps on the IQ bus (1.52.64 Mbps at
the Utopia interface) and a maximum transmit capacity of
149.76 Mbps ATM cells, the four-cell FIFO will be full
after 1.5 ms.
The UIAC component is an LCA device which is
programmed during "power-on-reset from a serial PROM.
St uses three synchronous 512 x 9 bit FIFOs for cell
insertion and extraction and one 128K x 8 bit SRAM for
routing. The UIAC module has a SCI/PHY (Utopia-like)
interface to the S/UNI+ component. ATM cell insertion in
41
CA 02444239 2003-10-24
t.
both the direction of the network (Sn~i/SONET) and in the
direction of the LTs is handled by a 1 SIF (signaling
insertion FIFO) buffer. An OBC bus is connected directly
to the eight data inputs of the FIFO. The direction of
cell insertion is specified by the OBC by writing into an
additional UIAC register. The ninth bit of the FIFO is
used for cell synchronisation and insertion direction
specification. A RAM lookup table is used for cell
filtering on VPI/VCI combinations. The RAM has 128K
entries of eight bits.
Downstream cell extraction is performed by a
downstream signaling extraction FrFO (DSEF). The eight-
bit output data of this buffer is connected to a
peripheral bus. All cells which are extracted are copied
by default to the downstream traffic stream. This can be
disabled, however, by a traffic contr~~1 register in the
UIAC.
Upstream cell extraction is performed. via the USEF
(upstream signal extraction FIFO). The eight-bit output
data of this buffer is connected to the peripheral bus.
A cell received on the upstream IQ interface is sent
either to the OBC or to the upstream SDH/SONET interface.
All cells which are extracted are copied by default to
the upstream traffic stream. This can be disabled,
however, by the traffic control register in the UIAC.
In the downstream direction, ATM cells are
transferred to an TCOM interface. In the upstream
direction, ATM cells are received from the ICOM.
The UIAC may be equipped by a boundary scan
interface conforming to IEEE 1149.1 (JTAG) Specification.
A block diagram of an ADSL Alarm. Control Unit (ACU)
is shown in Fig. 15A, while the functions thereof are
listed the table of Fig. 15B. Fig. 16 shows a front view
and Fig. 17 a side view of the ACU.
42
CA 02444239 2003-10-24
reference
relevance:
In addition to the foregoing disclosure,
may be made to the following disclosures of
U.S. Pat. No. 5,636,253, issued June 3, 1997,
entitled "Method for Detecting Erasures in Received Digital
Data";
U.S. Pat. No. 5,633,817, issued May 27, 1997,
entitled "Fast Fourier Transform Dedicated Processor";
U.S. Patent Application Serial No. 08/561,445,
filed November 21; 1995, entitled "Signal Processor
Module", disclosing ADSL selective DPLL (now U.S. Pat. No.
5,657,355);
U.S. Patent Application Serial No. 0.8/560,938,
filed November 20, 1995, entitled "Signal Processor"
disclosing a DMT-based transceiver (now U.S. Pat. No.
5,768,318);
U.S. Patent Application Serial No. 08/593,885,
filed January 30, 1996, entitled "Frequency D1v1S10n
Multiple Access (FDMA) Dedicated Transmission System,
Transmitter and Receiver Used in Such a System", disclosing
a DMT modem for multiple access (now U.S. Pat. No.
5, 809, 030) ;
U.S. Patent Application Serial No. 08/677,468,
filed July 10, 1996, entitled "Method for Allocating Data
Elements in Multicarrier Applications and Equipment to
Perform This Method'', disclosing ADSL bit allocation (now
U.S. Pat. No. 5,812,599);
U.S. Patent Applicaticn Serial No. 08/675,323,
filed July 10, 1990, entitled "Method of Allocation Data
Elements to a Set of Carriers, Mappir_~g Unit and Modulator
43
CA 02444239 2003-10-24
to Perform this Method", disclosing an ADSL BIGI Algorithm
(now LT. S. Pat. No. 5,790,550);
U.S. Patent A~oplica~~ion Serial No. 08/700,756,
ff led August 15, 1996, entitled "Method for Interleaving
Data Frames, Forward Error Correcting Device and Modulator
Including Such a Device", disclosing interleaving in ADSL
(now U.S. Pat. No. 5,907,560);
U.S. Patent Application Serial No. 08/718,641,
filed September 17, 1996, entitled "Sensing Circuit",
disclosing an activity detector for ADSL, where the CO is
quietly awaiting for remote activity {now U.S. Pat. No.
5, 963, 885) ;
U.S. Patent Application Serial No. 08/729,429,
filed October 11, 1996, entitled "Method for Transmission
Line Impulse Response Equalization. and a Device to Perform
this Method", disclosing an ISI reduction algorithm in an
analog (front-end) transceiver (now U.S. Pat. No.
5, 870,432) ;
U.S. Patent Application Serial No. 08/783,859,
filed January 16, 1997, entitled "Method and Modem for
Adaptive Allocation of the Pilot Carrier in a Multi-Carrier
System", disclosing DMT pilot tone reallacation (now U.S.
Pat. No. 5,867,528);
U.S. Provisional Applicatior~ Serial No. (Atty.
Docket No. 902-575) filed on even date herewith, entitled
"Method and Windowing Unit to Reduce Leakage, Fourier
Transformer and DMT Modern, Wherein the Unit is Used",
disclosing single frequency or banded noise immunity (which
gave rise to U.S. Pat. No. 6,240,129);
U.S. Provisional Application Serial No. (Atty.
Docket No. 902-576) entitled "Transmitter with Phase Rotor,
44
CA 02444239 2003-10-24
Modulator/Demodulator, Communications System and Method
Performed Thereby", disclosing a rotor for DMT (which gave
rise to U.S. Pat. No. 6,088,386);
U.S. Prov_sional Application Serial No. (Atty.
Docket No. 902-577) entitled "Method to Transparently
Transport an InCOming Clock Signal over a Network Segment
and Related Transmitter and Receiver IJnit", disclosing an
ATM time reference transport over ADSL (which gave rise to
U.S. Pat. No. 6,327,273);
U.S. Provisional Application Serial No. (Atty
Docket No. 902-578) entitled "A Method to Synchronize Data
and a Transmitter and Receiver Realizing Said Method"
disclosing reversal of clocks for ATM over ADSL (which gave
rise to U.S. Pat. No. 5,903,612,);
U.S. Provisional Application Serial No. (Atty.
Docket No. 902-579) entitled "Initialization Protocol for
Adaptive Data Rates and Related Transceiver", disclosing
ADSL rate renegotiation (which gave rise to U.S. Pat. No.
6,215,793);
U.S. Provisional Application Serial No. (Atty.
Docket No. 902-580) entitled "Method tc All.ocate Data Bits,
Multicarrier and Transmitter and Receiver Using the Method,
and Related Allocation Message", disclosing RFI reduction
in DMT systems (which gave rise to U.S. Pat.' No.
6,351,473);
U.S. Provisional Application Serial No. (.Atty.
Docket No. 902-581) entitled 'Priority-Based Access Control
Method and Arrangement", disclosing an earlier I* bus for
connecting an NT to LTs (WhlCh gave rise to U . S . Pat . No .
6,105,084);
CA 02444239 2003-10-24
U.S. Provisional Application Serial No. (Atty.
Docket No. 902-582) entitled "Current Control Interface
Arrangement", disclosing a power-up circuit (which gave
rise to U.S. Pat No. 5,951,660);
U.S. Provisional Application Serial No. (Atty.
Docket No. 902-583) entitled "Method for Prioritized Data
Transmission and Data T'ransriission Arrangement", disclosing
a preferred IQ bus for connecting an NT to LTs, as
described in Fig. 3 above (which gave rise to EP
application No. 0 881 853 published on December 2, 1998);
U.S. Provisional Application Serial No. (Atty.
Docket No, 902-585) entitled "Multicarrier Telecom System
with Power Adaptation Means" (which gave rise to U.S. Pat.
No. 6,246,725).
Although the invention has been shown and
described with respect to a best mode embodiment thereof,
it should be understood by those skilled in the art that
the foregoing and various other changes, omissions and
additions in the form and detail thereof may be made
therein without departing fram the spirit and scope of the
invention.
46
