Note : Les descriptions sont présentées dans la langue officielle dans laquelle elles ont été soumises.
CA 02507536 2005-05-13
Accelerated Stress Testing of Pixel Circuits for AMOLED Displays
Field of the Invention
The present invention relates to active matrix organic light emitting diode
(AMOLED) displays, more specifically to a pixel circuits, active matrix array
architecture, and the accelerated testing of such circuits and arrays at high
temperatures and high electrical stresses.
Background of the Invention
Amorphous silicon (a-Si) active matrix organic light-emitting diode
(AMOLED) displays have the potential to become the leading technology due to
their many advantages over LCDs. In a-Si AMOLED displays, the OLED is
coupled with a thin film transistor (TFT) pixel circuit that drives the
desired current
through it, thus the degradation in both the TFT circuit and OLED has to be
considered when determining the overall lifetime of the display. OLEDs are
routinely tested at high temperature and current, which accelerates the aging
of
the device, and the actual-use lifetime is then predicted by applying the
Arrhenius
model. However, no such acceleration method exists to test the a-Si TFT pixel
circuit degradation. Determining acceleration factors for pixel circuits is
not
straight-forward because the failure mechanism of the pixel circuits' is
governed by
multiple material and device effects, which are compounded by the self
compensating nature of the circuits. Nevertheless, there is an urgent need to
improve pixel circuit characterization throughput by reducing test times from
the
present 30000 hours to a more practical 5000 hours. The method presented in
this
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patent demonstrates how this can be achieved. The method can be directly
applied to other types of TFT technologies like polysilicon (p-Si) and organic
TFTs.
Summary of the Invention
It is an object of the invention to provide novel accelerated testing method
for V-r-shift compensating AMOLED pixel circuits
Aspects and features of the present invention will be readily apparent to
those skilled in the art from a review of the following detailed description
of
preferred embodiments in conjunction with the accompanying drawings.
Brief Description of the Drawings
The invention will be further understood from the following description with
reference to the drawings in which:
Figure 1: VT compensation mechanism in an AMOLED pixel circuit.
Figure 2: Time, temperature, and current dependence of VT-shift in a
132pm123pm
TFT under constant current stress.
Figure 3: IDS-VGS curves of a 200um123um TFT at different temperatures with
VDS=0.5V.
Figure 4: Variation of the initial VT of a TFT with temperature.
Figure 5: Variation of the effective mobility peff and the power parameter a
of a
TFT with temperature.
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Figure 6: Acceleration factors for voltage programmed circuits for different
temperatures and gate overdrive stress voltage ratios at VDD=20V and
W/L=20.
Figure 7: Acceleration factors for current programmed circuits for different
temperatures and drive current ratios at VDD=~OV and WIL=20.
Figure 8: Current programmed circuit acceleration factor graph showing that
temperature acceleration can be positive for certain values of current stress
(VDD=20V and WlL=20).
Figure 9: Acceleration factors for current programmed circuits for different
temperatures and drive current ratios at VDD=20V and 30V and WIL=40,
showing the transition point between positive and negative temperature
acceleration.
Figure 10: Demonstration of accelerated testing: 5000-hour measurement results
of the VGS of the drive TFT in an AMOLED pixel circuit operated at 300K
with (DRIVE=4pA (normal use), VDD=30V, and WlL=40. The normal use
measurements are compared to high temperature (350K) measurements
and high current stress measurements ((DRIVE=8pA).
Table 1: Applicability of a-Si pixel circuit accelerated testing theory to
different
types of AMOLED pixel circuits.
Table 2: a-Si TFT and pixel circuit parameters at 300K.
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Detailed Description of the Preferred Embodiments)
APPLICABILITY OF THIS TESTING METHOD
The accelerated testing method developed in this patent is valid for all types
of VT-
shift and variance compensating pixel circuits, including current programmed
[1,
2], voltage programmed [3, 4, 5], and external feedback circuits [6~, as shown
in
Table 1. This analysis does not apply to non-compensating circuits like the
conventional 2-TFT circuit [1]. Also, since the analysis is based on TFT
degradation phenomena, it cannot be applied to optical feedback circuits [7]
that
compensate for OLED degradation as welt as TFT degradation.
In this patent, we develop our theory assuming that there is only 1 TFT (the
current driving TFT) in series with the OLED in a pixel circuit, such as in
the
circuits shown in [1], [4], [6], and [7]. Some circuits ([2], [3], [5]) have
additional
switching TFTs in the OLED current path, which will cause a small voltage drop
and effectively reduce the Vpo. In order to accurately apply the analysis in
this
patent to such circuits, one has to calculate the expected voltage drop across
the
extra switch TFTs, subtract that voltage drop from Vpp, and use the resulting
voltage instead of the actuaP Vpd.
PRIMARY FAILURE MECHANISM
All VT-shift compensating circuits work by increasing the gate voltage VAS of
the drive TFT to overcome any increase in its VT, thereby allowing the drive
TFT to
supply a constant current to the OLED. Thus, the defects in the a-Si material
that
are responsible for the VT-shift manifest themselves through an ever-
increasing
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VAS as shown in Figure 1. This increase does not follow the traditional
stretched
exponential VT-shift model that has been developed for constant gate stress
voltages [8]. Instead, it seems to follow a power law relationship [9], which
is also
based on defect state creation but takes into account that Vas-VT (rather than
Vas)
is kept constant:
o vT (r~ _ (v~s (t) - vT (t>~ t
io Z . (1)
Here r and [3 are parameters that depend on the number of defect states and
hydrogen diffusion in the amorphous silicon layer [8].
The power law shows that there is no upper bound for Vas or VT of the drive
TFT
since it is under constant current stress. At some point in time Vas will
become
high enough to reach the supply voltage Vpo, causing the compensating
mechanism of the circuit to stop working. At that time, the TFTs in the pixel
circuit
will still be functional (albeit at a much higher VT), but the OLED drive
current will
no longer be independent of the VT of the drive TFT. If we consider that the
OLED
is in series with the drive TFT and has a voltage drop Vo~E~, we can see that
the
circuit compensation mechanism stops when Vas reaches VpD-VOLED~ This is the
primary failure mechanism of a-Si AMOLED pixel circuits, and the circuit
lifetime
can be defined as the time taken for Vas t0 reach Voo-VpLED due to VT-shift.
It is
important to note that common transistor failure mechanisms like insulator
degradation do exist in TFTs, but their time-to-failure is far longer than VT-
shift
related failure.
TIME-TO-FAILURE
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In order to quantitatively determine the time-to-failure of AMOLED'pixel
circuits,
we note that the increase in Vas is equal to the increase in VT, thus we can
say
that the circuit fails when
~GSO + ~VT (t = t.fail J = YDD ~OLED
where Veso is the initial gate voltage of the drive TFT, t~;, is the time to
failure, and
Vo~EO is the voltage drop across the OLED. For simplicity, we have assumed
that
Vo,~p does not change over time due to OLED aging. The analysis can easily be
repeated using a function VpLED(t) for more accuracy. We define the net supply
voltage available to the pixel circuit as
~DD - vDD vOLED .
Using equation (1 ) to substitute for ~VT and noting that V~s(t)-Vr(t) = V~so-
Vro
since it does not change over time, we get
vGSO 'f' \vGSO - Yro ~ tfit~ ~ _ ~nD
(4)
Thus, the time-to-failure is determined to be
yDD - yGSO
~fou = z
vGSO - yro , (5)
While Equation {5) is suitable for voltage programmed circuits, it cannot be
applied
to current programmed circuits since they do not control the Vas directly. For
the
latter, we can re-write equation (4) using the following Ips-Vcs relationship
for a-Si
TFTs (simplified from [10~):
IDs =f~etfC~ 2L (vGS -T~r)~'
(6)
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where Nevis the effective device mobility, C; the gate dielectric capacitance
per unit
area, and a a coefficient that ranges between 2 and 2.4 [10]. Thus;
_r _r
a a
I°s W + VTO + I°s W CtfytJ = VoD
u~C' 2L~. ~'~c' 2Le~ ' (~)
tfail y ~ 2L I~ a ~ ~VDD Vro ~ 1
pS
and . (8)
Even though the equations (5) and (8) for voltage programmed and current
programmed circuits have been derived from the same premise, they are distinct
cases since tfail for voltage programmed circuits does not depend on a and
peg,
while tfail for current programmed circuits does. Also, equation (8) applies
to
external feedback circuits even though they are usually voltage programmed.
This
is because feedback circuits generally sense the OLED drive current, and are
therefore affected by changes in a and ue~. On the other hand, if a certain
feedback circuit directly senses the V~ of the drive TFT and compensates for
it,
then its lifetime is predicted by equation (5).
ACCELERATION OF ~iT-SHIFT
High electrical stress is commonly used in the accelerated testing of
semiconductors. From equations (5) and (8) it, is apparent that higher gate
voltage
or drain current will lead to a shorter circuit lifetime, therefore they can
be used to
accelerate the failure of the circuit.
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The other commonly used acceleration method, high temperature testing, can
also
be applied to a-Si TFTs. The magnitude of Vrshift has been known to increase
with temperature [8]. We have characterized this increase by determining the
temperature dependence of VT-shift for TFTs subjected to constant current
stress,
the results of which are shown in Figure 2. We extracted ø and t using the
measurements in Figure 2 with the power law model of equation (1). The
measurements compare weH with literature [11, 12] and show that ø and r
exhibit
the following relationships with absolute temperature:
/3(T) = T I To - Rio , where øo = 0.28 and To = 400 K, (9)
Er
z(T) = zo exp
CkT where z =14.05 hours and E = 0.14eV. 10
, a ~ ( )
The maximum temperature and electrical stress that a pixel circuit can be
subject
to is limited by the presence of secondary effects like defect annealing and
insulator breakdown. Through our experiments we have determined that such
effects become significant at very high temperatures (>100°C),
therefore we
postulate that accelerated testing should be performed at temperatures no
higher
than 75°C. A thorough investigation into these effects will help define
a clear
demarcation point at which the secondary degradation mechanisms start to
dominate.
An important consideration during high temperature testing is the temperature
dependence of VTp, a, and peff. As explained in earlier, any variation in
these
parameters will affect the time-to-failure and acceleration factors. VAS-los
sweeps
of a TFT at various temperatures (Figure 3) reveal that the initial VT, the
effective
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mobility per, the power parameter a change with temperature as shown in Figure
4
and 5. We have modeled the behaviour of these parameters with the following
equations, which are consistent with models shown in [13, 14, 15]:
VT (T) = VT (0) - al ~ T , where VT(0) = 1.76 V and a~ = 0.0035 V/K, ( 11 )
a(T) - ao + 0.95q
kTp , where ao = 1.6 and p = 55.124 eV, and
(12)
_Eo
~'~(T) =~e~~e kT , where peg _ 199.53 cm2lVs and Eo = 0.1865 eV. (13)
The behaviour of the VT of an a-Si TFT with temperature is similar to that
observed in the crystalline silicon FET, where the VT decreases with
increasing
temperature due to the thermal generation of carriers in the channel. The
power
parameter a depends on the localized bulk states and by the a-Si-insulator
interface, and its observed dependence on temperature corresponds to the
results
shown in (15]. Since conduction in a-Si is trap limited, the effective
mobility peg in
a-Si TFTs is not physical, rather it is a measure of the conductivity of the
channel.
Therefore, the observed exponential relationship with temperature, which is
very
similar to the conductivity-temperature relationship, is expected. In the next
section, equations (9-13) will be essential in the calculation of acceleration
factors.
Finally, we would like to point out that even though equations (9-13)
generally
apply to all a-Si TFTs, the exact values of the parameters are highly process
specific and should be measured for every process.
ACCELERATION FACTORS
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The acceleration factor is the ratio of the time-to-failure under normal use
to the
time-to-failure under high stress conditions [16, 17]. We assume that normal
use is
at a temperature of 300 K, with the gate overdrive voltage V~so-VTO equal to
10V
(voltage programmed) or the OLED drive current IoRivs equal to SpA (current
programmed). V~so-Vro and IoR,vE are coefficients based on the image data and
do
not change with temperature or over time. For the sake of generality, we
assume
that the circuits are stress tested at temperature Ts (in Kelvin) and
programmed
with a voltage/current that is a factor of X higher than normal. That is,
(VGSO VTO )STRESS - X ' OGSO ~TO ) NORM ( 14)
Or jDRIVE-STRESS - X ' I DRIVE-NORM . ( 1 J)
Using the lifetime models derived above, we can obtain the following voltage
programmed circuit acceleration factor equation:
yDD - yGSO
AFy - tFAIL-NORM - ~~GSO yT0 )
tFAIL-STRESS rj~ - tJ ~~ lj('s)
DD GSO ~ S ) T
2~~5 ) ~ ~ X ' (vGSO - VTO )
( 16)
Since V~so is not readily available in a pixel circuit, it is better to
represent it as VT
plus a gate overdrive voltage. Thus,
yDD - OGSO - VTa ) + VTO 's
z wGSO - YTO )
AF,, 1
-~z~Ts)~ ~ ( o
yDD - ~X ' OGSO - yTO ) '~ YTO ~Ts )) ~~TS
X ~ ~VGSO ~TO )
. ~ ~ 7)
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In equation (17), V~op should be greater than {X (~oso WTO)+VTO(TS)}, and Vii,
r, and
VTO can be determined from equations (9-11 ). Similarly, we can derive the
current
programmed circuit acceleration factor to be:
~eff~'iW ~ r _
- OVDD _ ~TO ~ 1
2'Leff I DRlYE
AFB
t
=Cz(TS>~ 1
r R(TS )
~eff lTS) ~iW a~Ts)
x . 2L 1 vvDD - vTO CTS )O 1
efJ' DRIYE
(18)
We can see that there is a strong dependence of the acceleration factors
on the V pp of the circuits. This root cause of this dependence is that VT-
shift
becomes progressively slower as the operating time is increased. As a result,
there is a non-linear relationship between tfa;, and V'pD. Therefore, one has
to
specify the operating voltage when specifying acceleration factors for pixel
circuits.
We have plotted acceleration factors for voltage and current programmed
circuits
using the University of Waterloo inverted-staggered a-Si TFT process data
shown
in Table 2. Figure 6 shows voltage programmed acceleration factors AFv for
different temperatures and stress voltages. From the figure, we can see that
acceleration factors of around 8 are easily achievable by testing at 350K with
a
gate overdrive voltage that is 1.4. times the normal overdrive voltage. Thus,
a
30000-hour lifetime for a voltage pragrammed circuit can be assessed by
testing it
for approximately 4000 hours.
Figure 7 shows current programmed circuit acceleration factors AFB. These
factors are significantly different from those in Figure 6 because for X>0.6,
higher
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temperatures actually decrease circuit degradation. The reason negative
temperature acceleration is that even though higher temperatures increase VT-
shift, they also significantly increase the peg of the TFT. As a result, the
overall on-
resistance of the TFT decreases, and the circuit compensates for it by
lowering
the gate stress voltage, thereby causing less VT-shift. This effect does not
exist in
voltage programmed circuits, which is why AFv are substantially higher than
AFc.
In Figure 7, it is interesting to note that for current stress factors X<0.6,
the
temperature acceleration is indeed positive. This is seen more clearly in
Figure 8,
which shows that for 0<X<0.4, higher temperatures do result in more
acceleration.
The transition region is when 0.4<X<0.6, during which the effect of increasing
Neff
starts to dominate over the increasing ~VT. It is not useful, however, to keep
X<0.6
since the overall acceleration factor is less than 1 (i.e. we would actually
be
decelerating the degradation of the circuit).
The point at which the transition between positive and negative temperature
acceleration takes place is dependent on WIL and Vpp. From Figure 9 we can see
that for WIL=40 and Voc=30V, this transition happens when X=2 and AFc=4, thus
it is possible to get an overall acceleration factor that is greater than 1
solely due
to high temperature. Still, the effects of temperature acceleration diminish
when X
is increased significantly.
From the above discussion, we can conclude that because of current programmed
circuit action, it is not feasible to significantly accelerate the failure of
such circuits
using high temperature. Therefore, the only means available to obtain very
high
acceleration factors in current programmed circuits is to increase the current
stress factor X.
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LONG-TERM MEASUREMENT RESULTS
We have verified our theoretical analysis of accelerated testing by
performing long-term tests on three identical current programmed AMOLED pixel
circuits, each subject to a different level of current and temperature stress.
The
circuits had WIL=1000taml23Nm and Vpo=30V. Circuit 1 represents the normal use
case, and was stressed with a 4pA average drive current at 300K for 5000
hours.
Circuit 2 was stressed with a 4uA average drive current (X=1 ) at 350K for
high
temperature acceleration, while circuit 3 was stressed with an ,8pA average
drive
current (X=2) at 300K for high current acceleration. Figure 10 presents a
selection
of results from ongoing measurements. From Figure 10, we can see that the Vas
of the drive TFT of circuit 2 reached 11 V in about 2300 hours, while that of
circuit
1 reached the same level after 5000 hours, giving us AFB= 2.17. Likewise,
circuit 3
reached that level after 1000 hours, giving us AFc=5. These acceleration
factors
correspond very well with those obtained from eguation (18) and Figure 10.
Since
the measurements have been done for relatively short durations, these
acceleration factors only give us a rough estimate of the actual lifetime. The
acceleration factors will be more accurate when VGS approaches Vpp (i.e. when
circuit failure is imminent) after tens of thousands of hours of operation.
As is the case with any acceleration model, the more it is extrapolated, the
farther
it deviates from real conditions. For example, standard practice in the OLED
industry is to limit the acceleration factors in OLED testing to a maximum of
8
since predictions do not reflect the actual-use lifetime beyond that.
Therefore,
long-term statistical analysis based on a large number of circuits being
tested
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under normal and accelerated conditions is needed to determine the limits of
our
a-Si TFT lifetime and acceleration models.
SUMMARY
This patent addressed the urgent need to reduce the testing time of AMOLED
pixel circuits from tens of thousands of hours to around 4000-8000 hours by
developing an accelerated testing theory for such circuits. We quantified the
behaviour of threshold voltage shift, the primary failure mechanism, with
temperature and electrical stress and used the mode! to define the time-to-
failure
and acceleration factors. With this analysis, we have shown that acceleration
factors of around 8 are easily achievable for voltage programmed circuits,
while
factors of 4 are achievable for current programmed circuits, the difference
being
attributed to the fact that the latter also compensate for changes in the
effective
mobility of the TFT. While our theory can be broadly applied to all types of a-
Si
AMOLED pixel circuits, the acceleration factors should be recalculated for
different
fabrication processes.
