Note : Les descriptions sont présentées dans la langue officielle dans laquelle elles ont été soumises.
CA 02544090 2006-04-19
STABLE DRIVING SCHEME PREVENTING THE ACCUMULATIVE
AGING IN ACTIVE MATRIX DISPLAYS
FIELD OF THE INVENTION
The present invention generally relates to light emitting device displays, and
particularly, to a
driving technique for AMOLED, and to enhance the lifetime of the displays.
SUMMARY OF INVENTION
The new method reduces the aging speed by dividing the frame into driving and
relaxation
(annealing) phase.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 shows the proposed timing schedule.
FIG. 2 shows a 2-TFT pixel circuit and proposed compensation scheme.
FIG. 3 shows the lifetime results for the compensated and conventional driving
scheme.
FIG. 4 shows the modified frame time of 2-TFT based on proposed timing
schedule.
FIG. 5 shows the lifetime results for the compensated 2-TFT with the proposed
timing schedule.
DETAILED DESCRIPTION
FIG. 1 shows the proposed timing schedule that suppresses the aging for pixel
circuits in
AMOLED displays. As will be explained later, the measurement results show that
letting the
pixel relax for a fraction of each frame can control the aging of the pixel
including the aging of
the driving devices (i.e. TFTs), and the OLED. Thus, a frame can be divided
into three phases:
programming, driving (i.e. emitting), and relaxing. During the programming
cycle, pixel is
programmed with required data to provide the wanted brightness. During the
driving cycle, the
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CA 02544090 2006-04-19
OLED emits required brightness based on the programming data. Finally, during
the relaxing
cycle, the pixel is OFF or biased with reverse polarity of driving cycle.
Consequently, the aging
effect causes by driving cycle is annealed. This prevents aging accumulation
effect from one
frame to the other frame, and so the pixel life time increases significantly.
However, to obtain the wanted average brightness, the pixel must be programmed
for a higher
brightness since it is OFF for a fraction of frame time. The programming
brightness based on
wanted one is given by
2F
LCP = LN (1)
Z'F - ZR
in which LcP is the compensating luminance, LN the normal luminance, TR the
relaxation time,
and TF the frame time.
In the following, we review a pixel example employing this method, but it must
be denoted that
the above timing schedule is applicable to any other pixel circuit despite its
configuration and
type.
FIG. 2 shows a 2-TFT pixel circuit and a compensating driving scheme. The
operation of the
pixel can be explained as the following.
During the first operating cycle (VcP_Ge1), VDD changes to a negative voltage
(-VCPB) while
VDATA has a positive voltage (VCPA). Thus, node A is charged to VCPA, and node
B is
discharged to -VCPB. During the second operating cycle (VT_Ge1), VDD changes
to Vdd2, i.e. the
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voltage during the driving cycle. As a result, node B is charged to the point
at which Tl turns off.
At this point, the voltage at node B is VCPA-VT, and the voltage stored in the
storage capacitor
(Cs) is the VT of T1. It is worth mentioning that VCPA should be smaller than
VTO+VOLEDO, where
the VTO is the threshold voltage of the unstressed T1 and the VOLEDO is the ON
voltage of the
unstressed OLED. During the third operating cycle, VDATA changes to a
programming voltage,
VCPA+VP. Assuming that the OLED capacitance (CLD) is large, the voltage at
node A remains at
VCPA-VT. Therefore, the gate-source voltage of T1 ideally becomes VP+VT.
Consequently, the
pixel current becomes independent of the AVT and AVoLED.
FIG. 3 signifies the effectiveness of the compensating driving scheme. the
pixel circuits are
programmed for 2 A at a frame rate of -60 Hz by using both the conventional
and the novel
compensation driving schemes. It is evident that the newly designed driving
scheme is highly
stable, reducing the total aging error to less than 11 %. However, the aging
effects result in a 50%
error in the pixel current over the measurement period in the conventional
driving scheme. The
total shift in the OLED voltage and threshold voltage of Tl (A(VOLED+ VT) ) is
-4 V.
FIG. 4 shows a frame using compensating driving scheme and the proposed timing
schedule
presented in FIG. 1. Two new operating cycles are added to the pixel operation
as shown in FIG.
4. During the first operating cycle of the kth row, SEL[i] is high, and so the
storage capacitors of
the pixel circuits at the ith row are charged to VCPA. Considering that VCPA
is smaller than
VOLED+VT, the pixel circuits at ith row are OFF and also the corresponding
drive TFTs are
negatively biased resulting in partial annealing of the VT-shift.
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CA 02544090 2006-04-19
FIG. 5(a) demonstrates a longer lifetime test for the pixel circuit employing
the newly developed
timing cycles. The result signifies that the above method and results in a
highly stable pixel
current even after 90 days of operation. Here, the pixel is programmed for 2.5
A to compensate
for the luminance lost during the relaxing cycle. The A(VOLED+ VT) is
extracted once after a long
timing interval (few days) to not disturb pixel operation. The result depicted
in FIG. 5(b)
confirms that the enhanced timing diagram suppresses aging significantly,
resulting in longer
lifetime. Here, A(VOLED+ VT) is 1.8 V after a 90 days of operation, whereas it
is 3.6 V for the
compensation driving scheme without the relaxing cycle after a shorter time.
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