CIRCUIT DE MEMOIRE

MEMORY CIRCUIT

Abrégé anglais

ABSTRACT OF THE DISCLOSURE
This invention relates to an improvement in a video
signal playback device which derives video signals from a
track on a video disc using a light source impinging upon an
information track on the surface of the video disc, the light
beam modulated by the information track being sensed in a light
sensor. In prior art devices, poor picture quality has resulted
from the fact that focus of the beam on the information track
cannot be maintained dynamically, that is as the turntable
rotates and the disc and read head move relative to one another
radially of the disc. The present invention overcomes the
deficiencies of the prior art in this respect by providing
a reader and disc arranged for relative lateral movement
radially of the disc wherein an objective lens mounted in the
disc reader adjacent the disc maintains focusing of the light
beam on the information track of the disc as the disc is played.
The objective lens is mounted for movement relative to the
surface of the disc along the path of the impinging light beam
to maintain focus of the beam on the information track as the
rotating disc moves laterally relative to the reader.

Revendications

WHAT WE CLAIM IS:
1. A memory circuit under the logical control
of three inputs, comprising a semiconductor element
circuit of equivalently a four layer PNPN structure and
at least one PNP transistor and NPN transistor, wherein
the PNP transistor is connected at its collector to the
base of the NPN transistor and the NPN transistor is
connected at its collector to a control gate of the
semiconductor element circuit, whereby the emitter and
base of the PNP transistor and the emitter of the NPN
transistor function as logical input terminals, respec-
tively.
2. A memory circuit under the logical control
of three inputs, comprising a semiconductor element
circuit of equivalently a four layer PNPN structure, one
PNP transistor, one NPN transistor and one resistor,
wherein the PNP transistor is connected at its collector
to the base of the NPN transistor and the NPN transistor
is connected at its collector to a control gate of
the semiconductor element circuit with the resistor
connected at its one end to the base of the NPN transistor
and grounded at the other end, whereby the emitter and
base of the PNP transistor and the emitter of the NPN
transistor function as logical input terminals,
respectively.
3. A memory circuit under the logical control of
three inputs, comprising a semiconductor element circuit
of equivalently a four layer PNPN structure, one PNP
transistor, one NPN transistor and two resistors,
wherein the PNP transistor is connected at its collector


to the base of the NPN transistor and the NPN transistor
is connected at its collector to a control gate of
the semiconductor element circuit with the first
resistor connected at its one end to the base of the
PNP transistor and with the second resistor connected at
one end to the base of the NPN transistor and grounded
at the other end, whereby the emitter of the PNP
transistor, the other end of the first resistor and
the emitter of the NPN transistor function as logical
input terminals, respectively.
4. A memory circuit under the logical control of
three inputs, comprising a semiconductor element circuit
of equivalently a four layer PNPN structure, one PNP
transistor, one NPN transistor, two resistors and one
diode, wherein the PNP transistor is connected at its
collector to the base of the NPN transistor and also
connected at its base to the first resistor through
the diode, and the NPN transistor is connected at its .
collector to a control gate of the semiconductor
element circuit with the second resistor connected
between the base of the NPN transistor and the ground,
whereby the emitter of the PNP transistor, the other
end of the first resistor and the emitter of the NPN
transistor function as logical input terminals,
respectively.
5. A memory circuit under the logical control
of three inputs, comprising a semiconductor element
circuit of equivalently a four layer PNPN structure, one
PNP transistor and two NPN transistors, wherein the PNP
transistor is connected at its base to the collector



of the first NPN transistor, and also connected at its
collector to a control gate of the semiconductor
element circuit, and the first NPN transistor is
connected at its emitter to the collector of the second
NPN transistor which is grounded at its emitter, whereby
the emitter of the PNP transistor, and the bases of
the first and second NPN transistors function as logical
input terminals, respectively.
6. A memory circuit under the logical control
of three inputs, comprising a semiconductor element
circuit of equivalently a four layer PNPN structure, one
PNP transistor, two NPN transistors, three resistors
and one diode, wherein the PNP transistor is connected
at its base to the collector of the first NPN transistor,
at its collector to a control gate of the semiconductor
element circuit and at its emitter to the one end of
the first resistor, and the first NPN transistor is
connected at its emitter to the collector of the second
NPN transistor and at its base to the one end of the
second resistor with the base and emitter of the second
NPN transistor respectively connected to the third
resistor through the diode and direct to the ground,
whereby the other end of the first resistor, the other
end of the second resistor and the other end of the
third resistor function as logical input terminals,
respectively.

11

Description

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The present invention relates to a memory circuit,
and more particularly to a memory circuit including a semi-
conductor element circuit of equivalently a four layer PNPN
structure under the control of three logical inputs x, y and z
to provide a zero OFF-holding power.
In one aspect of the invention t~here is provided ;
a memory circuit under the logical control of three inputs,
comprising a semiconductor element circuit of equivalently
a four layer PNPN structure and at least one PNP transistor
and NPN transistor, wherein the PNP transistor is connected
at its collector to the base of the NPN transistor and the
NPN transistor is connected at its collector to a control gate
of the semiconductor element circuit/ whereby the emitter and
base of the PNP transistor and the emitter of the NPN
transistor function as logical input terminals, respectively.
In order that the invention may be readily carried
into effect, it will now be described in detail, by way of
example, with reference to the accompanying diagrammatic `
drawings, in which:
Fig. 1 is a circuit diagram of a well-known memory
:
circuit using a semiconductor element circuit of four PNPN
layer structure with two inputs;
Fig~ 2 is a truth table of the memory circuit with
two inputs;
Fig. 3 is a block diagram of a memory circuit
arranged in a matrix according to the present invention;
Fig. 4 is a truth table of a memory circuit
with three inputs;




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Fig~ 5 is a circuit diagram of a first embodiment .
of a memory circuit according to the present invention;
Fig. 6 is a circuit diagram of a second embodiment
of a memory circuit according to the present invention; :.
Fig. 7 is a circuit diagram of a third embodiment
of a memory circuit according to the present inventlon; .
Fig. 8 is a circuit diagram of a fourth embodiment
of a memory circuit according to the present

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1 invention; and
Fig. 9 is a circuit diagram of a. fifth
embodiment of a memory circuit according to the present
invention.
There are two circuit connections for memories,
a symmetrical circuit such as a flip-flop circuit which
consumes power in both "ON" and "OF~"' modes, and an
a.s~nmetrical circuit requiring no power comsumption
in the "OFF" mode with the aid of a. self-holding effect `.
which a semiconductor element circuit of a four layer
PNPN structure has. The former circuit is usually
often used because of its excellent cha.racteristics in
: view of stability of operations, high speed response,
etc.~ but t~e latter circuit also has the possibility to
provide an excellent memory with maximum utilized
advantages when used in the field where the low power
is strictly required but the high speed response is
of less importance~ For example~ the memory used in a.
holding circuit for speech path switches of a telephone
20 exchange system has the most OFF-holding modes and ~ ~r
there~ore has the requirement o~ the low power and the
less requirement of high speed response. Fig. 1 shows ~ .
a known memory circuit adapted for use in the holding
circuit for the speech path switch. The memor~ circuit
functions according to a truth table shown in Fig. 2, in
which QtN and QtN+1 denote the memory circuit output at
Nth and (N~l)th points of time, respectively, and has
the exeellent characteristic that a logical input
section thereof comprising a transistor Ql and a
resistor Rl as well as a memory cell comprising transistors
Q2~ Q3 and a resistor R2 both have the power consumption
. of zero ~n the OFF-holding state. The memory circuit,



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l however~ has the drawback that either one of memory
cells should always ~e selected because of two inputs,
when taking into account that the memory circuit is
connected in a matrix to enlarge a memory ca.pacity and
a decoder for selecting the x, y inputs is connected
in the preceding stage. To eliminate the drawback, the
third control input z was conventiona.lly added to the
. memory circuit besides x, y inputs with its functions
conformed so as to satisfy a truth table shown in
Fig. ~ as shown, for example, in Fig. 3 where a
plurality of memory circuits (Mll ... Mmn) a
in a matrix. It is to be noted that a switching element
such as a transistor is turned on or off in response
to an output signal. from the memory circuit when it
is used in the speech path switch, although in Fig. 3
the output citcuit of the memory circuit is shown as
eliminaked.
A method for providing the z input termina.l is
2 to use an AND gate, the use of which, however, lea.ds to
the drawback tha.t the power is consumed in the controlling
logical input section when the z input is in the "0"
holding mode, and the AND gate disadvantageously increases
in number when a memory of large capa.city is intended
to be manufactured.
An object of the present invention is to
provide a memory circuit including a semiconductor
element circuit of equivalently a four layer PNPN
structure with the OFF-holding power of zero or low power
consumption under the control of three logical inputs.
The present invention provides a memory circuit

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1 under the logical control of three inputs~ comprising
a semiconductor element circuit of equivalently a our :~
layer PNPN structure, and at least one PNP transistor and
NPN transistor. The PNP transistor is connected at its
collector to the base of the NPN transistor and the NPN
transistor is connected at its collector to a control
gate of the semiconductor element ci.rcuit so tha.t the
emitter and base of the PNP transistor and the emitter
of the NPN tra.nsistor may function as logical input ;~
terminals, respectively.
Figs. 5 shows the first embodiment of a memory
circuit according to the present invention. Ql and
Q4 show an NPN tra.nsistor and PNP transistor which form
a logical input section for controlling a memory cell,
Rl a. resistor for defining the current flowing in the
logical input section, Q2' and Q3 a PNP transistor a.nd
NPN transistor which form the memory cell of the
seimiconductor element circuit of equivalently a four :.
layer PNPN structure, R2 a resistor for defining the ON- ~
20 holding current of the memory cell, Vcc a termina.l of a .
power supply, x, y, z logical input terminals,
respectively, and Q an output terminal. This circuit
functions according to the truth table shown in ~ig. 4.
It is to be noted that the z input receives inversed "1"
and "0", but no problem arises if the z input is inversed
prior to its applica.tion.
The memory circuit has the zero power consump-
tion because the memory cell is formed of the semiconductor
element circuit o~ equiYalently a four layer PNPN structure.
~urther, when the logica.l input section is in the "1"



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3109
1 holding condition of the z input, the PNP transistor Q~
is cut off and the NPN transistor is cut off in turn,
so that the logical input section has the power consump-
tion of zero.
On the other hand~ the PNP transistor Q4 and
NPN transistor Ql are off in the "O" z input and the
"O" holding state of the y input.
In other words, the memory circuit with the
zero power consumption in both the memory cell and the
logical input section can be obtained in the "off"
holding mode of the memory cell comprising the semi-
conductor element circuit of equiv~lently a four
layer PNPN structure.
Fig, 6 shows the second embodiment of the
memory ircuit according to the present invention~ in
which a resistor R3 for discharging a storage charge
is connected to a connection between the transistors
Ql and Q4 in the memory circuit shown in Fig. 5. Other
circuit elements and their operations are the same as
those shown in Fig. 5.
In Fig. 7 there is shown the third embodiment
of the memory circuit according to the present invention,
in which a level shifting diode Dl is connected to the
z input terminal of the memory circuit shown in Fig. 6
25 to increase a noise immunity of the circuit. It is
to be noted that the level shifting device may be
connected to the other input terminals or the emitter
of the NPN transistor Q3, the element of the semiconductor
element circuit.
Fig. 8 shows the fourth embodiment of the




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1 memory cricuit according to ihe present invention~ in
which Q2' Q3 show a PNP transistor and NPN transistor
. both constituting the memory cell of the semiconductor
element circuit of equivalently a four layer PNPN struc-
ture, Q~ and Q5, Q6 a PNP transistor and NPN transistorsconstituting the logica.l input section for controlling
the memory cell, Rl, R4~ R5 resistors for defining the
current to the logical inputs, R2 a resistor for defining ..
the ON-holding current of the memory cell, and Dl, D2
level shifting diodes provided to form a level in
accordance with the logica.l input section. Vcc shows
a terminal of the power supply, x, y, z logical input
terminals, respectively, and Q an output terminal. This
circuit functions a.ccording to the truth table shown in
15 Fig. ~. In this memory circuit~ the memory cell
consumes no power in the off state because it is
eonsidered to be the semiconductor eJ.ement circuit of
equivalently a four layer PNPN structure. The logical
input section., on the other hand, has its transistors
~ Q~' Q5' Q6 cut off in the "O" holding mode of the z
input, thus having -the zero power consumption. The
memory circuit with the zero power consumption can,
therefore~ be achieved in the z input of "O" and in the
OFF-holdin~ mode of the memory cell. In the z input
25 of "l" and in the "O" holding sta.te of the y input, the
eireuit consumes the power due to the current flowing
from the z input into the base of the NPN transistor
Q5, but has the very small power consumption at this
time because the transistor Q5 is cut off and thus the
transistor Q6 has no collector current. It is~ therefore,

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1 possible to provide the substantially low power consump-
tion also in the OFF-holding mode. Further, the low
power consumption can be obtained more efficiently iIl
the use of this memory circuit if a logic is designed
by which the more holding modes are realized by the z
input of '10ll,
Fig. 9 shows the fifth embodiment of the
memory circuit according to the present invention, in
which a level shifting diode D3 is connected to the z
input terminal of the memory circuit shown in Fig. 8
to increase the noise immunity of the circuit.
In each embodiment shown in Figs. 5 to 9 it
is understood that the resistors Rl, R4 and R5 may be
suitably removed when input current from an enabling
circuit in a preceding stage is limited. Furthermore,
the level shifting diodes Dl and D2 are connected at
the side of the semiconductor element circuit in the
embodiments shown in Figs. 8 and 9, but it would be
understood that they may be replaced by transistors,
etc. Further, a transistor may be connected to provide
the output Q, although it is derived from the collector
of the NPN transistor Q3 constituting the semiconductor
element circuit of equivalently a ~our layer PNPN structure
in each of the above-mentioned embodiments.
As mentioned above, the memory circuit according
to the present invention, having the logical control
input section with the three inputs x, y, z, makes it
possible to enlarge its functions and has the low power
consumption with the zero power consumption in the
logical input section in the holding mode generated by

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1 the z input and with the zero OFF-holding power in the `,~
memory cell. The use of the memory circuit according
to the present invention can, therefore, provide a
memory with la.rge capa.city in accordance with the
5 blocks shown in Fig. 3. In this case, the logica.l -
input section including the transistors Q4, Q5 and
the memory cell including the transistors Q2' Q3 must
be increased depending upon the desired memory capacity,
but it is understood that only one transistor Q6 is
10 required to take charge of the z input. In other words, :
the collector of the transistor Q6 can be combined with ,~
the emitter of the tra.nsistor Q5 in a multi-connection : .
to provide the memory shown in Fig. 3 with the result of
economization of the elements in number.



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