Note : Les descriptions sont présentées dans la langue officielle dans laquelle elles ont été soumises.
11~02J~
~itle of the Invention:
PEASE DISC~IMINA~OR
Field o~ the Invention
The pre~en~ inventio~ rela~es to radio engineerine and,
more particularl~, the invention relates to phase di~crimi-
nator~.
~ he invention may successfully be used in ~ystems for
pha~e automatic fre~uency control, in particular, in analog
computers, in ultrasonic flow meters, ~or ~eparation of
signal~ proportional to the pha3e mismatch between the
pulse trains.
Backgrou~d o~ the Invention:
Enown in the ar~ i~ a pha~e discriminator (c~. U~SR
Inventor'~ Certi~icate ~o. 534031, cl. H03 K 9~04) who~e
one input receives a reference signal and i~ electrically
connected to one of the inputs of a first memor~ element
connected to one of the inputs of a first coincidence circuit,
while the other input of the pha~e di~criminator ~ed with
a Rignal to be anal~zed is electrically connected to one of
the inputs o~ a secondar~ memory element connected to one
of the inputs o~ a second coincidence circuit whose out-
put, as ~ell a~ the output of the first coincidence circuit,
are corre~ponding outputs o~ the phase di3criminator.
Furthermore, the ~i~en discriminator include~ two in~erters,
the input o~ one inverter being connected to the discrimina-
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21 8
tor input ~ed with the reference signal and the input of
the other inverter being connected to the discriminator
input ~ed with the signal to be analyzed; the outputs of
the inverters are con~ected to the inputs o~ the ~econd-
memory element. ~urthermore~ in the given discriminator
the other input~ o~ the ~irst and second coincidence cir-
cuits are connected respectiYely to the outputs o~ the
second and first memo~y elements.
Ho~ever, ~n the knot~m discriminator a time delay o~
the signal~ in the in~er~er~ re~ults in appearance of pulse~
at one of its output~, the duration of these pul~e~ di~e-
ring ~rom the error in the compared pul~e trainæ b~ a time
period equal to the delay time in the inverter~. In this
ca~e at the other output o~ the inverter pulses are produ-
ced, the duration of which i~ equal to the delay time in
the inverters. However, since these pulses ~ignal about
the ~rror in the compared pulse train~ in the direction
opposite to the true one, the resolution of the known
discriminator is limited b~ a value equal to the double
delay time in the inverters.
In addition, the circui~ry o~ the known discriminator
i~ developed so that one o~ it~ inputæ i9 to be ~ed with a
reference signal only of the meander type, and this limit~
the field o~ application o~ thi~ de~ice.
~ urthermore, the k~own discriminator ~eatures poor
noise immunity.
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Brief Description of the Invention
An object o~ the present in~ention is to provide a phase
discriminator m~ing it possible to increase th~ resolution
o~ the phase automatic ~requency control.
Another object o~ the pre~ent in~ention is to provide
noise immunity o~ the phase discriminator.
These objects are attained by pro~iding a pha~e discri-
minator, one input of which receives a reference signal and
which i8 electrically connected to one of the inputs of a
; first memo~y element connected to one o~ the inputs of a
first coincidence circuit, while tha other input of the
discriminator is ~ed with a signal to be analyzed and which
is electrically connected to one of the inputs o~ A gecond
memory element connected to one o~ the inputs of a second
coincidence circuit ~hose output, as well as the output o~
the ~irst coincidence circuit, are respective outputs o~
the phase discr~min~tor; according to the invention, the
discriminator input fed with a reference signal i~ electri-
cally connected to the other input of the second coincidence
circuit, v~hile the discriminator input fed with the si~nal
to be analyzed is electrically connected to the other input
of the ~irst coincidence circuit; the discriminator ha3
still another mput to receive a gate sign~l, w~ich is elec-
trically connected to the setting inputs o~ the iirst and
second memory element and to other inputs o~ the ~irst and
second coincidence circuits.
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~1402~8
~ he present invention makes it possible to determine
the real time of mi~match of the compared pulse train~ of
the reference and analyzed signals and thi~ increases the
resolution o~ the proposed phase discriminator.
Furthermore, the present invention provides simultane~
ous presence of short pulse~ o~ equal length at the outputs
of the phase discriminator, when tho phase dif~erence of
the compared pulse train~ of the reference and analyzed
signals is e~ual to zero, and this provides continuou~
operation of the actuating device of the phase automatic
~requency control system and this, in turn, improve~ the
resolution of the phase di~criminator.
What is more, the present invention proYides pha~e
automatic frequency control for a selected pulse train and
this provide~ noise immunity of the system.
- Brief Description of the Drawings
Other obaects and inherent advantages of the present in-
vention will be clear from a description o~ one particular
embodiment o~ the invention with reference to the acco~panying
drawings, in which:
Fig. 1 shows a schematic diagram of the phase discrimi-
nator according to the invention;
Fig. 2 a, b, c, d, e, f, 8 show time diagrams of ~hc
signals acting in the phase di~criminator shown in ~igol~
according to the invention.
~ 5 ~
;~ Detailed Description o~ the Invention
~ he phase discriminator comprise~ two m~mo~y element~
1, 2 (Fig.l), the respective inputs 3, 4 of which are its
input 5 receiving a reference signal UO and it~ input 6
receiving a signal to be ~nalyzed Ul. Connected to the
outputs o~ the elements 1 and 2 are circuit~ 7 and 8
through it~ repsective input~ 9 and 10. ~he other inputs 11
and 12 of the respective circuits 7 and 8 are connected to
the discriminator inputs 6 and 5 respectively. The discri-
minator has an input 13 to receive a gate signal ~2 and to
be connected to the ~etting input~ 14 and 15 o~ the elements
1 and 2 respectively and the inputs 16 and 17 o~ the cir-
cuits 7 and 8 respectively. ~he outputs 18 and l9 of the
circuits 7 and 8 are di~criminator outputs.
The phase discriminator operate~ as ~ollows.
With no ~ate ~ignal U2(shown in ~ig. 2a) at the input
13 (~ig.l) o~ the phase discriminator the memory elements
1, 2 are set to a bias unit state by the corresponding
setting inputs 14 and 15. Upon arrival o~ the re~erence sig-
nal UO (shown in ~ig. 2 b) and the signal Ul to be analyzed
( sho~n in Fig. 2c) to the correspondi~ inputs 5 and 6
(~ig.l) of the phase discriminator and, therefore, at the
respective inputs 3 and 4 o~ the memory element~ 1 and 2,
these eleme~t~ 1 and 2 are set to the zero state.
In this case the memo~y elements 1 and 2 operate with pri-
ority by the setting i~puts 14 and 15.
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114C~218
When the gate signal U2 (Fig. 2a) is applied to the
input 13 (Fig.l) of the phase di~criminator, the memory
element~ 1,2 are prepared ~or operation (a signal i~ ap-
plied to the input~ 14 and 15 of the memory elements 1,2~
which permits recordin~ o~ information into these elements),
~nd the gate signal ~2 (Fi~. 2a~ gives permission at the
input~ 16, 17 (Fig.l) of the respective coincidence circuits
7~ 8. Furthermore, a permis~ive signal is ~ed to the inputs
9 and 10 o~ the respective coincidence circuits 7 and 8
from the memory eleme~t~ 1 and 2, ~inc~ the memory element~
1 and 2 have been set to unity state without ~ gate sign~l
U2 (Fig.2)-
According to the invention, one o~ the signals~ e.g.the re~erence signal Uo(Fig. 2b) is associated with the
gate signal U2 (Fig.2 a) so tha~ the leading edge of each
re~erence pulse of the train o~ re~erence pulqes of the re-
~erence ~ignal UO (Fig. 2b) is within the gate pulse from
the train o~ gate pulses of the gate ~ignal U2 (Fig.2a).
Let us consi~er the operation of the discr~minator
under three dif~eren~ conditions o~ phase mismatch o~ t~e
compared sign~ls.
I~ the pul~e 20 (shown in Fig.2c) o~ the analy~ed ~ig-
nal Ul lags behind the re~erence pulse 21 (~hown Ln Fig. 2b)
of the re~erence si~nal UO~ at the output o~ the memory
ele~ent 2 (Fig.l) to the moment of arrival of the re~erence
pulse 21 (Fig. 2b~ there will be preserved the pre~iously set
bias u~it state shown in Fig. 2d~
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11~0218
When the reference pulse 21 (Fig. 2b) i9 applied to
the i~put 12 (Fig.1) of the coincidence circuit 8, at it~
output 19 (Fig.l) ~here appears a delay pulse 23 (shown
in Fig. 2e) signalling that the pulse 20 (~ig. 2c) of the
analyzed signal Ul la~ behind the pulse 21 (~ig. 2b) of
the reference signal U0.
In order to increase the noise immunity, according to
the in~ention, the dura~ion of the pul~e 23 (Fig. 2e) is
limited by the gate pulse 22 (Fig. 2a) applied to the input
17 (Fig.l)of the coincidence circuit 8, i.e. at large va-
lues of the mi~match the dura~io~ o~ the pulse 2~ (Fig.2e)
is fixed.
Under the ~ext operating conditions of the phase
discriminator at lo~ delay values (within the range of
the gate pulse 24 shown in Fig. 2a) o~ the analyzed pulse
25 (shown in ~ig. 2c) from the reference pulse 26 (shown
in Fig. a b)9 the duration of the delay pul~e 27 (shown
in Fig. 2e) signalling about the lag of the pulse 25 (~ig. 2c)
of the analyzed signal Ul with respect to the pulse 26
(Fi~. 2 b) of the re~erence signal UO at the output 19
(Fig.l) o~ the circuit 8 i9 equal to the mismatch ~alue,
becaus~ the leading edge of the analyzed pulse 25 (Fig. 2c)
fed to the input 4 (Fig.l) of the ~emory element 2 bia~e~
this eleme~t 2 to a zero state (shown in Fig. 2 d). Thus,
the passage of the reference pulse 26 (Fig. 2b) through
the circuit 8 i8 inhibited.
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ll~QZ18
Under the con~idered operating conditions o~ the phase
discriminator there is no signals at the output 1~ (~ig.l)
of the circui~ 7 and, therefore, at the discriminator output.
I~ the third form of operation of the phaae discrimi-
nator, when the analyzed pulse 28 (shown in Fig. 2c) advances
the reference pulse 29 (~hown in Fig. 2b), the output of the
memory eleme~t 1 (Fig. 1) is biased to the unit state (shown
in Fig. 2~) te the moment o~ arrival of the pul~e 28 ~Fig.
2 c). When a gate pulse 30 (~ig. 2a) is applied to the in-
put 16 (Fig.l) of the coincidence circuit 7, at its ;output
18 there is produced a pulse 31 (shown in Fig. 2 g) indica~ing
that the pulse 28 (Fig. 2c) being analyzed advances the
re~ere~ce pulse 29 (Fig. 2b). In this case the leading edge
o~ the pulse 31 (Fig. 2g) is coincide~t with the leading
edge of the pul~e 28 (Fig.2c). The trailing edge of the
pulse 31 (Fig. 2g) is coincident with the leadi~g edge o~
the pulse 29 (Fig. 2b) biasing the memory element 1 (Fig.l)
to zero by the input 3 (Fig. 2f). ~hu~, i~hibition is made
for fuI~her pa~sa~e of the analyzed pulse 28 (Fig. 2c) fed
to the input 11 (Fig.l) of the circuit 7, i.e. the duration
o~ the pul~e at the output 18 (~ig 1) 0~ the circuit 7 will
be equal to the value of mismatch between the reference
pulse 29 (~ig. 2b) and the analyzed pul~e 28 (Fig. 2c). In
thi~ case no pulse i9 produced at the o~tput 19 (~ig.l) oX
the circuit 8, ~ince with the arrival of the advanced ana-
lyzed pul~e 28 (~igo 2c) the memor~ element 2 (Fig.l) i8
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~14{~218
set to the zero state (Fig. 2d) before arrival o~ theleadin~ edge o~ the re~erence pulse 29 (Fig. 2b). ~hus,
~he passa~e of the re~ere~ce pulse 29 (Fig. 2b) through the
circuit 8 (Fig.l) i~ inhibited. ~hen the action of the gate
pulse 30 (Fig. 2a) is over, the memory elements 1,2 (Fig.l)
are again set to their i~itial co~dition.
~ hus, when the ~ignal Ul (Fig. 2c) being analyzed lags
i~ phase behind the re~erence ~ignal UO (Fig. 2b) or advances
this signal within the range of the gate signal U2 (Figo 2a),
a delay pulse 27 (Fig. 2e) and an ad~ance pulse 31 (Fig. 2g)
are produced respectively at the outputs 19 and 18 (Fig.l)
of the corresponding circuit~ 8 and 7. In thi~ case the
dura~ion of the pul~es 27 (Fig. 2e) and 31 (Fig. 2g) is
proportional to the di~erence of the phases o~ the analyzed
signal ~1 (Fi~. 2c) and reference signal UO (Fig. 2b).
If the length of the analyzed signal Ul (Fig. 2c) is
not ~ithin the ra~ge o~ the gate signal U2 (Fig. 2a), at
the outpu~ 19 ~Fig.l) o~ the circuit 8 there is produced
a pulse 23 (Fig. 2e) having a duration from the leadin~
edge o~ the re~erence pulse 21 (Fig. 2b) to the training
edge o~ the ga~e pulse 22 (Fig. 2a), i.e. havi~g max~mum
duration and this pulse 23 (~ig. 2e) ~a~ be uAed ~or pha~e
detection.
~ hus, in the proposed phase discriminator the phase
au~omatic freQuency control of, for example~ a~ oscillator
being studied (not sho~n in the drawings) producing
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li4(g2~18
pulse~ o~ ~elected sequence can be ef~ected by matching
the train of gate pulses with one of the ~erie~ of coherent
pulse trains supplied as a re~erence ~ignal.
The present invention ha~ tec~nical and economic~l
advantage~, ~ince in this invention improvement of
technical parameter~ is combined with a simple ~d reliable
circuitry.
