ETALONNAGE HYBRIDE DE COURANT DE POLARISATION

HYBRID CALIBRATION OF BIAS CURRENT

Abrégé anglais

Post-processing steps for integrating of micro devices into system (receiver)
substrate or
improving the performance of the micro devices after transfer. Post processing
steps for
additional structures such as reflective layers, fillers, black matrix or
other layers may be used to
improve the out coupling or confining of the generated LED light. Dielectric
and metallic layers
may be used to integrate an electro-optical thin film device into the system
substrate with
transferred micro devices. Color conversion layers may be integrated into the
system substrate
to create different outputs from the micro devices.

Revendications

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WHAT IS CLAIMED IS:

1. A method of integrated device fabrication, the integrated device
comprising a plurality
pixels each comprising at least one sub-pixel comprising a micro device
integrated on a
substrate, the method comprising:
extending an active area of a first sub-pixel to an area larger than an area
of a first micro
device of the first sub-pixel by patterning of a filler layer about the first
micro device and
between the first micro device and at least one second micro device.
2. A method according to claim 1 further comprising:
fabricating at least one reflective layer covering at least a portion of one
side of the
patterned filler layer, the reflective layer for confining at least a portion
of incoming or outgoing
light within the active area of the sub-pixel.
3. A method according to claim 2 wherein the reflective layer is fabricated
as an electrode
of the micro device.
4. A method according to claim 1 wherein the patterning of the filler layer
further patterns
the filler layer about a further sub-pixel.
5. A method according to claim 1 wherein the patterning of the filler layer
further is
performed with a dielectric filler material.
6. An integrated device comprising:
a plurality pixels each comprising at least one sub-pixel comprising a micro
device
integrated on a substrate; and
a patterned filler layer formed about a first micro device of a first sub-
pixel and between
the first micro device and at least one second micro device, the patterned
filler layer extending an
active area of the first sub-pixel to an area larger than an area of the first
micro device.


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7. An integrated device according to claim 6 further comprising:
at least one reflective layer covering at least a portion of one side of the
patterned filler
layer, the reflective layer for confining at least a portion of incoming or
outgoing light to the
active area of the first sub-pixel.
8. An integrated device according to claim 7 wherein the reflective layer
is an electrode of
the micro device.
9. An integrated device according to claim 7 wherein the patterned filler
layer is formed
about a further sub-pixel.
10. A method of integrated device fabrication, the device comprising a
plurality pixels each
comprising at least one sub-pixel comprising a micro device integrated on a
substrate, the
method comprising:
integrating at least one micro device into a receiver substrate; and
subsequently to the integration of the at least one micro device, integrating
at least one
thin-film electro-optical device into the receiver substrate.
11. A method according to claim 10, wherein integrating the at least one
thin-film electro-
optical device comprises forming an optical path for the micro device through
all or some layers
of the at least one electro-optical device.
12. A method according to claim 10 wherein integrating the at least one
thin-film electro-
optical device is such that an optical path for the micro device is through a
surface or area of the
integrated device other than a surface or area of the electro-optical device.
13. A method according to claim 10, further comprising fabricating an
electrode of the thin-
film electro-optical device, the electrode of the thin-film electro-optical
device defining an active
area of at least one of a pixel and a sub-pixel.


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14.
A method of according to claim 10, further comprising fabricating an electrode
which
serves as a shared electrode of both the thin-film electro-optical device and
the light emitting
micro device.

Description

CA 02898735 2015-07-29
IGNIS IGNIS
Patents
Hybrid Calibration of Bias Current
,
IGNIS
Innovation Inc.
IGNIS Patents
HYBRID CALIBRATION OF BIAS
CURRENT
Revision: 1.0
2015
2015 IGNIS Innovation Inc., 1

CA 02898735 2015-07-29
IGNIS IGNIS
Patents
Hybrid Calibration of Bias Current
I. Introduction
0
Driver
Figure 1: An embodiment of current-bias voltage-programmed (CBVP) display.
Figure 1 demonstrates an embodiment of current-bias voltage-programmed
display. The pixel is
biased with a current and programmed with video data through a driver. The
main challenge is to
have uniform current sources and lower cost and integrated into the display
panel.
This document describe a family of current source and method of making them
uniform using
existing displays components.
2015 IGNIS Innovation Inc., 2

CA 02898735 2015-07-29
It'
IC NIS IGNIS
Patents
Hybrid Calibration of Bias Current
-0-
00
Ref/Monitor
=
Driver
Figure 2: An embodiment of current-bias voltage-programmed (CBVP) display
using display drivers to
calibrate and control the current sources.
Here, the reference signal used to program (through voltage or reference
current) is used to also
measure the current of each current source. here the ref/monitor line is
coupled to the source or
drain of the transistor (or cascaded transistor structure). The gate of said
transistor (or cascaded
transistor structure) is coupled to the voltage (or current or charge) lines
that can be controlled
individually.
In one method, these lines can be connected to the source driver lines of the
panel. As a result,
the display timing controller program the display with one extra line.
One current sink based on this structure is demonstrated in Figure 3 based on
PMOS transistors.
Using similar principle one can easily make current source with PMOS
transistor. These
2015 IGNIS Innovation Inc., 3

CA 02898735 2015-07-29
IGNIS IGNIS
Patents
Hybrid Calibration of Bias Current
structure can be easily replaced with different types of transistor (PMOS,
NMOS or CMOS) and
different semiconductor materials (e.g. LTPS, Metal Oxide, etc. ).
During the programming, T3 connects the reference line (can be voltage or
current) to the source
of Ti and T2 connects a bias line to the gate of Ti. As a result, the storage
capacitance get
charged to defined value. In one method, after programming the circuit is
reconfigured to
discharge some of the voltage (charge) stored in the at least one of the
storage capacitor as a
function of the main element of the current source (sink) Ti or its related
components. The
calibration time in the Figure 3(b) is foi the discharge purpose. This can be
also eliminated.
!bias
EN __________________________________ T4 CAL
Ref/Monitor
WR =
13
CS
Vbias
= Ti
T2
VSS
Figure 3(a): An embodiment of a current sink using PMOS transistors.
In another method, the output current of the current sink/source can be
measured through the ref/
monitor line. Here, T3 turns ON and redirect the current to the ref/monitor
line which can be
measured outside. Since ref/monitor line can be shared between different
current sink/source,
during measurement all the embodiments are set to zero current except the one
intended for the
measurement.
2015 IGNIS Innovation Inc., 4

CA 02898735 2015-07-29
IGNIS IGNIS
Patents
Hybrid Calibration of Bias Current
Programming
>:
WR
CAL
EN
Calibration
Figure 3(b): An example of timing for controlling the current sink.
Figure 4 shows an example of current source using PMOS transistors. similar
timing as that
shown in Figure 3(b) can be used for this embodiment as well.
2015 IGNIS Innovation Inc., 5

CA 02898735 2015-07-29
IGNIS IGNIS
Patents
Hybrid Calibration of Bias Current
Vdd
= =
CS
= Ti CAL
Ref/Monitor
________________________________ = ______
T3
WR T4
EN
!bias
Figure 4: An embodiment of a current source using PMOS transistors.
2015 IGNIS Innovation Inc., 6